1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 2
3 / { 3 / {
4 pch: bus@10000000 { 4 pch: bus@10000000 {
5 compatible = "simple-bus"; 5 compatible = "simple-bus";
6 #address-cells = <2>; 6 #address-cells = <2>;
7 #size-cells = <2>; 7 #size-cells = <2>;
8 ranges = <0 0x10000000 0 0x100 8 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
9 0 0x20000000 0 9 0 0x20000000 0 0x20000000 0 0x10000000
10 0 0x40000000 0 10 0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */
11 0xe00 0x000000 11 0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>;
12 12
13 pic: interrupt-controller@1000 13 pic: interrupt-controller@10000000 {
14 compatible = "loongson 14 compatible = "loongson,pch-pic-1.0";
15 reg = <0 0x10000000 0 15 reg = <0 0x10000000 0 0x400>;
16 interrupt-controller; 16 interrupt-controller;
17 interrupt-parent = <&h 17 interrupt-parent = <&htvec>;
18 loongson,pic-base-vec 18 loongson,pic-base-vec = <0>;
19 #interrupt-cells = <2> 19 #interrupt-cells = <2>;
20 }; 20 };
21 21
22 rtc0: rtc@100d0100 { 22 rtc0: rtc@100d0100 {
23 compatible = "loongson 23 compatible = "loongson,ls7a-rtc";
24 reg = <0 0x100d0100 0 24 reg = <0 0x100d0100 0 0x78>;
25 interrupt-parent = <&p 25 interrupt-parent = <&pic>;
26 interrupts = <52 IRQ_T 26 interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
27 }; 27 };
28 28
29 ls7a_uart0: serial@10080000 { 29 ls7a_uart0: serial@10080000 {
30 compatible = "ns16550a 30 compatible = "ns16550a";
31 reg = <0 0x10080000 0 31 reg = <0 0x10080000 0 0x100>;
32 clock-frequency = <500 32 clock-frequency = <50000000>;
33 interrupt-parent = <&p 33 interrupt-parent = <&pic>;
34 interrupts = <8 IRQ_TY 34 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
35 no-loopback-test; 35 no-loopback-test;
36 }; 36 };
37 37
38 ls7a_uart1: serial@10080100 { 38 ls7a_uart1: serial@10080100 {
39 status = "disabled"; 39 status = "disabled";
40 compatible = "ns16550a 40 compatible = "ns16550a";
41 reg = <0 0x10080100 0 41 reg = <0 0x10080100 0 0x100>;
42 clock-frequency = <500 42 clock-frequency = <50000000>;
43 interrupt-parent = <&p 43 interrupt-parent = <&pic>;
44 interrupts = <8 IRQ_TY 44 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
45 no-loopback-test; 45 no-loopback-test;
46 }; 46 };
47 47
48 ls7a_uart2: serial@10080200 { 48 ls7a_uart2: serial@10080200 {
49 status = "disabled"; 49 status = "disabled";
50 compatible = "ns16550a 50 compatible = "ns16550a";
51 reg = <0 0x10080200 0 51 reg = <0 0x10080200 0 0x100>;
52 clock-frequency = <500 52 clock-frequency = <50000000>;
53 interrupt-parent = <&p 53 interrupt-parent = <&pic>;
54 interrupts = <8 IRQ_TY 54 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
55 no-loopback-test; 55 no-loopback-test;
56 }; 56 };
57 57
58 ls7a_uart3: serial@10080300 { 58 ls7a_uart3: serial@10080300 {
59 status = "disabled"; 59 status = "disabled";
60 compatible = "ns16550a 60 compatible = "ns16550a";
61 reg = <0 0x10080300 0 61 reg = <0 0x10080300 0 0x100>;
62 clock-frequency = <500 62 clock-frequency = <50000000>;
63 interrupt-parent = <&p 63 interrupt-parent = <&pic>;
64 interrupts = <8 IRQ_TY 64 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
65 no-loopback-test; 65 no-loopback-test;
66 }; 66 };
67 67
68 pci@1a000000 { 68 pci@1a000000 {
69 compatible = "loongson 69 compatible = "loongson,ls7a-pci";
70 device_type = "pci"; 70 device_type = "pci";
71 #address-cells = <3>; 71 #address-cells = <3>;
72 #size-cells = <2>; 72 #size-cells = <2>;
73 #interrupt-cells = <2> 73 #interrupt-cells = <2>;
74 msi-parent = <&msi>; 74 msi-parent = <&msi>;
75 75
76 reg = <0 0x1a000000 0 76 reg = <0 0x1a000000 0 0x02000000>,
77 <0xefe 0x00000 77 <0xefe 0x00000000 0 0x20000000>;
78 78
79 ranges = <0x01000000 0 79 ranges = <0x01000000 0x0 0x00020000 0x0 0x18020000 0x0 0x00020000>,
80 <0x02000000 0 80 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
81 81
82 ohci@4,0 { 82 ohci@4,0 {
83 compatible = " 83 compatible = "pci0014,7a24.0",
84 84 "pci0014,7a24",
85 85 "pciclass0c0310",
86 86 "pciclass0c03";
87 87
88 reg = <0x2000 88 reg = <0x2000 0x0 0x0 0x0 0x0>;
89 interrupts = < 89 interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
90 interrupt-pare 90 interrupt-parent = <&pic>;
91 }; 91 };
92 92
93 ehci@4,1 { 93 ehci@4,1 {
94 compatible = " 94 compatible = "pci0014,7a14.0",
95 95 "pci0014,7a14",
96 96 "pciclass0c0320",
97 97 "pciclass0c03";
98 98
99 reg = <0x2100 99 reg = <0x2100 0x0 0x0 0x0 0x0>;
100 interrupts = < 100 interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
101 interrupt-pare 101 interrupt-parent = <&pic>;
102 }; 102 };
103 103
104 ohci@5,0 { 104 ohci@5,0 {
105 compatible = " 105 compatible = "pci0014,7a24.0",
106 106 "pci0014,7a24",
107 107 "pciclass0c0310",
108 108 "pciclass0c03";
109 109
110 reg = <0x2800 110 reg = <0x2800 0x0 0x0 0x0 0x0>;
111 interrupts = < 111 interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
112 interrupt-pare 112 interrupt-parent = <&pic>;
113 }; 113 };
114 114
115 ehci@5,1 { 115 ehci@5,1 {
116 compatible = " 116 compatible = "pci0014,7a14.0",
117 117 "pci0014,7a14",
118 118 "pciclass0c0320",
119 119 "pciclass0c03";
120 120
121 reg = <0x2900 121 reg = <0x2900 0x0 0x0 0x0 0x0>;
122 interrupts = < 122 interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
123 interrupt-pare 123 interrupt-parent = <&pic>;
124 }; 124 };
125 125
126 sata@8,0 { 126 sata@8,0 {
127 compatible = " 127 compatible = "pci0014,7a08.0",
128 128 "pci0014,7a08",
129 129 "pciclass010601",
130 130 "pciclass0106";
131 131
132 reg = <0x4000 132 reg = <0x4000 0x0 0x0 0x0 0x0>;
133 interrupts = < 133 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-pare 134 interrupt-parent = <&pic>;
135 }; 135 };
136 136
137 sata@8,1 { 137 sata@8,1 {
138 compatible = " 138 compatible = "pci0014,7a08.0",
139 139 "pci0014,7a08",
140 140 "pciclass010601",
141 141 "pciclass0106";
142 142
143 reg = <0x4100 143 reg = <0x4100 0x0 0x0 0x0 0x0>;
144 interrupts = < 144 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
145 interrupt-pare 145 interrupt-parent = <&pic>;
146 }; 146 };
147 147
148 sata@8,2 { 148 sata@8,2 {
149 compatible = " 149 compatible = "pci0014,7a08.0",
150 150 "pci0014,7a08",
151 151 "pciclass010601",
152 152 "pciclass0106";
153 153
154 reg = <0x4200 154 reg = <0x4200 0x0 0x0 0x0 0x0>;
155 interrupts = < 155 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
156 interrupt-pare 156 interrupt-parent = <&pic>;
157 }; 157 };
158 158
159 gpu@6,0 { 159 gpu@6,0 {
160 compatible = " 160 compatible = "pci0014,7a15.0",
161 161 "pci0014,7a15",
162 162 "pciclass030200",
163 163 "pciclass0302";
164 164
165 reg = <0x3000 165 reg = <0x3000 0x0 0x0 0x0 0x0>;
166 interrupts = < 166 interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
167 interrupt-pare 167 interrupt-parent = <&pic>;
168 }; 168 };
169 169
170 dc@6,1 { 170 dc@6,1 {
171 compatible = " 171 compatible = "pci0014,7a06.0",
172 172 "pci0014,7a06",
173 173 "pciclass030000",
174 174 "pciclass0300";
175 175
176 reg = <0x3100 176 reg = <0x3100 0x0 0x0 0x0 0x0>;
177 interrupts = < 177 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-pare 178 interrupt-parent = <&pic>;
179 }; 179 };
180 180
181 hda@7,0 { 181 hda@7,0 {
182 compatible = " 182 compatible = "pci0014,7a07.0",
183 183 "pci0014,7a07",
184 184 "pciclass040300",
185 185 "pciclass0403";
186 186
187 reg = <0x3800 187 reg = <0x3800 0x0 0x0 0x0 0x0>;
188 interrupts = < 188 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
189 interrupt-pare 189 interrupt-parent = <&pic>;
190 }; 190 };
191 191
192 gmac@3,0 { 192 gmac@3,0 {
193 compatible = " 193 compatible = "pci0014,7a03.0",
194 194 "pci0014,7a03",
195 195 "pciclass020000",
196 196 "pciclass0200";
197 197
198 reg = <0x1800 198 reg = <0x1800 0x0 0x0 0x0 0x0>;
199 interrupts = < 199 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
200 < 200 <13 IRQ_TYPE_LEVEL_HIGH>;
201 interrupt-name 201 interrupt-names = "macirq", "eth_lpi";
202 interrupt-pare 202 interrupt-parent = <&pic>;
203 phy-mode = "rg 203 phy-mode = "rgmii";
204 mdio { 204 mdio {
205 #addre 205 #address-cells = <1>;
206 #size- 206 #size-cells = <0>;
207 compat 207 compatible = "snps,dwmac-mdio";
208 phy0: 208 phy0: ethernet-phy@0 {
209 209 reg = <0>;
210 }; 210 };
211 }; 211 };
212 }; 212 };
213 213
214 gmac@3,1 { 214 gmac@3,1 {
215 compatible = " 215 compatible = "pci0014,7a03.0",
216 216 "pci0014,7a03",
217 217 "pciclass020000",
218 218 "pciclass0200",
219 219 "loongson, pci-gmac";
220 220
221 reg = <0x1900 221 reg = <0x1900 0x0 0x0 0x0 0x0>;
222 interrupts = < 222 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
223 < 223 <15 IRQ_TYPE_LEVEL_HIGH>;
224 interrupt-name 224 interrupt-names = "macirq", "eth_lpi";
225 interrupt-pare 225 interrupt-parent = <&pic>;
226 phy-mode = "rg 226 phy-mode = "rgmii";
227 mdio { 227 mdio {
228 #addre 228 #address-cells = <1>;
229 #size- 229 #size-cells = <0>;
230 compat 230 compatible = "snps,dwmac-mdio";
231 phy1: 231 phy1: ethernet-phy@1 {
232 232 reg = <0>;
233 }; 233 };
234 }; 234 };
235 }; 235 };
236 236
237 pci_bridge@9,0 { 237 pci_bridge@9,0 {
238 compatible = " 238 compatible = "pci0014,7a19.1",
239 239 "pci0014,7a19",
240 240 "pciclass060400",
241 241 "pciclass0604";
242 242
243 reg = <0x4800 243 reg = <0x4800 0x0 0x0 0x0 0x0>;
244 interrupts = < 244 interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
245 interrupt-pare 245 interrupt-parent = <&pic>;
246 246
247 #interrupt-cel 247 #interrupt-cells = <1>;
248 interrupt-map- 248 interrupt-map-mask = <0 0 0 0>;
249 interrupt-map 249 interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;
250 }; 250 };
251 251
252 pci_bridge@a,0 { 252 pci_bridge@a,0 {
253 compatible = " 253 compatible = "pci0014,7a09.1",
254 254 "pci0014,7a09",
255 255 "pciclass060400",
256 256 "pciclass0604";
257 257
258 reg = <0x5000 258 reg = <0x5000 0x0 0x0 0x0 0x0>;
259 interrupts = < 259 interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
260 interrupt-pare 260 interrupt-parent = <&pic>;
261 261
262 #interrupt-cel 262 #interrupt-cells = <1>;
263 interrupt-map- 263 interrupt-map-mask = <0 0 0 0>;
264 interrupt-map 264 interrupt-map = <0 0 0 0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;
265 }; 265 };
266 266
267 pci_bridge@b,0 { 267 pci_bridge@b,0 {
268 compatible = " 268 compatible = "pci0014,7a09.1",
269 269 "pci0014,7a09",
270 270 "pciclass060400",
271 271 "pciclass0604";
272 272
273 reg = <0x5800 273 reg = <0x5800 0x0 0x0 0x0 0x0>;
274 interrupts = < 274 interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
275 interrupt-pare 275 interrupt-parent = <&pic>;
276 276
277 #interrupt-cel 277 #interrupt-cells = <1>;
278 interrupt-map- 278 interrupt-map-mask = <0 0 0 0>;
279 interrupt-map 279 interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
280 }; 280 };
281 281
282 pci_bridge@c,0 { 282 pci_bridge@c,0 {
283 compatible = " 283 compatible = "pci0014,7a09.1",
284 284 "pci0014,7a09",
285 285 "pciclass060400",
286 286 "pciclass0604";
287 287
288 reg = <0x6000 288 reg = <0x6000 0x0 0x0 0x0 0x0>;
289 interrupts = < 289 interrupts = <35 IRQ_TYPE_LEVEL_HIGH>;
290 interrupt-pare 290 interrupt-parent = <&pic>;
291 291
292 #interrupt-cel 292 #interrupt-cells = <1>;
293 interrupt-map- 293 interrupt-map-mask = <0 0 0 0>;
294 interrupt-map 294 interrupt-map = <0 0 0 0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;
295 }; 295 };
296 296
297 pci_bridge@d,0 { 297 pci_bridge@d,0 {
298 compatible = " 298 compatible = "pci0014,7a19.1",
299 299 "pci0014,7a19",
300 300 "pciclass060400",
301 301 "pciclass0604";
302 302
303 reg = <0x6800 303 reg = <0x6800 0x0 0x0 0x0 0x0>;
304 interrupts = < 304 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
305 interrupt-pare 305 interrupt-parent = <&pic>;
306 306
307 #interrupt-cel 307 #interrupt-cells = <1>;
308 interrupt-map- 308 interrupt-map-mask = <0 0 0 0>;
309 interrupt-map 309 interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
310 }; 310 };
311 311
312 pci_bridge@e,0 { 312 pci_bridge@e,0 {
313 compatible = " 313 compatible = "pci0014,7a09.1",
314 314 "pci0014,7a09",
315 315 "pciclass060400",
316 316 "pciclass0604";
317 317
318 reg = <0x7000 318 reg = <0x7000 0x0 0x0 0x0 0x0>;
319 interrupts = < 319 interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
320 interrupt-pare 320 interrupt-parent = <&pic>;
321 321
322 #interrupt-cel 322 #interrupt-cells = <1>;
323 interrupt-map- 323 interrupt-map-mask = <0 0 0 0>;
324 interrupt-map 324 interrupt-map = <0 0 0 0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;
325 }; 325 };
326 326
327 pci_bridge@f,0 { 327 pci_bridge@f,0 {
328 compatible = " 328 compatible = "pci0014,7a29.1",
329 329 "pci0014,7a29",
330 330 "pciclass060400",
331 331 "pciclass0604";
332 332
333 reg = <0x7800 333 reg = <0x7800 0x0 0x0 0x0 0x0>;
334 interrupts = < 334 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
335 interrupt-pare 335 interrupt-parent = <&pic>;
336 336
337 #interrupt-cel 337 #interrupt-cells = <1>;
338 interrupt-map- 338 interrupt-map-mask = <0 0 0 0>;
339 interrupt-map 339 interrupt-map = <0 0 0 0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;
340 }; 340 };
341 341
342 pci_bridge@10,0 { 342 pci_bridge@10,0 {
343 compatible = " 343 compatible = "pci0014,7a19.1",
344 344 "pci0014,7a19",
345 345 "pciclass060400",
346 346 "pciclass0604";
347 347
348 reg = <0x8000 348 reg = <0x8000 0x0 0x0 0x0 0x0>;
349 interrupts = < 349 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
350 interrupt-pare 350 interrupt-parent = <&pic>;
351 351
352 #interrupt-cel 352 #interrupt-cells = <1>;
353 interrupt-map- 353 interrupt-map-mask = <0 0 0 0>;
354 interrupt-map 354 interrupt-map = <0 0 0 0 &pic 41 IRQ_TYPE_LEVEL_HIGH>;
355 }; 355 };
356 356
357 pci_bridge@11,0 { 357 pci_bridge@11,0 {
358 compatible = " 358 compatible = "pci0014,7a29.1",
359 359 "pci0014,7a29",
360 360 "pciclass060400",
361 361 "pciclass0604";
362 362
363 reg = <0x8800 363 reg = <0x8800 0x0 0x0 0x0 0x0>;
364 interrupts = < 364 interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
365 interrupt-pare 365 interrupt-parent = <&pic>;
366 366
367 #interrupt-cel 367 #interrupt-cells = <1>;
368 interrupt-map- 368 interrupt-map-mask = <0 0 0 0>;
369 interrupt-map 369 interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>;
370 }; 370 };
371 371
372 pci_bridge@12,0 { 372 pci_bridge@12,0 {
373 compatible = " 373 compatible = "pci0014,7a19.1",
374 374 "pci0014,7a19",
375 375 "pciclass060400",
376 376 "pciclass0604";
377 377
378 reg = <0x9000 378 reg = <0x9000 0x0 0x0 0x0 0x0>;
379 interrupts = < 379 interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
380 interrupt-pare 380 interrupt-parent = <&pic>;
381 381
382 #interrupt-cel 382 #interrupt-cells = <1>;
383 interrupt-map- 383 interrupt-map-mask = <0 0 0 0>;
384 interrupt-map 384 interrupt-map = <0 0 0 0 &pic 43 IRQ_TYPE_LEVEL_HIGH>;
385 }; 385 };
386 386
387 pci_bridge@13,0 { 387 pci_bridge@13,0 {
388 compatible = " 388 compatible = "pci0014,7a29.1",
389 389 "pci0014,7a29",
390 390 "pciclass060400",
391 391 "pciclass0604";
392 392
393 reg = <0x9800 393 reg = <0x9800 0x0 0x0 0x0 0x0>;
394 interrupts = < 394 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
395 interrupt-pare 395 interrupt-parent = <&pic>;
396 396
397 #interrupt-cel 397 #interrupt-cells = <1>;
398 interrupt-map- 398 interrupt-map-mask = <0 0 0 0>;
399 interrupt-map 399 interrupt-map = <0 0 0 0 &pic 38 IRQ_TYPE_LEVEL_HIGH>;
400 }; 400 };
401 401
402 pci_bridge@14,0 { 402 pci_bridge@14,0 {
403 compatible = " 403 compatible = "pci0014,7a19.1",
404 404 "pci0014,7a19",
405 405 "pciclass060400",
406 406 "pciclass0604";
407 407
408 reg = <0xa000 408 reg = <0xa000 0x0 0x0 0x0 0x0>;
409 interrupts = < 409 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
410 interrupt-pare 410 interrupt-parent = <&pic>;
411 411
412 #interrupt-cel 412 #interrupt-cells = <1>;
413 interrupt-map- 413 interrupt-map-mask = <0 0 0 0>;
414 interrupt-map 414 interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>;
415 }; 415 };
416 }; 416 };
417 417
418 isa@18000000 { 418 isa@18000000 {
419 compatible = "isa"; 419 compatible = "isa";
420 #address-cells = <2>; 420 #address-cells = <2>;
421 #size-cells = <1>; 421 #size-cells = <1>;
422 ranges = <1 0 0 0x1800 422 ranges = <1 0 0 0x18000000 0x20000>;
423 }; 423 };
424 }; 424 };
425 }; 425 };
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