1 // SPDX-License-Identifier: GPL-2.0-only OR BS 1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2 /* 2 /*
3 * Copyright 2023 Mobileye Vision Technologies 3 * Copyright 2023 Mobileye Vision Technologies Ltd.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/mip 6 #include <dt-bindings/interrupt-controller/mips-gic.h>
7 7
8 #include "eyeq5-clocks.dtsi" 8 #include "eyeq5-clocks.dtsi"
9 9
10 / { 10 / {
11 #address-cells = <2>; 11 #address-cells = <2>;
12 #size-cells = <2>; 12 #size-cells = <2>;
13 cpus { 13 cpus {
14 #address-cells = <1>; 14 #address-cells = <1>;
15 #size-cells = <0>; 15 #size-cells = <0>;
16 cpu@0 { 16 cpu@0 {
17 device_type = "cpu"; 17 device_type = "cpu";
18 compatible = "img,i650 18 compatible = "img,i6500";
19 reg = <0>; 19 reg = <0>;
20 clocks = <&core0_clk>; 20 clocks = <&core0_clk>;
21 }; 21 };
22 }; 22 };
23 23
24 reserved-memory { 24 reserved-memory {
25 #address-cells = <2>; 25 #address-cells = <2>;
26 #size-cells = <2>; 26 #size-cells = <2>;
27 ranges; 27 ranges;
28 28
29 /* These reserved memory regio 29 /* These reserved memory regions are also defined in bootmanager
30 * for configuring inbound tran 30 * for configuring inbound translation for BARS, don't change
31 * these without syncing with b 31 * these without syncing with bootmanager
32 */ 32 */
33 shmem0_reserved: shmem@8040000 33 shmem0_reserved: shmem@804000000 {
34 reg = <0x8 0x04000000 34 reg = <0x8 0x04000000 0x0 0x1000000>;
35 }; 35 };
36 shmem1_reserved: shmem@8050000 36 shmem1_reserved: shmem@805000000 {
37 reg = <0x8 0x05000000 37 reg = <0x8 0x05000000 0x0 0x1000000>;
38 }; 38 };
39 pci0_msi_reserved: pci0-msi@80 39 pci0_msi_reserved: pci0-msi@806000000 {
40 reg = <0x8 0x06000000 40 reg = <0x8 0x06000000 0x0 0x100000>;
41 }; 41 };
42 pci1_msi_reserved: pci1-msi@80 42 pci1_msi_reserved: pci1-msi@806100000 {
43 reg = <0x8 0x06100000 43 reg = <0x8 0x06100000 0x0 0x100000>;
44 }; 44 };
45 45
46 mini_coredump0_reserved: mini- 46 mini_coredump0_reserved: mini-coredump0@806200000 {
47 reg = <0x8 0x06200000 47 reg = <0x8 0x06200000 0x0 0x100000>;
48 }; 48 };
49 mhm_reserved_0: the-mhm-reserv 49 mhm_reserved_0: the-mhm-reserved-0@0 {
50 reg = <0x8 0x00000000 50 reg = <0x8 0x00000000 0x0 0x0000800>;
51 }; 51 };
52 }; 52 };
53 53
54 aliases { 54 aliases {
55 serial0 = &uart0; 55 serial0 = &uart0;
56 serial1 = &uart1; 56 serial1 = &uart1;
57 serial2 = &uart2; 57 serial2 = &uart2;
58 }; 58 };
59 59
60 cpu_intc: interrupt-controller { 60 cpu_intc: interrupt-controller {
61 compatible = "mti,cpu-interrup 61 compatible = "mti,cpu-interrupt-controller";
62 interrupt-controller; 62 interrupt-controller;
63 #address-cells = <0>; 63 #address-cells = <0>;
64 #interrupt-cells = <1>; 64 #interrupt-cells = <1>;
65 }; 65 };
66 66
67 soc: soc { 67 soc: soc {
68 #address-cells = <2>; 68 #address-cells = <2>;
69 #size-cells = <2>; 69 #size-cells = <2>;
70 ranges; 70 ranges;
71 compatible = "simple-bus"; 71 compatible = "simple-bus";
72 72
73 uart0: serial@800000 { 73 uart0: serial@800000 {
74 compatible = "arm,pl01 74 compatible = "arm,pl011", "arm,primecell";
75 reg = <0 0x800000 0x0 75 reg = <0 0x800000 0x0 0x1000>;
76 reg-io-width = <4>; 76 reg-io-width = <4>;
77 interrupt-parent = <&g 77 interrupt-parent = <&gic>;
78 interrupts = <GIC_SHAR 78 interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
79 clocks = <&uart_clk>, 79 clocks = <&uart_clk>, <&occ_periph>;
80 clock-names = "uartclk 80 clock-names = "uartclk", "apb_pclk";
81 resets = <&olb 0 10>; 81 resets = <&olb 0 10>;
82 pinctrl-names = "defau 82 pinctrl-names = "default";
83 pinctrl-0 = <&uart0_pi 83 pinctrl-0 = <&uart0_pins>;
84 }; 84 };
85 85
86 uart1: serial@900000 { 86 uart1: serial@900000 {
87 compatible = "arm,pl01 87 compatible = "arm,pl011", "arm,primecell";
88 reg = <0 0x900000 0x0 88 reg = <0 0x900000 0x0 0x1000>;
89 reg-io-width = <4>; 89 reg-io-width = <4>;
90 interrupt-parent = <&g 90 interrupt-parent = <&gic>;
91 interrupts = <GIC_SHAR 91 interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
92 clocks = <&uart_clk>, 92 clocks = <&uart_clk>, <&occ_periph>;
93 clock-names = "uartclk 93 clock-names = "uartclk", "apb_pclk";
94 resets = <&olb 0 11>; 94 resets = <&olb 0 11>;
95 pinctrl-names = "defau 95 pinctrl-names = "default";
96 pinctrl-0 = <&uart1_pi 96 pinctrl-0 = <&uart1_pins>;
97 }; 97 };
98 98
99 uart2: serial@a00000 { 99 uart2: serial@a00000 {
100 compatible = "arm,pl01 100 compatible = "arm,pl011", "arm,primecell";
101 reg = <0 0xa00000 0x0 101 reg = <0 0xa00000 0x0 0x1000>;
102 reg-io-width = <4>; 102 reg-io-width = <4>;
103 interrupt-parent = <&g 103 interrupt-parent = <&gic>;
104 interrupts = <GIC_SHAR 104 interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
105 clocks = <&uart_clk>, 105 clocks = <&uart_clk>, <&occ_periph>;
106 clock-names = "uartclk 106 clock-names = "uartclk", "apb_pclk";
107 resets = <&olb 0 12>; 107 resets = <&olb 0 12>;
108 pinctrl-names = "defau 108 pinctrl-names = "default";
109 pinctrl-0 = <&uart2_pi 109 pinctrl-0 = <&uart2_pins>;
110 }; 110 };
111 111
112 olb: system-controller@e00000 112 olb: system-controller@e00000 {
113 compatible = "mobileye 113 compatible = "mobileye,eyeq5-olb", "syscon";
114 reg = <0 0xe00000 0x0 114 reg = <0 0xe00000 0x0 0x400>;
115 #reset-cells = <2>; 115 #reset-cells = <2>;
116 #clock-cells = <1>; 116 #clock-cells = <1>;
117 clocks = <&xtal>; 117 clocks = <&xtal>;
118 clock-names = "ref"; 118 clock-names = "ref";
119 }; 119 };
120 120
121 gic: interrupt-controller@1400 121 gic: interrupt-controller@140000 {
122 compatible = "mti,gic" 122 compatible = "mti,gic";
123 reg = <0x0 0x140000 0x 123 reg = <0x0 0x140000 0x0 0x20000>;
124 interrupt-controller; 124 interrupt-controller;
125 #interrupt-cells = <3> 125 #interrupt-cells = <3>;
126 126
127 /* 127 /*
128 * Declare the interrup 128 * Declare the interrupt-parent even though the mti,gic
129 * binding doesn't requ 129 * binding doesn't require it, such that the kernel can
130 * figure out that cpu_ 130 * figure out that cpu_intc is the root interrupt
131 * controller & should 131 * controller & should be probed first.
132 */ 132 */
133 interrupt-parent = <&c 133 interrupt-parent = <&cpu_intc>;
134 134
135 timer { 135 timer {
136 compatible = " 136 compatible = "mti,gic-timer";
137 interrupts = < 137 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
138 clocks = <&cor 138 clocks = <&core0_clk>;
139 }; 139 };
140 }; 140 };
141 }; 141 };
142 }; 142 };
143 143
144 #include "eyeq5-pins.dtsi" 144 #include "eyeq5-pins.dtsi"
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