Linux/scripts/dtc/include-prefixes/mips/mscc/ocelot.dtsi

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

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1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2017 Microsemi Corporation */ 2 /* Copyright (c) 2017 Microsemi Corporation */ 3 3 4 / { 4 / { 5 #address-cells = <1>; 5 #address-cells = <1>; 6 #size-cells = <1>; 6 #size-cells = <1>; 7 compatible = "mscc,ocelot"; 7 compatible = "mscc,ocelot"; 8 8 9 cpus { 9 cpus { 10 #address-cells = <1>; 10 #address-cells = <1>; 11 #size-cells = <0>; 11 #size-cells = <0>; 12 12 13 cpu@0 { 13 cpu@0 { 14 compatible = "mips,mip 14 compatible = "mips,mips24KEc"; 15 device_type = "cpu"; 15 device_type = "cpu"; 16 clocks = <&cpu_clk>; 16 clocks = <&cpu_clk>; 17 reg = <0>; 17 reg = <0>; 18 }; 18 }; 19 }; 19 }; 20 20 21 aliases { 21 aliases { 22 serial0 = &uart0; 22 serial0 = &uart0; 23 }; 23 }; 24 24 25 cpuintc: interrupt-controller { 25 cpuintc: interrupt-controller { 26 #address-cells = <0>; 26 #address-cells = <0>; 27 #interrupt-cells = <1>; 27 #interrupt-cells = <1>; 28 interrupt-controller; 28 interrupt-controller; 29 compatible = "mti,cpu-interrup 29 compatible = "mti,cpu-interrupt-controller"; 30 }; 30 }; 31 31 32 cpu_clk: cpu-clock { 32 cpu_clk: cpu-clock { 33 compatible = "fixed-clock"; 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 34 #clock-cells = <0>; 35 clock-frequency = <500000000>; 35 clock-frequency = <500000000>; 36 }; 36 }; 37 37 38 ahb_clk: ahb-clk { 38 ahb_clk: ahb-clk { 39 compatible = "fixed-factor-clo 39 compatible = "fixed-factor-clock"; 40 #clock-cells = <0>; 40 #clock-cells = <0>; 41 clocks = <&cpu_clk>; 41 clocks = <&cpu_clk>; 42 clock-div = <2>; 42 clock-div = <2>; 43 clock-mult = <1>; 43 clock-mult = <1>; 44 }; 44 }; 45 45 46 ahb@70000000 { 46 ahb@70000000 { 47 compatible = "simple-bus"; 47 compatible = "simple-bus"; 48 #address-cells = <1>; 48 #address-cells = <1>; 49 #size-cells = <1>; 49 #size-cells = <1>; 50 ranges = <0 0x70000000 0x20000 50 ranges = <0 0x70000000 0x2000000>; 51 51 52 interrupt-parent = <&intc>; 52 interrupt-parent = <&intc>; 53 53 54 cpu_ctrl: syscon@0 { 54 cpu_ctrl: syscon@0 { 55 compatible = "mscc,oce 55 compatible = "mscc,ocelot-cpu-syscon", "syscon"; 56 reg = <0x0 0x2c>; 56 reg = <0x0 0x2c>; 57 }; 57 }; 58 58 59 intc: interrupt-controller@70 59 intc: interrupt-controller@70 { 60 compatible = "mscc,oce 60 compatible = "mscc,ocelot-icpu-intr"; 61 reg = <0x70 0x70>; 61 reg = <0x70 0x70>; 62 #interrupt-cells = <1> 62 #interrupt-cells = <1>; 63 interrupt-controller; 63 interrupt-controller; 64 interrupt-parent = <&c 64 interrupt-parent = <&cpuintc>; 65 interrupts = <2>; 65 interrupts = <2>; 66 }; 66 }; 67 67 68 uart0: serial@100000 { 68 uart0: serial@100000 { 69 pinctrl-0 = <&uart_pin 69 pinctrl-0 = <&uart_pins>; 70 pinctrl-names = "defau 70 pinctrl-names = "default"; 71 compatible = "ns16550a 71 compatible = "ns16550a"; 72 reg = <0x100000 0x20>; 72 reg = <0x100000 0x20>; 73 interrupts = <6>; 73 interrupts = <6>; 74 clocks = <&ahb_clk>; 74 clocks = <&ahb_clk>; 75 reg-io-width = <4>; 75 reg-io-width = <4>; 76 reg-shift = <2>; 76 reg-shift = <2>; 77 77 78 status = "disabled"; 78 status = "disabled"; 79 }; 79 }; 80 80 81 i2c: i2c@100400 { << 82 compatible = "mscc,oce << 83 pinctrl-0 = <&i2c_pins << 84 pinctrl-names = "defau << 85 reg = <0x100400 0x100> << 86 #address-cells = <1>; << 87 #size-cells = <0>; << 88 interrupts = <8>; << 89 clocks = <&ahb_clk>; << 90 << 91 status = "disabled"; << 92 }; << 93 << 94 uart2: serial@100800 { 81 uart2: serial@100800 { 95 pinctrl-0 = <&uart2_pi 82 pinctrl-0 = <&uart2_pins>; 96 pinctrl-names = "defau 83 pinctrl-names = "default"; 97 compatible = "ns16550a 84 compatible = "ns16550a"; 98 reg = <0x100800 0x20>; 85 reg = <0x100800 0x20>; 99 interrupts = <7>; 86 interrupts = <7>; 100 clocks = <&ahb_clk>; 87 clocks = <&ahb_clk>; 101 reg-io-width = <4>; 88 reg-io-width = <4>; 102 reg-shift = <2>; 89 reg-shift = <2>; 103 90 104 status = "disabled"; 91 status = "disabled"; 105 }; 92 }; 106 93 107 spi: spi@101000 { << 108 compatible = "mscc,oce << 109 #address-cells = <1>; << 110 #size-cells = <0>; << 111 reg = <0x101000 0x100> << 112 interrupts = <9>; << 113 clocks = <&ahb_clk>; << 114 << 115 status = "disabled"; << 116 }; << 117 << 118 switch@1010000 { << 119 compatible = "mscc,vsc << 120 reg = <0x1010000 0x100 << 121 <0x1030000 0x100 << 122 <0x1080000 0x100 << 123 <0x10e0000 0x100 << 124 <0x11e0000 0x100 << 125 <0x11f0000 0x100 << 126 <0x1200000 0x100 << 127 <0x1210000 0x100 << 128 <0x1220000 0x100 << 129 <0x1230000 0x100 << 130 <0x1240000 0x100 << 131 <0x1250000 0x100 << 132 <0x1260000 0x100 << 133 <0x1270000 0x100 << 134 <0x1280000 0x100 << 135 <0x1800000 0x800 << 136 <0x1880000 0x100 << 137 <0x1040000 0x100 << 138 <0x1050000 0x100 << 139 <0x1060000 0x100 << 140 <0x1a0 0x1c4>; << 141 reg-names = "sys", "re << 142 "port2", " << 143 "port7", " << 144 "ana", "s0 << 145 interrupts = <18 21 22 << 146 interrupt-names = "ptp << 147 << 148 ethernet-ports { << 149 #address-cells << 150 #size-cells = << 151 << 152 port0: port@0 << 153 reg = << 154 status << 155 }; << 156 port1: port@1 << 157 reg = << 158 status << 159 }; << 160 port2: port@2 << 161 reg = << 162 status << 163 }; << 164 port3: port@3 << 165 reg = << 166 status << 167 }; << 168 port4: port@4 << 169 reg = << 170 status << 171 }; << 172 port5: port@5 << 173 reg = << 174 status << 175 }; << 176 port6: port@6 << 177 reg = << 178 status << 179 }; << 180 port7: port@7 << 181 reg = << 182 status << 183 }; << 184 port8: port@8 << 185 reg = << 186 status << 187 }; << 188 port9: port@9 << 189 reg = << 190 status << 191 }; << 192 port10: port@1 << 193 reg = << 194 status << 195 }; << 196 }; << 197 }; << 198 << 199 reset@1070008 { 94 reset@1070008 { 200 compatible = "mscc,oce 95 compatible = "mscc,ocelot-chip-reset"; 201 reg = <0x1070008 0x4>; 96 reg = <0x1070008 0x4>; 202 }; 97 }; 203 98 204 gpio: pinctrl@1070034 { 99 gpio: pinctrl@1070034 { 205 compatible = "mscc,oce 100 compatible = "mscc,ocelot-pinctrl"; 206 reg = <0x1070034 0x68> 101 reg = <0x1070034 0x68>; 207 gpio-controller; 102 gpio-controller; 208 #gpio-cells = <2>; 103 #gpio-cells = <2>; 209 gpio-ranges = <&gpio 0 104 gpio-ranges = <&gpio 0 0 22>; 210 interrupt-controller; << 211 interrupts = <13>; << 212 #interrupt-cells = <2> << 213 << 214 i2c_pins: i2c-pins { << 215 pins = "GPIO_1 << 216 function = "tw << 217 }; << 218 105 219 uart_pins: uart-pins { 106 uart_pins: uart-pins { 220 pins = "GPIO_6 107 pins = "GPIO_6", "GPIO_7"; 221 function = "ua 108 function = "uart"; 222 }; 109 }; 223 110 224 uart2_pins: uart2-pins 111 uart2_pins: uart2-pins { 225 pins = "GPIO_1 112 pins = "GPIO_12", "GPIO_13"; 226 function = "ua 113 function = "uart2"; 227 }; << 228 << 229 miim1_pins: miim1-pins << 230 pins = "GPIO_1 << 231 function = "mi << 232 }; << 233 << 234 }; << 235 << 236 mdio0: mdio@107009c { << 237 #address-cells = <1>; << 238 #size-cells = <0>; << 239 compatible = "mscc,oce << 240 reg = <0x107009c 0x24> << 241 interrupts = <14>; << 242 status = "disabled"; << 243 << 244 phy0: ethernet-phy@0 { << 245 reg = <0>; << 246 }; << 247 phy1: ethernet-phy@1 { << 248 reg = <1>; << 249 }; << 250 phy2: ethernet-phy@2 { << 251 reg = <2>; << 252 }; << 253 phy3: ethernet-phy@3 { << 254 reg = <3>; << 255 }; << 256 }; << 257 << 258 mdio1: mdio@10700c0 { << 259 #address-cells = <1>; << 260 #size-cells = <0>; << 261 compatible = "mscc,oce << 262 reg = <0x10700c0 0x24> << 263 interrupts = <15>; << 264 pinctrl-names = "defau << 265 pinctrl-0 = <&miim1_pi << 266 status = "disabled"; << 267 }; << 268 << 269 hsio: syscon@10d0000 { << 270 compatible = "mscc,oce << 271 reg = <0x10d0000 0x100 << 272 << 273 serdes: serdes { << 274 compatible = " << 275 #phy-cells = < << 276 }; 114 }; 277 }; 115 }; 278 }; 116 }; 279 }; 117 };

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Linux/scripts/dtc/include-prefixes/mips/mscc/ocelot.dtsi

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Differences between /scripts/dtc/include-prefixes/mips/mscc/ocelot.dtsi (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/mips/mscc/ocelot.dtsi (Version linux-4.17.19)

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Differences between /scripts/dtc/include-prefixes/mips/mscc/ocelot.dtsi (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/mips/mscc/ocelot.dtsi (Version linux-4.17.19)

TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/mips/mscc/ocelot.dtsi