1 // SPDX-License-Identifier: GPL-2.0 <<
2 #include <dt-bindings/clock/ath79-clk.h> 1 #include <dt-bindings/clock/ath79-clk.h>
3 2
4 / { 3 / {
5 compatible = "qca,ar9132"; 4 compatible = "qca,ar9132";
6 5
7 #address-cells = <1>; 6 #address-cells = <1>;
8 #size-cells = <1>; 7 #size-cells = <1>;
9 8
10 cpus { 9 cpus {
11 #address-cells = <1>; 10 #address-cells = <1>;
12 #size-cells = <0>; 11 #size-cells = <0>;
13 12
14 cpu@0 { 13 cpu@0 {
15 device_type = "cpu"; 14 device_type = "cpu";
16 compatible = "mips,mip 15 compatible = "mips,mips24Kc";
17 clocks = <&pll ATH79_C 16 clocks = <&pll ATH79_CLK_CPU>;
18 reg = <0>; 17 reg = <0>;
19 }; 18 };
20 }; 19 };
21 20
22 cpuintc: interrupt-controller { 21 cpuintc: interrupt-controller {
23 compatible = "qca,ar9132-cpu-i 22 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
24 23
25 interrupt-controller; 24 interrupt-controller;
26 #interrupt-cells = <1>; 25 #interrupt-cells = <1>;
27 26
28 qca,ddr-wb-channel-interrupts 27 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
29 qca,ddr-wb-channels = <&ddr_ct 28 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
30 <&ddr_ 29 <&ddr_ctrl 0>, <&ddr_ctrl 1>;
31 }; 30 };
32 31
33 ahb { 32 ahb {
34 compatible = "simple-bus"; 33 compatible = "simple-bus";
35 ranges; 34 ranges;
36 35
37 #address-cells = <1>; 36 #address-cells = <1>;
38 #size-cells = <1>; 37 #size-cells = <1>;
39 38
40 interrupt-parent = <&cpuintc>; 39 interrupt-parent = <&cpuintc>;
41 40
42 apb { 41 apb {
43 compatible = "simple-b 42 compatible = "simple-bus";
44 ranges; 43 ranges;
45 44
46 #address-cells = <1>; 45 #address-cells = <1>;
47 #size-cells = <1>; 46 #size-cells = <1>;
48 47
49 interrupt-parent = <&m 48 interrupt-parent = <&miscintc>;
50 49
51 ddr_ctrl: memory-contr 50 ddr_ctrl: memory-controller@18000000 {
52 compatible = " 51 compatible = "qca,ar9132-ddr-controller",
53 52 "qca,ar7240-ddr-controller";
54 reg = <0x18000 53 reg = <0x18000000 0x100>;
55 54
56 #qca,ddr-wb-ch 55 #qca,ddr-wb-channel-cells = <1>;
57 }; 56 };
58 57
59 uart: uart@18020000 { 58 uart: uart@18020000 {
60 compatible = " 59 compatible = "ns8250";
61 reg = <0x18020 60 reg = <0x18020000 0x20>;
62 interrupts = < 61 interrupts = <3>;
63 62
64 clocks = <&pll 63 clocks = <&pll ATH79_CLK_AHB>;
65 clock-names = 64 clock-names = "uart";
66 65
67 reg-io-width = 66 reg-io-width = <4>;
68 reg-shift = <2 67 reg-shift = <2>;
69 no-loopback-te 68 no-loopback-test;
70 69
71 status = "disa 70 status = "disabled";
72 }; 71 };
73 72
74 gpio: gpio@18040000 { 73 gpio: gpio@18040000 {
75 compatible = " 74 compatible = "qca,ar9132-gpio",
76 75 "qca,ar7100-gpio";
77 reg = <0x18040 76 reg = <0x18040000 0x30>;
78 interrupts = < 77 interrupts = <2>;
79 78
80 ngpios = <22>; 79 ngpios = <22>;
81 80
82 gpio-controlle 81 gpio-controller;
83 #gpio-cells = 82 #gpio-cells = <2>;
84 83
85 interrupt-cont 84 interrupt-controller;
86 #interrupt-cel 85 #interrupt-cells = <2>;
87 }; 86 };
88 87
89 pll: pll-controller@18 88 pll: pll-controller@18050000 {
90 compatible = " 89 compatible = "qca,ar9132-pll",
91 90 "qca,ar9130-pll";
92 reg = <0x18050 91 reg = <0x18050000 0x20>;
93 92
94 clock-names = 93 clock-names = "ref";
95 /* The board m 94 /* The board must provides the ref clock */
96 95
97 #clock-cells = 96 #clock-cells = <1>;
98 clock-output-n 97 clock-output-names = "cpu", "ddr", "ahb";
99 }; 98 };
100 99
101 wdt: wdt@18060008 { 100 wdt: wdt@18060008 {
102 compatible = " 101 compatible = "qca,ar7130-wdt";
103 reg = <0x18060 102 reg = <0x18060008 0x8>;
104 103
105 interrupts = < 104 interrupts = <4>;
106 105
107 clocks = <&pll 106 clocks = <&pll ATH79_CLK_AHB>;
108 clock-names = 107 clock-names = "wdt";
109 }; 108 };
110 109
111 miscintc: interrupt-co 110 miscintc: interrupt-controller@18060010 {
112 compatible = " 111 compatible = "qca,ar9132-misc-intc",
113 "qc 112 "qca,ar7100-misc-intc";
114 reg = <0x18060 113 reg = <0x18060010 0x8>;
115 114
116 interrupt-pare 115 interrupt-parent = <&cpuintc>;
117 interrupts = < 116 interrupts = <6>;
118 117
119 interrupt-cont 118 interrupt-controller;
120 #interrupt-cel 119 #interrupt-cells = <1>;
121 }; 120 };
122 121
123 rst: reset-controller@ 122 rst: reset-controller@1806001c {
124 compatible = " 123 compatible = "qca,ar9132-reset",
125 124 "qca,ar7100-reset";
126 reg = <0x18060 125 reg = <0x1806001c 0x4>;
127 126
128 #reset-cells = 127 #reset-cells = <1>;
129 }; 128 };
130 }; 129 };
131 130
132 usb: usb@1b000100 { 131 usb: usb@1b000100 {
133 compatible = "qca,ar71 132 compatible = "qca,ar7100-ehci", "generic-ehci";
134 reg = <0x1b000100 0x10 133 reg = <0x1b000100 0x100>;
135 134
136 interrupts = <3>; 135 interrupts = <3>;
137 resets = <&rst 5>; 136 resets = <&rst 5>;
138 137
139 has-transaction-transl 138 has-transaction-translator;
140 139
141 phy-names = "usb"; 140 phy-names = "usb";
142 phys = <&usb_phy>; 141 phys = <&usb_phy>;
143 142
144 status = "disabled"; 143 status = "disabled";
145 }; 144 };
146 145
147 spi: spi@1f000000 { 146 spi: spi@1f000000 {
148 compatible = "qca,ar91 147 compatible = "qca,ar9132-spi", "qca,ar7100-spi";
149 reg = <0x1f000000 0x10 148 reg = <0x1f000000 0x10>;
150 149
151 clocks = <&pll ATH79_C 150 clocks = <&pll ATH79_CLK_AHB>;
152 clock-names = "ahb"; 151 clock-names = "ahb";
153 152
154 status = "disabled"; 153 status = "disabled";
155 154
156 #address-cells = <1>; 155 #address-cells = <1>;
157 #size-cells = <0>; 156 #size-cells = <0>;
158 }; 157 };
159 }; 158 };
160 159
161 usb_phy: usb-phy { 160 usb_phy: usb-phy {
162 compatible = "qca,ar7100-usb-p 161 compatible = "qca,ar7100-usb-phy";
163 162
164 reset-names = "phy", "suspend- !! 163 reset-names = "usb-phy", "usb-suspend-override";
165 resets = <&rst 4>, <&rst 3>; 164 resets = <&rst 4>, <&rst 3>;
166 165
167 #phy-cells = <0>; 166 #phy-cells = <0>;
168 167
169 status = "disabled"; 168 status = "disabled";
170 }; 169 };
171 }; 170 };
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