1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ath79-clk.h> 2 #include <dt-bindings/clock/ath79-clk.h>
3 3
4 / { 4 / {
5 compatible = "qca,ar9132"; 5 compatible = "qca,ar9132";
6 6
7 #address-cells = <1>; 7 #address-cells = <1>;
8 #size-cells = <1>; 8 #size-cells = <1>;
9 9
10 cpus { 10 cpus {
11 #address-cells = <1>; 11 #address-cells = <1>;
12 #size-cells = <0>; 12 #size-cells = <0>;
13 13
14 cpu@0 { 14 cpu@0 {
15 device_type = "cpu"; 15 device_type = "cpu";
16 compatible = "mips,mip 16 compatible = "mips,mips24Kc";
17 clocks = <&pll ATH79_C 17 clocks = <&pll ATH79_CLK_CPU>;
18 reg = <0>; 18 reg = <0>;
19 }; 19 };
20 }; 20 };
21 21
22 cpuintc: interrupt-controller { 22 cpuintc: interrupt-controller {
23 compatible = "qca,ar9132-cpu-i 23 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
24 24
25 interrupt-controller; 25 interrupt-controller;
26 #interrupt-cells = <1>; 26 #interrupt-cells = <1>;
27 27
28 qca,ddr-wb-channel-interrupts 28 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
29 qca,ddr-wb-channels = <&ddr_ct 29 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
30 <&ddr_ 30 <&ddr_ctrl 0>, <&ddr_ctrl 1>;
31 }; 31 };
32 32
33 ahb { 33 ahb {
34 compatible = "simple-bus"; 34 compatible = "simple-bus";
35 ranges; 35 ranges;
36 36
37 #address-cells = <1>; 37 #address-cells = <1>;
38 #size-cells = <1>; 38 #size-cells = <1>;
39 39
40 interrupt-parent = <&cpuintc>; 40 interrupt-parent = <&cpuintc>;
41 41
42 apb { 42 apb {
43 compatible = "simple-b 43 compatible = "simple-bus";
44 ranges; 44 ranges;
45 45
46 #address-cells = <1>; 46 #address-cells = <1>;
47 #size-cells = <1>; 47 #size-cells = <1>;
48 48
49 interrupt-parent = <&m 49 interrupt-parent = <&miscintc>;
50 50
51 ddr_ctrl: memory-contr 51 ddr_ctrl: memory-controller@18000000 {
52 compatible = " 52 compatible = "qca,ar9132-ddr-controller",
53 53 "qca,ar7240-ddr-controller";
54 reg = <0x18000 54 reg = <0x18000000 0x100>;
55 55
56 #qca,ddr-wb-ch 56 #qca,ddr-wb-channel-cells = <1>;
57 }; 57 };
58 58
59 uart: uart@18020000 { 59 uart: uart@18020000 {
60 compatible = " 60 compatible = "ns8250";
61 reg = <0x18020 61 reg = <0x18020000 0x20>;
62 interrupts = < 62 interrupts = <3>;
63 63
64 clocks = <&pll 64 clocks = <&pll ATH79_CLK_AHB>;
65 clock-names = 65 clock-names = "uart";
66 66
67 reg-io-width = 67 reg-io-width = <4>;
68 reg-shift = <2 68 reg-shift = <2>;
69 no-loopback-te 69 no-loopback-test;
70 70
71 status = "disa 71 status = "disabled";
72 }; 72 };
73 73
74 gpio: gpio@18040000 { 74 gpio: gpio@18040000 {
75 compatible = " 75 compatible = "qca,ar9132-gpio",
76 76 "qca,ar7100-gpio";
77 reg = <0x18040 77 reg = <0x18040000 0x30>;
78 interrupts = < 78 interrupts = <2>;
79 79
80 ngpios = <22>; 80 ngpios = <22>;
81 81
82 gpio-controlle 82 gpio-controller;
83 #gpio-cells = 83 #gpio-cells = <2>;
84 84
85 interrupt-cont 85 interrupt-controller;
86 #interrupt-cel 86 #interrupt-cells = <2>;
87 }; 87 };
88 88
89 pll: pll-controller@18 89 pll: pll-controller@18050000 {
90 compatible = " 90 compatible = "qca,ar9132-pll",
91 91 "qca,ar9130-pll";
92 reg = <0x18050 92 reg = <0x18050000 0x20>;
93 93
94 clock-names = 94 clock-names = "ref";
95 /* The board m 95 /* The board must provides the ref clock */
96 96
97 #clock-cells = 97 #clock-cells = <1>;
98 clock-output-n 98 clock-output-names = "cpu", "ddr", "ahb";
99 }; 99 };
100 100
101 wdt: wdt@18060008 { 101 wdt: wdt@18060008 {
102 compatible = " 102 compatible = "qca,ar7130-wdt";
103 reg = <0x18060 103 reg = <0x18060008 0x8>;
104 104
105 interrupts = < 105 interrupts = <4>;
106 106
107 clocks = <&pll 107 clocks = <&pll ATH79_CLK_AHB>;
108 clock-names = 108 clock-names = "wdt";
109 }; 109 };
110 110
111 miscintc: interrupt-co 111 miscintc: interrupt-controller@18060010 {
112 compatible = " 112 compatible = "qca,ar9132-misc-intc",
113 "qc 113 "qca,ar7100-misc-intc";
114 reg = <0x18060 114 reg = <0x18060010 0x8>;
115 115
116 interrupt-pare 116 interrupt-parent = <&cpuintc>;
117 interrupts = < 117 interrupts = <6>;
118 118
119 interrupt-cont 119 interrupt-controller;
120 #interrupt-cel 120 #interrupt-cells = <1>;
121 }; 121 };
122 122
123 rst: reset-controller@ 123 rst: reset-controller@1806001c {
124 compatible = " 124 compatible = "qca,ar9132-reset",
125 125 "qca,ar7100-reset";
126 reg = <0x18060 126 reg = <0x1806001c 0x4>;
127 127
128 #reset-cells = 128 #reset-cells = <1>;
129 }; 129 };
130 }; 130 };
131 131
132 usb: usb@1b000100 { 132 usb: usb@1b000100 {
133 compatible = "qca,ar71 133 compatible = "qca,ar7100-ehci", "generic-ehci";
134 reg = <0x1b000100 0x10 134 reg = <0x1b000100 0x100>;
135 135
136 interrupts = <3>; 136 interrupts = <3>;
137 resets = <&rst 5>; 137 resets = <&rst 5>;
138 138
139 has-transaction-transl 139 has-transaction-translator;
140 140
141 phy-names = "usb"; 141 phy-names = "usb";
142 phys = <&usb_phy>; 142 phys = <&usb_phy>;
143 143
144 status = "disabled"; 144 status = "disabled";
145 }; 145 };
146 146
147 spi: spi@1f000000 { 147 spi: spi@1f000000 {
148 compatible = "qca,ar91 148 compatible = "qca,ar9132-spi", "qca,ar7100-spi";
149 reg = <0x1f000000 0x10 149 reg = <0x1f000000 0x10>;
150 150
151 clocks = <&pll ATH79_C 151 clocks = <&pll ATH79_CLK_AHB>;
152 clock-names = "ahb"; 152 clock-names = "ahb";
153 153
154 status = "disabled"; 154 status = "disabled";
155 155
156 #address-cells = <1>; 156 #address-cells = <1>;
157 #size-cells = <0>; 157 #size-cells = <0>;
158 }; 158 };
159 }; 159 };
160 160
161 usb_phy: usb-phy { 161 usb_phy: usb-phy {
162 compatible = "qca,ar7100-usb-p 162 compatible = "qca,ar7100-usb-phy";
163 163
164 reset-names = "phy", "suspend- 164 reset-names = "phy", "suspend-override";
165 resets = <&rst 4>, <&rst 3>; 165 resets = <&rst 4>, <&rst 3>;
166 166
167 #phy-cells = <0>; 167 #phy-cells = <0>;
168 168
169 status = "disabled"; 169 status = "disabled";
170 }; 170 };
171 }; 171 };
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