1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ath79-clk.h> 2 #include <dt-bindings/clock/ath79-clk.h>
3 3
4 / { 4 / {
5 compatible = "qca,ar9331"; 5 compatible = "qca,ar9331";
6 6
7 #address-cells = <1>; 7 #address-cells = <1>;
8 #size-cells = <1>; 8 #size-cells = <1>;
9 9
10 cpus { 10 cpus {
11 #address-cells = <1>; 11 #address-cells = <1>;
12 #size-cells = <0>; 12 #size-cells = <0>;
13 13
14 cpu@0 { 14 cpu@0 {
15 device_type = "cpu"; 15 device_type = "cpu";
16 compatible = "mips,mip 16 compatible = "mips,mips24Kc";
17 clocks = <&pll ATH79_C 17 clocks = <&pll ATH79_CLK_CPU>;
18 reg = <0>; 18 reg = <0>;
19 }; 19 };
20 }; 20 };
21 21
22 cpuintc: interrupt-controller { 22 cpuintc: interrupt-controller {
23 compatible = "qca,ar7100-cpu-i 23 compatible = "qca,ar7100-cpu-intc";
24 24
25 interrupt-controller; 25 interrupt-controller;
26 #interrupt-cells = <1>; 26 #interrupt-cells = <1>;
27 27
28 qca,ddr-wb-channel-interrupts 28 qca,ddr-wb-channel-interrupts = <2>, <3>;
29 qca,ddr-wb-channels = <&ddr_ct 29 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>;
30 }; 30 };
31 31
32 ref: ref { 32 ref: ref {
33 compatible = "fixed-clock"; 33 compatible = "fixed-clock";
34 #clock-cells = <0>; 34 #clock-cells = <0>;
35 }; 35 };
36 36
37 ahb { 37 ahb {
38 compatible = "simple-bus"; 38 compatible = "simple-bus";
39 ranges; 39 ranges;
40 40
41 #address-cells = <1>; 41 #address-cells = <1>;
42 #size-cells = <1>; 42 #size-cells = <1>;
43 43
44 interrupt-parent = <&cpuintc>; 44 interrupt-parent = <&cpuintc>;
45 45
46 apb { 46 apb {
47 compatible = "simple-b 47 compatible = "simple-bus";
48 ranges; 48 ranges;
49 49
50 #address-cells = <1>; 50 #address-cells = <1>;
51 #size-cells = <1>; 51 #size-cells = <1>;
52 52
53 interrupt-parent = <&m 53 interrupt-parent = <&miscintc>;
54 54
55 ddr_ctrl: memory-contr 55 ddr_ctrl: memory-controller@18000000 {
56 compatible = " 56 compatible = "qca,ar7240-ddr-controller";
57 reg = <0x18000 57 reg = <0x18000000 0x100>;
58 58
59 #qca,ddr-wb-ch 59 #qca,ddr-wb-channel-cells = <1>;
60 }; 60 };
61 61
62 uart: serial@18020000 !! 62 uart: uart@18020000 {
63 compatible = " 63 compatible = "qca,ar9330-uart";
64 reg = <0x18020 64 reg = <0x18020000 0x14>;
65 65
66 interrupts = < 66 interrupts = <3>;
67 67
68 clocks = <&ref 68 clocks = <&ref>;
69 clock-names = 69 clock-names = "uart";
70 70
71 status = "disa 71 status = "disabled";
72 }; 72 };
73 73
74 gpio: gpio@18040000 { 74 gpio: gpio@18040000 {
75 compatible = " 75 compatible = "qca,ar7100-gpio";
76 reg = <0x18040 76 reg = <0x18040000 0x34>;
77 interrupts = < 77 interrupts = <2>;
78 78
79 ngpios = <30>; 79 ngpios = <30>;
80 80
81 gpio-controlle 81 gpio-controller;
82 #gpio-cells = 82 #gpio-cells = <2>;
83 83
84 interrupt-cont 84 interrupt-controller;
85 #interrupt-cel 85 #interrupt-cells = <2>;
86 86
87 status = "disa 87 status = "disabled";
88 }; 88 };
89 89
90 pll: pll-controller@18 90 pll: pll-controller@18050000 {
91 compatible = " 91 compatible = "qca,ar9330-pll";
92 reg = <0x18050 92 reg = <0x18050000 0x100>;
93 93
94 clocks = <&ref 94 clocks = <&ref>;
95 clock-names = 95 clock-names = "ref";
96 96
97 #clock-cells = 97 #clock-cells = <1>;
98 }; 98 };
99 99
100 miscintc: interrupt-co 100 miscintc: interrupt-controller@18060010 {
101 compatible = " 101 compatible = "qca,ar7240-misc-intc";
102 reg = <0x18060 102 reg = <0x18060010 0x8>;
103 103
104 interrupt-pare 104 interrupt-parent = <&cpuintc>;
105 interrupts = < 105 interrupts = <6>;
106 106
107 interrupt-cont 107 interrupt-controller;
108 #interrupt-cel 108 #interrupt-cells = <1>;
109 }; 109 };
110 110
111 rst: reset-controller@ 111 rst: reset-controller@1806001c {
112 compatible = " 112 compatible = "qca,ar7100-reset";
113 reg = <0x18060 113 reg = <0x1806001c 0x4>;
114 114
115 #reset-cells = 115 #reset-cells = <1>;
116 }; 116 };
117 }; 117 };
118 118
119 eth0: ethernet@19000000 { 119 eth0: ethernet@19000000 {
120 compatible = "qca,ar93 120 compatible = "qca,ar9330-eth";
121 reg = <0x19000000 0x20 121 reg = <0x19000000 0x200>;
122 interrupts = <4>; 122 interrupts = <4>;
123 123
124 resets = <&rst 9>, <&r 124 resets = <&rst 9>, <&rst 22>;
125 reset-names = "mac", " 125 reset-names = "mac", "mdio";
126 clocks = <&pll ATH79_C 126 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
127 clock-names = "eth", " 127 clock-names = "eth", "mdio";
128 128
129 phy-mode = "mii"; 129 phy-mode = "mii";
130 phy-handle = <&phy_por 130 phy-handle = <&phy_port4>;
131 131
132 status = "disabled"; 132 status = "disabled";
133 }; 133 };
134 134
135 eth1: ethernet@1a000000 { 135 eth1: ethernet@1a000000 {
136 compatible = "qca,ar93 136 compatible = "qca,ar9330-eth";
137 reg = <0x1a000000 0x20 137 reg = <0x1a000000 0x200>;
138 interrupts = <5>; 138 interrupts = <5>;
139 resets = <&rst 13>, <& 139 resets = <&rst 13>, <&rst 23>;
140 reset-names = "mac", " 140 reset-names = "mac", "mdio";
141 clocks = <&pll ATH79_C 141 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
142 clock-names = "eth", " 142 clock-names = "eth", "mdio";
143 143
144 phy-mode = "gmii"; 144 phy-mode = "gmii";
145 145
146 status = "disabled"; 146 status = "disabled";
147 147
148 fixed-link { 148 fixed-link {
149 speed = <1000> 149 speed = <1000>;
150 full-duplex; 150 full-duplex;
151 pause; <<
152 }; 151 };
153 152
154 mdio { 153 mdio {
155 #address-cells 154 #address-cells = <1>;
156 #size-cells = 155 #size-cells = <0>;
157 156
158 switch10: swit 157 switch10: switch@10 {
159 #addre 158 #address-cells = <1>;
160 #size- 159 #size-cells = <0>;
161 160
162 compat 161 compatible = "qca,ar9331-switch";
163 reg = 162 reg = <0x10>;
164 resets 163 resets = <&rst 8>;
165 reset- 164 reset-names = "switch";
166 165
167 interr 166 interrupt-parent = <&miscintc>;
168 interr 167 interrupts = <12>;
169 168
170 interr 169 interrupt-controller;
171 #inter 170 #interrupt-cells = <1>;
172 171
173 ports 172 ports {
174 173 #address-cells = <1>;
175 174 #size-cells = <0>;
176 175
177 176 switch_port0: port@0 {
178 177 reg = <0x0>;
>> 178 label = "cpu";
179 179 ethernet = <ð1>;
180 180
181 181 phy-mode = "gmii";
182 182
183 183 fixed-link {
184 184 speed = <1000>;
185 185 full-duplex;
186 <<
187 186 };
188 187 };
189 188
190 189 switch_port1: port@1 {
191 190 reg = <0x1>;
192 191 phy-handle = <&phy_port0>;
193 192 phy-mode = "internal";
194 193
195 194 status = "disabled";
196 195 };
197 196
198 197 switch_port2: port@2 {
199 198 reg = <0x2>;
200 199 phy-handle = <&phy_port1>;
201 200 phy-mode = "internal";
202 201
203 202 status = "disabled";
204 203 };
205 204
206 205 switch_port3: port@3 {
207 206 reg = <0x3>;
208 207 phy-handle = <&phy_port2>;
209 208 phy-mode = "internal";
210 209
211 210 status = "disabled";
212 211 };
213 212
214 213 switch_port4: port@4 {
215 214 reg = <0x4>;
216 215 phy-handle = <&phy_port3>;
217 216 phy-mode = "internal";
218 217
219 218 status = "disabled";
220 219 };
221 }; 220 };
222 221
223 mdio { 222 mdio {
224 223 #address-cells = <1>;
225 224 #size-cells = <0>;
226 225
227 226 interrupt-parent = <&switch10>;
228 227
229 228 phy_port0: phy@0 {
230 229 reg = <0x0>;
231 230 interrupts = <0>;
232 231 status = "disabled";
233 232 };
234 233
235 234 phy_port1: phy@1 {
236 235 reg = <0x1>;
237 236 interrupts = <0>;
238 237 status = "disabled";
239 238 };
240 239
241 240 phy_port2: phy@2 {
242 241 reg = <0x2>;
243 242 interrupts = <0>;
244 243 status = "disabled";
245 244 };
246 245
247 246 phy_port3: phy@3 {
248 247 reg = <0x3>;
249 248 interrupts = <0>;
250 249 status = "disabled";
251 250 };
252 251
253 252 phy_port4: phy@4 {
254 253 reg = <0x4>;
255 254 interrupts = <0>;
256 255 status = "disabled";
257 256 };
258 }; 257 };
259 }; 258 };
260 }; 259 };
261 }; 260 };
262 261
263 usb: usb@1b000100 { 262 usb: usb@1b000100 {
264 compatible = "chipidea 263 compatible = "chipidea,usb2";
265 reg = <0x1b000000 0x20 264 reg = <0x1b000000 0x200>;
266 265
267 interrupts = <3>; 266 interrupts = <3>;
268 resets = <&rst 5>; 267 resets = <&rst 5>;
269 268
270 phy-names = "usb-phy"; 269 phy-names = "usb-phy";
271 phys = <&usb_phy>; 270 phys = <&usb_phy>;
272 271
273 status = "disabled"; 272 status = "disabled";
274 }; 273 };
275 274
276 spi: spi@1f000000 { 275 spi: spi@1f000000 {
277 compatible = "qca,ar71 276 compatible = "qca,ar7100-spi";
278 reg = <0x1f000000 0x10 277 reg = <0x1f000000 0x10>;
279 278
280 clocks = <&pll ATH79_C 279 clocks = <&pll ATH79_CLK_AHB>;
281 clock-names = "ahb"; 280 clock-names = "ahb";
282 281
283 #address-cells = <1>; 282 #address-cells = <1>;
284 #size-cells = <0>; 283 #size-cells = <0>;
285 284
286 status = "disabled"; 285 status = "disabled";
287 }; 286 };
288 }; 287 };
289 288
290 usb_phy: usb-phy { 289 usb_phy: usb-phy {
291 compatible = "qca,ar7100-usb-p 290 compatible = "qca,ar7100-usb-phy";
292 291
293 reset-names = "phy", "suspend- 292 reset-names = "phy", "suspend-override";
294 resets = <&rst 4>, <&rst 3>; 293 resets = <&rst 4>, <&rst 3>;
295 294
296 #phy-cells = <0>; 295 #phy-cells = <0>;
297 296
298 status = "disabled"; 297 status = "disabled";
299 }; 298 };
300 }; 299 };
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