1 /dts-v1/; 1 /dts-v1/;
2 / { 2 / {
3 compatible = "opencores,or1ksim"; 3 compatible = "opencores,or1ksim";
4 #address-cells = <1>; 4 #address-cells = <1>;
5 #size-cells = <1>; 5 #size-cells = <1>;
6 interrupt-parent = <&pic>; 6 interrupt-parent = <&pic>;
7 7
8 aliases { 8 aliases {
9 uart0 = &serial0; 9 uart0 = &serial0;
10 }; 10 };
11 11
12 chosen { 12 chosen {
13 bootargs = "earlycon"; 13 bootargs = "earlycon";
14 stdout-path = "uart0:115200"; 14 stdout-path = "uart0:115200";
15 }; 15 };
16 16
17 memory@0 { 17 memory@0 {
18 device_type = "memory"; 18 device_type = "memory";
19 reg = <0x00000000 0x02000000>; 19 reg = <0x00000000 0x02000000>;
20 }; 20 };
21 21
22 cpus { 22 cpus {
23 #address-cells = <1>; 23 #address-cells = <1>;
24 #size-cells = <0>; 24 #size-cells = <0>;
25 cpu@0 { 25 cpu@0 {
26 compatible = "opencore 26 compatible = "opencores,or1200-rtlsvn481";
27 reg = <0>; 27 reg = <0>;
28 clock-frequency = <200 28 clock-frequency = <20000000>;
29 }; 29 };
30 cpu@1 { 30 cpu@1 {
31 compatible = "opencore 31 compatible = "opencores,or1200-rtlsvn481";
32 reg = <1>; 32 reg = <1>;
33 clock-frequency = <200 33 clock-frequency = <20000000>;
34 }; 34 };
35 }; 35 };
36 36
37 ompic: ompic@98000000 { 37 ompic: ompic@98000000 {
38 compatible = "openrisc,ompic"; 38 compatible = "openrisc,ompic";
39 reg = <0x98000000 16>; 39 reg = <0x98000000 16>;
40 interrupt-controller; 40 interrupt-controller;
41 #interrupt-cells = <0>; 41 #interrupt-cells = <0>;
42 interrupts = <1>; 42 interrupts = <1>;
43 }; 43 };
44 44
45 /* 45 /*
46 * OR1K PIC is built into CPU and acce 46 * OR1K PIC is built into CPU and accessed via special purpose
47 * registers. It is not addressable a 47 * registers. It is not addressable and, hence, has no 'reg'
48 * property. 48 * property.
49 */ 49 */
50 pic: pic { 50 pic: pic {
51 compatible = "opencores,or1k-p 51 compatible = "opencores,or1k-pic-level";
52 #interrupt-cells = <1>; 52 #interrupt-cells = <1>;
53 interrupt-controller; 53 interrupt-controller;
54 }; 54 };
55 55
56 serial0: serial@90000000 { 56 serial0: serial@90000000 {
57 compatible = "opencores,uart16 57 compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
58 reg = <0x90000000 0x100>; 58 reg = <0x90000000 0x100>;
59 interrupts = <2>; 59 interrupts = <2>;
60 clock-frequency = <20000000>; 60 clock-frequency = <20000000>;
61 }; 61 };
62 62
63 enet0: ethoc@92000000 { 63 enet0: ethoc@92000000 {
64 compatible = "opencores,ethoc" 64 compatible = "opencores,ethoc";
65 reg = <0x92000000 0x800>; 65 reg = <0x92000000 0x800>;
66 interrupts = <4>; 66 interrupts = <4>;
67 big-endian; 67 big-endian;
68 }; 68 };
69 }; 69 };
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