1 /* 1 /*
2 * Device Tree Source for IBM Embedded PPC 476 2 * Device Tree Source for IBM Embedded PPC 476 Platform
3 * 3 *
4 * Copyright © 2013 Tony Breeds IBM Corporati 4 * Copyright © 2013 Tony Breeds IBM Corporation
5 * Copyright © 2013 Alistair Popple IBM Corpo 5 * Copyright © 2013 Alistair Popple IBM Corporation
6 * 6 *
7 * This file is licensed under the terms of th 7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is license 8 * License version 2. This program is licensed "as is" without
9 * any warranty of any kind, whether express o 9 * any warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12 /dts-v1/; 12 /dts-v1/;
13 13
14 /memreserve/ 0x01f00000 0x00100000; // spi 14 /memreserve/ 0x01f00000 0x00100000; // spin table
15 15
16 / { 16 / {
17 #address-cells = <2>; 17 #address-cells = <2>;
18 #size-cells = <2>; 18 #size-cells = <2>;
19 model = "ibm,akebono"; 19 model = "ibm,akebono";
20 compatible = "ibm,akebono", "ibm,476gt 20 compatible = "ibm,akebono", "ibm,476gtr";
21 dcr-parent = <&{/cpus/cpu@0}>; 21 dcr-parent = <&{/cpus/cpu@0}>;
22 22
23 aliases { 23 aliases {
24 serial0 = &UART0; 24 serial0 = &UART0;
25 }; 25 };
26 26
27 cpus { 27 cpus {
28 #address-cells = <1>; 28 #address-cells = <1>;
29 #size-cells = <0>; 29 #size-cells = <0>;
30 30
31 cpu@0 { 31 cpu@0 {
32 device_type = "cpu"; 32 device_type = "cpu";
33 model = "PowerPC,476"; 33 model = "PowerPC,476";
34 reg = <0>; 34 reg = <0>;
35 clock-frequency = <160 35 clock-frequency = <1600000000>; // 1.6 GHz
36 timebase-frequency = < 36 timebase-frequency = <100000000>; // 100Mhz
37 i-cache-line-size = <3 37 i-cache-line-size = <32>;
38 d-cache-line-size = <3 38 d-cache-line-size = <32>;
39 i-cache-size = <32768> 39 i-cache-size = <32768>;
40 d-cache-size = <32768> 40 d-cache-size = <32768>;
41 dcr-controller; 41 dcr-controller;
42 dcr-access-method = "n 42 dcr-access-method = "native";
43 status = "okay"; 43 status = "okay";
44 }; 44 };
45 cpu@1 { 45 cpu@1 {
46 device_type = "cpu"; 46 device_type = "cpu";
47 model = "PowerPC,476"; 47 model = "PowerPC,476";
48 reg = <1>; 48 reg = <1>;
49 clock-frequency = <160 49 clock-frequency = <1600000000>; // 1.6 GHz
50 timebase-frequency = < 50 timebase-frequency = <100000000>; // 100Mhz
51 i-cache-line-size = <3 51 i-cache-line-size = <32>;
52 d-cache-line-size = <3 52 d-cache-line-size = <32>;
53 i-cache-size = <32768> 53 i-cache-size = <32768>;
54 d-cache-size = <32768> 54 d-cache-size = <32768>;
55 dcr-controller; 55 dcr-controller;
56 dcr-access-method = "n 56 dcr-access-method = "native";
57 status = "disabled"; 57 status = "disabled";
58 enable-method = "spin- 58 enable-method = "spin-table";
59 cpu-release-addr = <0x 59 cpu-release-addr = <0x0 0x01f00000>;
60 }; 60 };
61 }; 61 };
62 62
63 memory { 63 memory {
64 device_type = "memory"; 64 device_type = "memory";
65 reg = <0x0 0x0 0x0 0x0>; // fi 65 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
66 }; 66 };
67 67
68 MPIC: interrupt-controller { 68 MPIC: interrupt-controller {
69 compatible = "chrp,open-pic"; 69 compatible = "chrp,open-pic";
70 interrupt-controller; 70 interrupt-controller;
71 dcr-reg = <0xffc00000 0x000400 71 dcr-reg = <0xffc00000 0x00040000>;
72 #address-cells = <0>; 72 #address-cells = <0>;
73 #size-cells = <0>; 73 #size-cells = <0>;
74 #interrupt-cells = <2>; 74 #interrupt-cells = <2>;
75 single-cpu-affinity; 75 single-cpu-affinity;
76 }; 76 };
77 77
78 plb { 78 plb {
79 compatible = "ibm,plb6"; 79 compatible = "ibm,plb6";
80 #address-cells = <2>; 80 #address-cells = <2>;
81 #size-cells = <2>; 81 #size-cells = <2>;
82 ranges; 82 ranges;
83 clock-frequency = <200000000>; 83 clock-frequency = <200000000>; // 200Mhz
84 84
85 HSTA0: hsta@310000e0000 { 85 HSTA0: hsta@310000e0000 {
86 compatible = "ibm,476g 86 compatible = "ibm,476gtr-hsta-msi", "ibm,hsta-msi";
87 reg = <0x310 0x000e000 87 reg = <0x310 0x000e0000 0x0 0xf0>;
88 interrupt-parent = <&M 88 interrupt-parent = <&MPIC>;
89 interrupts = <108 0 89 interrupts = <108 0
90 109 0 90 109 0
91 110 0 91 110 0
92 111 0 92 111 0
93 112 0 93 112 0
94 113 0 94 113 0
95 114 0 95 114 0
96 115 0 96 115 0
97 116 0 97 116 0
98 117 0 98 117 0
99 118 0 99 118 0
100 119 0 100 119 0
101 120 0 101 120 0
102 121 0 102 121 0
103 122 0 103 122 0
104 123 0>; 104 123 0>;
105 }; 105 };
106 106
107 MAL0: mcmal { 107 MAL0: mcmal {
108 compatible = "ibm,mcma 108 compatible = "ibm,mcmal-476gtr", "ibm,mcmal2";
109 dcr-reg = <0xc0000000 109 dcr-reg = <0xc0000000 0x062>;
110 num-tx-chans = <1>; 110 num-tx-chans = <1>;
111 num-rx-chans = <1>; 111 num-rx-chans = <1>;
112 #address-cells = <0>; 112 #address-cells = <0>;
113 #size-cells = <0>; 113 #size-cells = <0>;
114 interrupt-parent = <&M 114 interrupt-parent = <&MPIC>;
115 interrupts = < /*TXEO 115 interrupts = < /*TXEOB*/ 77 0x4
116 /*RXEO 116 /*RXEOB*/ 78 0x4
117 /*SERR 117 /*SERR*/ 76 0x4
118 /*TXDE 118 /*TXDE*/ 79 0x4
119 /*RXDE 119 /*RXDE*/ 80 0x4>;
120 }; 120 };
121 121
122 SATA0: sata@30000010000 { 122 SATA0: sata@30000010000 {
123 compatible = "ibm,476g 123 compatible = "ibm,476gtr-ahci";
124 reg = <0x300 0x0001000 124 reg = <0x300 0x00010000 0x0 0x10000>;
125 interrupt-parent = <&M 125 interrupt-parent = <&MPIC>;
126 interrupts = <93 2>; 126 interrupts = <93 2>;
127 }; 127 };
128 128
129 EHCI0: usb@30010000000 { 129 EHCI0: usb@30010000000 {
130 compatible = "ibm,476g 130 compatible = "ibm,476gtr-ehci", "generic-ehci";
131 reg = <0x300 0x1000000 131 reg = <0x300 0x10000000 0x0 0x10000>;
132 interrupt-parent = <&M 132 interrupt-parent = <&MPIC>;
133 interrupts = <85 2>; 133 interrupts = <85 2>;
134 }; 134 };
135 135
136 SD0: sd@30000000000 { 136 SD0: sd@30000000000 {
137 compatible = "ibm,476g 137 compatible = "ibm,476gtr-sdhci", "generic-sdhci";
138 reg = <0x300 0x0000000 138 reg = <0x300 0x00000000 0x0 0x10000>;
139 interrupts = <91 2>; 139 interrupts = <91 2>;
140 interrupt-parent = <&M 140 interrupt-parent = <&MPIC>;
141 }; 141 };
142 142
143 OHCI0: usb@30010010000 { 143 OHCI0: usb@30010010000 {
144 compatible = "ibm,476g 144 compatible = "ibm,476gtr-ohci", "generic-ohci";
145 reg = <0x300 0x1001000 145 reg = <0x300 0x10010000 0x0 0x10000>;
146 interrupt-parent = <&M 146 interrupt-parent = <&MPIC>;
147 interrupts = <89 1>; 147 interrupts = <89 1>;
148 }; 148 };
149 149
150 OHCI1: usb@30010020000 { 150 OHCI1: usb@30010020000 {
151 compatible = "ibm,476g 151 compatible = "ibm,476gtr-ohci", "generic-ohci";
152 reg = <0x300 0x1002000 152 reg = <0x300 0x10020000 0x0 0x10000>;
153 interrupt-parent = <&M 153 interrupt-parent = <&MPIC>;
154 interrupts = <88 1>; 154 interrupts = <88 1>;
155 }; 155 };
156 156
157 POB0: opb { 157 POB0: opb {
158 compatible = "ibm,opb- 158 compatible = "ibm,opb-4xx", "ibm,opb";
159 #address-cells = <1>; 159 #address-cells = <1>;
160 #size-cells = <1>; 160 #size-cells = <1>;
161 /* Wish there was a ni 161 /* Wish there was a nicer way of specifying a full
162 * 32-bit range 162 * 32-bit range
163 */ 163 */
164 ranges = <0x00000000 0 164 ranges = <0x00000000 0x0000033f 0x00000000 0x80000000
165 0x80000000 0 165 0x80000000 0x0000033f 0x80000000 0x80000000>;
166 clock-frequency = <100 166 clock-frequency = <100000000>;
167 167
168 RGMII0: emac-rgmii-wol 168 RGMII0: emac-rgmii-wol@50004 {
169 compatible = " 169 compatible = "ibm,rgmii-wol-476gtr", "ibm,rgmii-wol";
170 reg = <0x50004 170 reg = <0x50004 0x00000008>;
171 has-mdio; 171 has-mdio;
172 }; 172 };
173 173
174 EMAC0: ethernet@30000 174 EMAC0: ethernet@30000 {
175 device_type = 175 device_type = "network";
176 compatible = " 176 compatible = "ibm,emac-476gtr", "ibm,emac4sync";
177 interrupt-pare 177 interrupt-parent = <&EMAC0>;
178 interrupts = < 178 interrupts = <0x0 0x1>;
179 #interrupt-cel 179 #interrupt-cells = <1>;
180 #address-cells 180 #address-cells = <0>;
181 #size-cells = 181 #size-cells = <0>;
182 interrupt-map 182 interrupt-map = </*Status*/ 0x0 &MPIC 81 0x4
183 183 /*Wake*/ 0x1 &MPIC 82 0x4>;
184 reg = <0x30000 184 reg = <0x30000 0x78>;
185 185
186 /* local-mac-a 186 /* local-mac-address will normally be added by
187 * the wrapper 187 * the wrapper. If your device doesn't support
188 * passing dat 188 * passing data to the wrapper (in the form
189 * local-mac-a 189 * local-mac-addr=<hwaddr>) then you will need
190 * to set it m 190 * to set it manually here. */
191 //local-mac-ad 191 //local-mac-address = [000000000000];
192 192
193 mal-device = < 193 mal-device = <&MAL0>;
194 mal-tx-channel 194 mal-tx-channel = <0>;
195 mal-rx-channel 195 mal-rx-channel = <0>;
196 cell-index = < 196 cell-index = <0>;
197 max-frame-size 197 max-frame-size = <9000>;
198 rx-fifo-size = 198 rx-fifo-size = <4096>;
199 tx-fifo-size = 199 tx-fifo-size = <2048>;
200 rx-fifo-size-g 200 rx-fifo-size-gige = <16384>;
201 phy-mode = "rg 201 phy-mode = "rgmii";
202 phy-map = <0x0 202 phy-map = <0x00000000>;
203 rgmii-wol-devi 203 rgmii-wol-device = <&RGMII0>;
204 has-inverted-s 204 has-inverted-stacr-oc;
205 has-new-stacr- 205 has-new-stacr-staopc;
206 }; 206 };
207 207
208 UART0: serial@10000 { 208 UART0: serial@10000 {
209 device_type = 209 device_type = "serial";
210 compatible = " 210 compatible = "ns16750", "ns16550";
211 reg = <0x10000 211 reg = <0x10000 0x00000008>;
212 virtual-reg = 212 virtual-reg = <0xe8010000>;
213 clock-frequenc 213 clock-frequency = <1851851>;
214 current-speed 214 current-speed = <38400>;
215 interrupt-pare 215 interrupt-parent = <&MPIC>;
216 interrupts = < 216 interrupts = <39 2>;
217 }; 217 };
218 218
219 IIC0: i2c@0 { 219 IIC0: i2c@0 {
220 compatible = " 220 compatible = "ibm,iic-476gtr", "ibm,iic";
221 reg = <0x0 0x0 221 reg = <0x0 0x00000020>;
222 interrupt-pare 222 interrupt-parent = <&MPIC>;
223 interrupts = < 223 interrupts = <37 2>;
224 #address-cells 224 #address-cells = <1>;
225 #size-cells = 225 #size-cells = <0>;
226 rtc@68 { 226 rtc@68 {
227 compat 227 compatible = "st,m41t80", "m41st85";
228 reg = 228 reg = <0x68>;
229 }; 229 };
230 }; 230 };
231 231
232 IIC1: i2c@100 { 232 IIC1: i2c@100 {
233 compatible = " 233 compatible = "ibm,iic-476gtr", "ibm,iic";
234 reg = <0x100 0 234 reg = <0x100 0x00000020>;
235 interrupt-pare 235 interrupt-parent = <&MPIC>;
236 interrupts = < 236 interrupts = <38 2>;
237 #address-cells 237 #address-cells = <1>;
238 #size-cells = 238 #size-cells = <0>;
239 avr@58 { 239 avr@58 {
240 compat 240 compatible = "ibm,akebono-avr";
241 reg = 241 reg = <0x58>;
242 }; 242 };
243 }; 243 };
244 244
245 FPGA0: fpga@ebc00000 { 245 FPGA0: fpga@ebc00000 {
246 compatible = " 246 compatible = "ibm,akebono-fpga";
247 reg = <0xebc00 247 reg = <0xebc00000 0x8>;
248 }; 248 };
249 }; 249 };
250 250
251 PCIE0: pcie@10100000000 { 251 PCIE0: pcie@10100000000 {
252 device_type = "pci"; 252 device_type = "pci";
253 #interrupt-cells = <1> 253 #interrupt-cells = <1>;
254 #size-cells = <2>; 254 #size-cells = <2>;
255 #address-cells = <3>; 255 #address-cells = <3>;
256 compatible = "ibm,plb- 256 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
257 primary; 257 primary;
258 port = <0x0>; /* port 258 port = <0x0>; /* port number */
259 reg = <0x00000101 0x00 259 reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */
260 0x00000100 0x00 260 0x00000100 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
261 dcr-reg = <0xc0 0x20>; 261 dcr-reg = <0xc0 0x20>;
262 262
263 // pci_space < 263 // pci_space < pci_addr > < cpu_addr > < size >
264 ranges = <0x02000000 0 264 ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
265 0x01000000 0 265 0x01000000 0x0 0x0 0x00000140 0x0 0x0 0x00010000>;
266 266
267 /* Inbound starting at 267 /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
268 * PCI devices must be 268 * PCI devices must be able to write to the HSTA module.
269 */ 269 */
270 dma-ranges = <0x420000 270 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
271 271
272 /* This drives busses 272 /* This drives busses 0 to 0xf */
273 bus-range = <0x0 0xf>; 273 bus-range = <0x0 0xf>;
274 274
275 /* Legacy interrupts ( 275 /* Legacy interrupts (note the weird polarity, the bridge seems
276 * to invert PCIe lega 276 * to invert PCIe legacy interrupts).
277 * We are de-swizzling 277 * We are de-swizzling here because the numbers are actually for
278 * port of the root co 278 * port of the root complex virtual P2P bridge. But I want
279 * to avoid putting a 279 * to avoid putting a node for it in the tree, so the numbers
280 * below are basically 280 * below are basically de-swizzled numbers.
281 * The real slot is on 281 * The real slot is on idsel 0, so the swizzling is 1:1
282 */ 282 */
283 interrupt-map-mask = < 283 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
284 interrupt-map = < 284 interrupt-map = <
285 0x0 0x0 0x0 0x 285 0x0 0x0 0x0 0x1 &MPIC 45 0x2 /* int A */
286 0x0 0x0 0x0 0x 286 0x0 0x0 0x0 0x2 &MPIC 46 0x2 /* int B */
287 0x0 0x0 0x0 0x 287 0x0 0x0 0x0 0x3 &MPIC 47 0x2 /* int C */
288 0x0 0x0 0x0 0x 288 0x0 0x0 0x0 0x4 &MPIC 48 0x2 /* int D */>;
289 }; 289 };
290 290
291 PCIE1: pcie@20100000000 { 291 PCIE1: pcie@20100000000 {
292 device_type = "pci"; 292 device_type = "pci";
293 #interrupt-cells = <1> 293 #interrupt-cells = <1>;
294 #size-cells = <2>; 294 #size-cells = <2>;
295 #address-cells = <3>; 295 #address-cells = <3>;
296 compatible = "ibm,plb- 296 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
297 primary; 297 primary;
298 port = <0x1>; /* port 298 port = <0x1>; /* port number */
299 reg = <0x00000201 0x00 299 reg = <0x00000201 0x00000000 0x0 0x10000000 /* Config space access */
300 0x00000200 0x00 300 0x00000200 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
301 dcr-reg = <0x100 0x20> 301 dcr-reg = <0x100 0x20>;
302 302
303 // pci_space < 303 // pci_space < pci_addr > < cpu_addr > < size >
304 ranges = <0x02000000 0 304 ranges = <0x02000000 0x00000000 0x80000000 0x00000210 0x80000000 0x0 0x80000000
305 0x01000000 0 305 0x01000000 0x0 0x0 0x00000240 0x0 0x0 0x00010000>;
306 306
307 /* Inbound starting at 307 /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
308 * PCI devices must be 308 * PCI devices must be able to write to the HSTA module.
309 */ 309 */
310 dma-ranges = <0x420000 310 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
311 311
312 /* This drives busses 312 /* This drives busses 0 to 0xf */
313 bus-range = <0x0 0xf>; 313 bus-range = <0x0 0xf>;
314 314
315 /* Legacy interrupts ( 315 /* Legacy interrupts (note the weird polarity, the bridge seems
316 * to invert PCIe lega 316 * to invert PCIe legacy interrupts).
317 * We are de-swizzling 317 * We are de-swizzling here because the numbers are actually for
318 * port of the root co 318 * port of the root complex virtual P2P bridge. But I want
319 * to avoid putting a 319 * to avoid putting a node for it in the tree, so the numbers
320 * below are basically 320 * below are basically de-swizzled numbers.
321 * The real slot is on 321 * The real slot is on idsel 0, so the swizzling is 1:1
322 */ 322 */
323 interrupt-map-mask = < 323 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
324 interrupt-map = < 324 interrupt-map = <
325 0x0 0x0 0x0 0x 325 0x0 0x0 0x0 0x1 &MPIC 53 0x2 /* int A */
326 0x0 0x0 0x0 0x 326 0x0 0x0 0x0 0x2 &MPIC 54 0x2 /* int B */
327 0x0 0x0 0x0 0x 327 0x0 0x0 0x0 0x3 &MPIC 55 0x2 /* int C */
328 0x0 0x0 0x0 0x 328 0x0 0x0 0x0 0x4 &MPIC 56 0x2 /* int D */>;
329 }; 329 };
330 330
331 PCIE2: pcie@18100000000 { 331 PCIE2: pcie@18100000000 {
332 device_type = "pci"; 332 device_type = "pci";
333 #interrupt-cells = <1> 333 #interrupt-cells = <1>;
334 #size-cells = <2>; 334 #size-cells = <2>;
335 #address-cells = <3>; 335 #address-cells = <3>;
336 compatible = "ibm,plb- 336 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
337 primary; 337 primary;
338 port = <0x2>; /* port 338 port = <0x2>; /* port number */
339 reg = <0x00000181 0x00 339 reg = <0x00000181 0x00000000 0x0 0x10000000 /* Config space access */
340 0x00000180 0x00 340 0x00000180 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
341 dcr-reg = <0xe0 0x20>; 341 dcr-reg = <0xe0 0x20>;
342 342
343 // pci_space < 343 // pci_space < pci_addr > < cpu_addr > < size >
344 ranges = <0x02000000 0 344 ranges = <0x02000000 0x00000000 0x80000000 0x00000190 0x80000000 0x0 0x80000000
345 0x01000000 0 345 0x01000000 0x0 0x0 0x000001c0 0x0 0x0 0x00010000>;
346 346
347 /* Inbound starting at 347 /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
348 * PCI devices must be 348 * PCI devices must be able to write to the HSTA module.
349 */ 349 */
350 dma-ranges = <0x420000 350 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
351 351
352 /* This drives busses 352 /* This drives busses 0 to 0xf */
353 bus-range = <0x0 0xf>; 353 bus-range = <0x0 0xf>;
354 354
355 /* Legacy interrupts ( 355 /* Legacy interrupts (note the weird polarity, the bridge seems
356 * to invert PCIe lega 356 * to invert PCIe legacy interrupts).
357 * We are de-swizzling 357 * We are de-swizzling here because the numbers are actually for
358 * port of the root co 358 * port of the root complex virtual P2P bridge. But I want
359 * to avoid putting a 359 * to avoid putting a node for it in the tree, so the numbers
360 * below are basically 360 * below are basically de-swizzled numbers.
361 * The real slot is on 361 * The real slot is on idsel 0, so the swizzling is 1:1
362 */ 362 */
363 interrupt-map-mask = < 363 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
364 interrupt-map = < 364 interrupt-map = <
365 0x0 0x0 0x0 0x 365 0x0 0x0 0x0 0x1 &MPIC 61 0x2 /* int A */
366 0x0 0x0 0x0 0x 366 0x0 0x0 0x0 0x2 &MPIC 62 0x2 /* int B */
367 0x0 0x0 0x0 0x 367 0x0 0x0 0x0 0x3 &MPIC 63 0x2 /* int C */
368 0x0 0x0 0x0 0x 368 0x0 0x0 0x0 0x4 &MPIC 64 0x2 /* int D */>;
369 }; 369 };
370 370
371 PCIE3: pcie@28100000000 { 371 PCIE3: pcie@28100000000 {
372 device_type = "pci"; 372 device_type = "pci";
373 #interrupt-cells = <1> 373 #interrupt-cells = <1>;
374 #size-cells = <2>; 374 #size-cells = <2>;
375 #address-cells = <3>; 375 #address-cells = <3>;
376 compatible = "ibm,plb- 376 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
377 primary; 377 primary;
378 port = <0x3>; /* port 378 port = <0x3>; /* port number */
379 reg = <0x00000281 0x00 379 reg = <0x00000281 0x00000000 0x0 0x10000000 /* Config space access */
380 0x00000280 0x00 380 0x00000280 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
381 dcr-reg = <0x120 0x20> 381 dcr-reg = <0x120 0x20>;
382 382
383 // pci_space < 383 // pci_space < pci_addr > < cpu_addr > < size >
384 ranges = <0x02000000 0 384 ranges = <0x02000000 0x00000000 0x80000000 0x00000290 0x80000000 0x0 0x80000000
385 0x01000000 0 385 0x01000000 0x0 0x0 0x000002c0 0x0 0x0 0x00010000>;
386 386
387 /* Inbound starting at 387 /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
388 * PCI devices must be 388 * PCI devices must be able to write to the HSTA module.
389 */ 389 */
390 dma-ranges = <0x420000 390 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
391 391
392 /* This drives busses 392 /* This drives busses 0 to 0xf */
393 bus-range = <0x0 0xf>; 393 bus-range = <0x0 0xf>;
394 394
395 /* Legacy interrupts ( 395 /* Legacy interrupts (note the weird polarity, the bridge seems
396 * to invert PCIe lega 396 * to invert PCIe legacy interrupts).
397 * We are de-swizzling 397 * We are de-swizzling here because the numbers are actually for
398 * port of the root co 398 * port of the root complex virtual P2P bridge. But I want
399 * to avoid putting a 399 * to avoid putting a node for it in the tree, so the numbers
400 * below are basically 400 * below are basically de-swizzled numbers.
401 * The real slot is on 401 * The real slot is on idsel 0, so the swizzling is 1:1
402 */ 402 */
403 interrupt-map-mask = < 403 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
404 interrupt-map = < 404 interrupt-map = <
405 0x0 0x0 0x0 0x 405 0x0 0x0 0x0 0x1 &MPIC 69 0x2 /* int A */
406 0x0 0x0 0x0 0x 406 0x0 0x0 0x0 0x2 &MPIC 70 0x2 /* int B */
407 0x0 0x0 0x0 0x 407 0x0 0x0 0x0 0x3 &MPIC 71 0x2 /* int C */
408 0x0 0x0 0x0 0x 408 0x0 0x0 0x0 0x4 &MPIC 72 0x2 /* int D */>;
409 }; 409 };
410 }; 410 };
411 411
412 chosen { 412 chosen {
413 stdout-path = &UART0; 413 stdout-path = &UART0;
414 }; 414 };
415 }; 415 };
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