1 /*
2 * Device Tree Source for AMCC Canyonlands (46
3 *
4 * Copyright 2008-2009 DENX Software Engineeri<
5 *
6 * This file is licensed under the terms of th
7 * License version 2. This program is license
8 * any warranty of any kind, whether express o
9 */
10
11 /dts-v1/;
12
13 / {
14 #address-cells = <2>;
15 #size-cells = <1>;
16 model = "amcc,canyonlands";
17 compatible = "amcc,canyonlands";
18 dcr-parent = <&{/cpus/cpu@0}>;
19
20 aliases {
21 ethernet0 = &EMAC0;
22 ethernet1 = &EMAC1;
23 serial0 = &UART0;
24 serial1 = &UART1;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 model = "PowerPC,460EX
34 reg = <0x00000000>;
35 clock-frequency = <0>;
36 timebase-frequency = <
37 i-cache-line-size = <3
38 d-cache-line-size = <3
39 i-cache-size = <32768>
40 d-cache-size = <32768>
41 dcr-controller;
42 dcr-access-method = "n
43 next-level-cache = <&L
44 };
45 };
46
47 memory {
48 device_type = "memory";
49 reg = <0x00000000 0x00000000 0
50 };
51
52 UIC0: interrupt-controller0 {
53 compatible = "ibm,uic-460ex","
54 interrupt-controller;
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
58 #size-cells = <0>;
59 #interrupt-cells = <2>;
60 };
61
62 UIC1: interrupt-controller1 {
63 compatible = "ibm,uic-460ex","
64 interrupt-controller;
65 cell-index = <1>;
66 dcr-reg = <0x0d0 0x009>;
67 #address-cells = <0>;
68 #size-cells = <0>;
69 #interrupt-cells = <2>;
70 interrupts = <0x1e 0x4 0x1f 0x
71 interrupt-parent = <&UIC0>;
72 };
73
74 UIC2: interrupt-controller2 {
75 compatible = "ibm,uic-460ex","
76 interrupt-controller;
77 cell-index = <2>;
78 dcr-reg = <0x0e0 0x009>;
79 #address-cells = <0>;
80 #size-cells = <0>;
81 #interrupt-cells = <2>;
82 interrupts = <0xa 0x4 0xb 0x4>
83 interrupt-parent = <&UIC0>;
84 };
85
86 UIC3: interrupt-controller3 {
87 compatible = "ibm,uic-460ex","
88 interrupt-controller;
89 cell-index = <3>;
90 dcr-reg = <0x0f0 0x009>;
91 #address-cells = <0>;
92 #size-cells = <0>;
93 #interrupt-cells = <2>;
94 interrupts = <0x10 0x4 0x11 0x
95 interrupt-parent = <&UIC0>;
96 };
97
98 SDR0: sdr {
99 compatible = "ibm,sdr-460ex";
100 dcr-reg = <0x00e 0x002>;
101 };
102
103 CPR0: cpr {
104 compatible = "ibm,cpr-460ex";
105 dcr-reg = <0x00c 0x002>;
106 };
107
108 CPM0: cpm {
109 compatible = "ibm,cpm";
110 dcr-access-method = "native";
111 dcr-reg = <0x160 0x003>;
112 unused-units = <0x00000100>;
113 idle-doze = <0x02000000>;
114 standby = <0xfeff791d>;
115 };
116
117 L2C0: l2c {
118 compatible = "ibm,l2-cache-460
119 dcr-reg = <0x020 0x008
120 0x030 0x008>;
121 cache-line-size = <32>;
122 cache-size = <262144>;
123 interrupt-parent = <&UIC1>;
124 interrupts = <11 1>;
125 };
126
127 plb {
128 compatible = "ibm,plb-460ex",
129 #address-cells = <2>;
130 #size-cells = <1>;
131 ranges;
132 clock-frequency = <0>; /* Fill
133
134 SDRAM0: sdram {
135 compatible = "ibm,sdra
136 dcr-reg = <0x010 0x002
137 };
138
139 CRYPTO: crypto@180000 {
140 compatible = "amcc,ppc
141 reg = <4 0x00180000 0x
142 interrupt-parent = <&U
143 interrupts = <0x1d 0x4
144 };
145
146 HWRNG: hwrng@110000 {
147 compatible = "amcc,ppc
148 reg = <4 0x00110000 0x
149 };
150
151 MAL0: mcmal {
152 compatible = "ibm,mcma
153 dcr-reg = <0x180 0x062
154 num-tx-chans = <2>;
155 num-rx-chans = <16>;
156 #address-cells = <0>;
157 #size-cells = <0>;
158 interrupt-parent = <&U
159 interrupts = < /*TXEO
160 /*RXEO
161 /*SERR
162 /*TXDE
163 /*RXDE
164 };
165
166 USB0: ehci@bffd0400 {
167 compatible = "ibm,usb-
168 interrupt-parent = <&U
169 interrupts = <0x1d 4>;
170 reg = <4 0xbffd0400 0x
171 };
172
173 USB1: usb@bffd0000 {
174 compatible = "ohci-le"
175 reg = <4 0xbffd0000 0x
176 interrupt-parent = <&U
177 interrupts = <0x1e 4>;
178 };
179
180 USBOTG0: usbotg@bff80000 {
181 compatible = "amcc,dwc
182 reg = <0x4 0xbff80000
183 interrupt-parent = <&U
184 #interrupt-cells = <1>
185 #address-cells = <0>;
186 #size-cells = <0>;
187 interrupts = <0x0 0x1
188 interrupt-map = </* US
189 /* HI
190 /* DM
191 };
192
193 AHBDMA: dma@bffd0800 {
194 compatible = "snps,dma
195 reg = <4 0xbffd0800 0x
196 interrupt-parent = <&U
197 interrupts = <0x5 0x4>
198 #dma-cells = <3>;
199 };
200
201 SATA0: sata@bffd1000 {
202 compatible = "amcc,sat
203 reg = <4 0xbffd1000 0x
204 interrupt-parent = <&U
205 interrupts = <0x0 0x4>
206 dmas = <&AHBDMA 0 1 0>
207 dma-names = "sata-dma"
208 };
209
210 POB0: opb {
211 compatible = "ibm,opb-
212 #address-cells = <1>;
213 #size-cells = <1>;
214 ranges = <0xb0000000 0
215 clock-frequency = <0>;
216
217 EBC0: ebc {
218 compatible = "
219 dcr-reg = <0x0
220 #address-cells
221 #size-cells =
222 clock-frequenc
223 /* ranges prop
224 interrupts = <
225 interrupt-pare
226
227 nor_flash@0,0
228 compat
229 bank-w
230 reg =
231 #addre
232 #size-
233 partit
234
235
236 };
237 partit
238
239
240 };
241 partit
242
243
244 };
245 partit
246
247
248 };
249 partit
250
251
252 };
253 partit
254
255
256 };
257 partit
258
259
260 };
261 };
262
263 cpld@2,0 {
264 compat
265 reg =
266 };
267
268 ndfc@3,0 {
269 compat
270 reg =
271 ccr =
272 bank-s
273 #addre
274 #size-
275
276 nand {
277
278
279
280
281
282
283
284
285
286
287
288 };
289 };
290 };
291
292 UART0: serial@ef600300
293 device_type =
294 compatible = "
295 reg = <0xef600
296 virtual-reg =
297 clock-frequenc
298 current-speed
299 interrupt-pare
300 interrupts = <
301 };
302
303 UART1: serial@ef600400
304 device_type =
305 compatible = "
306 reg = <0xef600
307 virtual-reg =
308 clock-frequenc
309 current-speed
310 interrupt-pare
311 interrupts = <
312 };
313
314 IIC0: i2c@ef600700 {
315 compatible = "
316 reg = <0xef600
317 interrupt-pare
318 interrupts = <
319 #address-cells
320 #size-cells =
321 rtc@68 {
322 compat
323 reg =
324 interr
325 interr
326 };
327 sttm@48 {
328 compat
329 reg =
330 interr
331 interr
332 };
333 };
334
335 IIC1: i2c@ef600800 {
336 compatible = "
337 reg = <0xef600
338 interrupt-pare
339 interrupts = <
340 };
341
342 GPIO0: gpio@ef600b00 {
343 compatible = "
344 reg = <0xef600
345 gpio-controlle
346 };
347
348 ZMII0: emac-zmii@ef600
349 compatible = "
350 reg = <0xef600
351 };
352
353 RGMII0: emac-rgmii@ef6
354 compatible = "
355 reg = <0xef601
356 has-mdio;
357 };
358
359 TAH0: emac-tah@ef60135
360 compatible = "
361 reg = <0xef601
362 };
363
364 TAH1: emac-tah@ef60145
365 compatible = "
366 reg = <0xef601
367 };
368
369 EMAC0: ethernet@ef600e
370 device_type =
371 compatible = "
372 interrupt-pare
373 interrupts = <
374 #interrupt-cel
375 #address-cells
376 #size-cells =
377 interrupt-map
378
379 reg = <0xef600
380 local-mac-addr
381 mal-device = <
382 mal-tx-channel
383 mal-rx-channel
384 cell-index = <
385 max-frame-size
386 rx-fifo-size =
387 tx-fifo-size =
388 rx-fifo-size-g
389 phy-mode = "rg
390 phy-map = <0x0
391 rgmii-device =
392 rgmii-channel
393 tah-device = <
394 tah-channel =
395 has-inverted-s
396 has-new-stacr-
397 };
398
399 EMAC1: ethernet@ef600f
400 device_type =
401 compatible = "
402 interrupt-pare
403 interrupts = <
404 #interrupt-cel
405 #address-cells
406 #size-cells =
407 interrupt-map
408
409 reg = <0xef600
410 local-mac-addr
411 mal-device = <
412 mal-tx-channel
413 mal-rx-channel
414 cell-index = <
415 max-frame-size
416 rx-fifo-size =
417 tx-fifo-size =
418 rx-fifo-size-g
419 phy-mode = "rg
420 phy-map = <0x0
421 rgmii-device =
422 rgmii-channel
423 tah-device = <
424 tah-channel =
425 has-inverted-s
426 has-new-stacr-
427 mdio-device =
428 };
429 };
430
431 PCIX0: pci@c0ec00000 {
432 device_type = "pci";
433 #interrupt-cells = <1>
434 #size-cells = <2>;
435 #address-cells = <3>;
436 compatible = "ibm,plb-
437 primary;
438 large-inbound-windows;
439 enable-msi-hole;
440 reg = <0x0000000c 0x0e
441 0x00000000 0x00
442 0x0000000c 0x0e
443 0x0000000c 0x0e
444 0x0000000c 0x0e
445
446 /* Outbound ranges, on
447 * later cannot be cha
448 */
449 ranges = <0x02000000 0
450 0x02000000 0
451 0x01000000 0
452
453 /* Inbound 2GB range s
454 dma-ranges = <0x420000
455
456 /* This drives busses
457 bus-range = <0x0 0x3f>
458
459 /* All PCI interrupts
460 interrupt-map-mask = <
461 interrupt-map = < 0x0
462 };
463
464 PCIE0: pcie@d00000000 {
465 device_type = "pci";
466 #interrupt-cells = <1>
467 #size-cells = <2>;
468 #address-cells = <3>;
469 compatible = "ibm,plb-
470 primary;
471 port = <0x0>; /* port
472 reg = <0x0000000d 0x00
473 0x0000000c 0x08
474 dcr-reg = <0x100 0x020
475 sdr-base = <0x300>;
476
477 /* Outbound ranges, on
478 * later cannot be cha
479 */
480 ranges = <0x02000000 0
481 0x02000000 0
482 0x01000000 0
483
484 /* Inbound 2GB range s
485 dma-ranges = <0x420000
486
487 /* This drives busses
488 bus-range = <0x40 0x7f
489
490 /* Legacy interrupts (
491 * to invert PCIe lega
492 * We are de-swizzling
493 * port of the root co
494 * to avoid putting a
495 * below are basically
496 * The real slot is on
497 */
498 interrupt-map-mask = <
499 interrupt-map = <
500 0x0 0x0 0x0 0x
501 0x0 0x0 0x0 0x
502 0x0 0x0 0x0 0x
503 0x0 0x0 0x0 0x
504 };
505
506 PCIE1: pcie@d20000000 {
507 device_type = "pci";
508 #interrupt-cells = <1>
509 #size-cells = <2>;
510 #address-cells = <3>;
511 compatible = "ibm,plb-
512 primary;
513 port = <0x1>; /* port
514 reg = <0x0000000d 0x20
515 0x0000000c 0x08
516 dcr-reg = <0x120 0x020
517 sdr-base = <0x340>;
518
519 /* Outbound ranges, on
520 * later cannot be cha
521 */
522 ranges = <0x02000000 0
523 0x02000000 0
524 0x01000000 0
525
526 /* Inbound 2GB range s
527 dma-ranges = <0x420000
528
529 /* This drives busses
530 bus-range = <0x80 0xbf
531
532 /* Legacy interrupts (
533 * to invert PCIe lega
534 * We are de-swizzling
535 * port of the root co
536 * to avoid putting a
537 * below are basically
538 * The real slot is on
539 */
540 interrupt-map-mask = <
541 interrupt-map = <
542 0x0 0x0 0x0 0x
543 0x0 0x0 0x0 0x
544 0x0 0x0 0x0 0x
545 0x0 0x0 0x0 0x
546 };
547 };
548 };
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