1 /*
2 * B4860DS Device Tree Source
3 *
4 * Copyright 2012 - 2015 Freescale Semiconduct
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT
33 */
34
35 /include/ "b4860si-pre.dtsi"
36 /include/ "b4qds.dtsi"
37
38 / {
39 model = "fsl,B4860QDS";
40 compatible = "fsl,B4860QDS";
41
42 aliases {
43 phy_sgmii_1e = &phy_sgmii_1e;
44 phy_sgmii_1f = &phy_sgmii_1f;
45 phy_xaui_slot1 = &phy_xaui_slo
46 phy_xaui_slot2 = &phy_xaui_slo
47 };
48
49 ifc: localbus@ffe124000 {
50 board-control@3,0 {
51 compatible = "fsl,b486
52 };
53 };
54
55 soc@ffe000000 {
56 fman@400000 {
57 ethernet@e8000 {
58 phy-handle = <
59 phy-connection
60 };
61
62 ethernet@ea000 {
63 phy-handle = <
64 phy-connection
65 };
66
67 ethernet@f0000 {
68 phy-handle = <
69 phy-connection
70 };
71
72 ethernet@f2000 {
73 phy-handle = <
74 phy-connection
75 };
76
77 mdio@fc000 {
78 phy_sgmii_1e:
79 reg =
80 status
81 };
82
83 phy_sgmii_1f:
84 reg =
85 status
86 };
87 };
88
89 mdio@fd000 {
90 phy_xaui_slot1
91 compat
92 reg =
93 status
94 };
95
96 phy_xaui_slot2
97 compat
98 reg =
99 status
100 };
101 };
102 };
103 };
104
105 rio: rapidio@ffe0c0000 {
106 reg = <0xf 0xfe0c0000 0 0x1100
107
108 port1 {
109 ranges = <0 0 0xc 0x20
110 };
111 port2 {
112 ranges = <0 0 0xc 0x30
113 };
114 };
115 };
116
117 /include/ "b4860si-post.dtsi"
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