1 /* 1 /*
2 * B4420 Silicon/SoC Device Tree Source (post 2 * B4420 Silicon/SoC Device Tree Source (post include)
3 * 3 *
4 * Copyright 2012 - 2015 Freescale Semiconduct 4 * Copyright 2012 - 2015 Freescale Semiconductor, Inc.
5 * 5 *
6 * Redistribution and use in source and binary 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that t 7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must r 8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and t 9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must r 10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and t 11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials 12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semicon 13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used 14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without sp 15 * derived from this software without specific prior written permission.
16 * 16 *
17 * 17 *
18 * ALTERNATIVELY, this software may be distrib 18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as publi 19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that Licens 20 * Foundation, either version 2 of that License or (at your option) any
21 * later version. 21 * later version.
22 * 22 *
23 * This software is provided by Freescale Semi 23 * This software is provided by Freescale Semiconductor "as is" and any
24 * express or implied warranties, including, b 24 * express or implied warranties, including, but not limited to, the implied
25 * warranties of merchantability and fitness f 25 * warranties of merchantability and fitness for a particular purpose are
26 * disclaimed. In no event shall Freescale Sem 26 * disclaimed. In no event shall Freescale Semiconductor be liable for any
27 * direct, indirect, incidental, special, exem 27 * direct, indirect, incidental, special, exemplary, or consequential damages
28 * (including, but not limited to, procurement 28 * (including, but not limited to, procurement of substitute goods or services;
29 * loss of use, data, or profits; or business 29 * loss of use, data, or profits; or business interruption) however caused and
30 * on any theory of liability, whether in cont 30 * on any theory of liability, whether in contract, strict liability, or tort
31 * (including negligence or otherwise) arising 31 * (including negligence or otherwise) arising in any way out of the use of
32 * this software, even if advised of the possi 32 * this software, even if advised of the possibility of such damage.
33 */ 33 */
34 34
35 &bman_fbpr { 35 &bman_fbpr {
36 compatible = "fsl,bman-fbpr"; 36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>; 37 alloc-ranges = <0 0 0x10000 0>;
38 }; 38 };
39 39
40 &qman_fqd { 40 &qman_fqd {
41 compatible = "fsl,qman-fqd"; 41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>; 42 alloc-ranges = <0 0 0x10000 0>;
43 }; 43 };
44 44
45 &qman_pfdr { 45 &qman_pfdr {
46 compatible = "fsl,qman-pfdr"; 46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>; 47 alloc-ranges = <0 0 0x10000 0>;
48 }; 48 };
49 49
50 &ifc { 50 &ifc {
51 #address-cells = <2>; 51 #address-cells = <2>;
52 #size-cells = <1>; 52 #size-cells = <1>;
53 compatible = "fsl,ifc"; !! 53 compatible = "fsl,ifc", "simple-bus";
54 interrupts = <25 2 0 0>; 54 interrupts = <25 2 0 0>;
55 }; 55 };
56 56
57 /* controller at 0x200000 */ 57 /* controller at 0x200000 */
58 &pci0 { 58 &pci0 {
59 compatible = "fsl,b4-pcie", "fsl,qoriq 59 compatible = "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4";
60 device_type = "pci"; 60 device_type = "pci";
61 #size-cells = <2>; 61 #size-cells = <2>;
62 #address-cells = <3>; 62 #address-cells = <3>;
63 bus-range = <0x0 0xff>; 63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>; 64 interrupts = <20 2 0 0>;
65 fsl,iommu-parent = <&pamu0>; 65 fsl,iommu-parent = <&pamu0>;
66 pcie@0 { 66 pcie@0 {
67 #interrupt-cells = <1>; 67 #interrupt-cells = <1>;
68 #size-cells = <2>; 68 #size-cells = <2>;
69 #address-cells = <3>; 69 #address-cells = <3>;
70 device_type = "pci"; 70 device_type = "pci";
71 reg = <0 0 0 0 0>; 71 reg = <0 0 0 0 0>;
72 interrupts = <20 2 0 0>; 72 interrupts = <20 2 0 0>;
73 interrupt-map-mask = <0xf800 0 73 interrupt-map-mask = <0xf800 0 0 7>;
74 interrupt-map = < 74 interrupt-map = <
75 /* IDSEL 0x0 */ 75 /* IDSEL 0x0 */
76 0000 0 0 1 &mpic 40 1 76 0000 0 0 1 &mpic 40 1 0 0
77 0000 0 0 2 &mpic 1 1 0 77 0000 0 0 2 &mpic 1 1 0 0
78 0000 0 0 3 &mpic 2 1 0 78 0000 0 0 3 &mpic 2 1 0 0
79 0000 0 0 4 &mpic 3 1 0 79 0000 0 0 4 &mpic 3 1 0 0
80 >; 80 >;
81 }; 81 };
82 }; 82 };
83 83
84 &dcsr { 84 &dcsr {
85 #address-cells = <1>; 85 #address-cells = <1>;
86 #size-cells = <1>; 86 #size-cells = <1>;
87 compatible = "fsl,dcsr", "simple-bus"; 87 compatible = "fsl,dcsr", "simple-bus";
88 88
89 dcsr-epu@0 { 89 dcsr-epu@0 {
90 compatible = "fsl,b4-dcsr-epu" 90 compatible = "fsl,b4-dcsr-epu", "fsl,dcsr-epu";
91 interrupts = <52 2 0 0 91 interrupts = <52 2 0 0
92 84 2 0 0 92 84 2 0 0
93 85 2 0 0 93 85 2 0 0
94 94 2 0 0 94 94 2 0 0
95 95 2 0 0>; 95 95 2 0 0>;
96 reg = <0x0 0x1000>; 96 reg = <0x0 0x1000>;
97 }; 97 };
98 dcsr-npc { 98 dcsr-npc {
99 compatible = "fsl,b4-dcsr-cnpc 99 compatible = "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc";
100 reg = <0x1000 0x1000 0x1002000 100 reg = <0x1000 0x1000 0x1002000 0x10000>;
101 }; 101 };
102 dcsr-nxc@2000 { 102 dcsr-nxc@2000 {
103 compatible = "fsl,dcsr-nxc"; 103 compatible = "fsl,dcsr-nxc";
104 reg = <0x2000 0x1000>; 104 reg = <0x2000 0x1000>;
105 }; 105 };
106 dcsr-corenet { 106 dcsr-corenet {
107 compatible = "fsl,dcsr-corenet 107 compatible = "fsl,dcsr-corenet";
108 reg = <0x8000 0x1000 0x1A000 0 108 reg = <0x8000 0x1000 0x1A000 0x1000>;
109 }; 109 };
110 dcsr-dpaa@9000 { 110 dcsr-dpaa@9000 {
111 compatible = "fsl,b4-dcsr-dpaa 111 compatible = "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa";
112 reg = <0x9000 0x1000>; 112 reg = <0x9000 0x1000>;
113 }; 113 };
114 dcsr-ocn@11000 { 114 dcsr-ocn@11000 {
115 compatible = "fsl,b4-dcsr-ocn" 115 compatible = "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn";
116 reg = <0x11000 0x1000>; 116 reg = <0x11000 0x1000>;
117 }; 117 };
118 dcsr-ddr@12000 { 118 dcsr-ddr@12000 {
119 compatible = "fsl,dcsr-ddr"; 119 compatible = "fsl,dcsr-ddr";
120 dev-handle = <&ddr1>; 120 dev-handle = <&ddr1>;
121 reg = <0x12000 0x1000>; 121 reg = <0x12000 0x1000>;
122 }; 122 };
123 dcsr-nal@18000 { 123 dcsr-nal@18000 {
124 compatible = "fsl,b4-dcsr-nal" 124 compatible = "fsl,b4-dcsr-nal", "fsl,dcsr-nal";
125 reg = <0x18000 0x1000>; 125 reg = <0x18000 0x1000>;
126 }; 126 };
127 dcsr-rcpm@22000 { 127 dcsr-rcpm@22000 {
128 compatible = "fsl,b4-dcsr-rcpm 128 compatible = "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm";
129 reg = <0x22000 0x1000>; 129 reg = <0x22000 0x1000>;
130 }; 130 };
131 dcsr-snpc@30000 { 131 dcsr-snpc@30000 {
132 compatible = "fsl,b4-dcsr-snpc 132 compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
133 reg = <0x30000 0x1000 0x102200 133 reg = <0x30000 0x1000 0x1022000 0x10000>;
134 }; 134 };
135 dcsr-snpc@31000 { 135 dcsr-snpc@31000 {
136 compatible = "fsl,b4-dcsr-snpc 136 compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
137 reg = <0x31000 0x1000 0x104200 137 reg = <0x31000 0x1000 0x1042000 0x10000>;
138 }; 138 };
139 dcsr-cpu-sb-proxy@100000 { 139 dcsr-cpu-sb-proxy@100000 {
140 compatible = "fsl,dcsr-e6500-s 140 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
141 cpu-handle = <&cpu0>; 141 cpu-handle = <&cpu0>;
142 reg = <0x100000 0x1000 0x10100 142 reg = <0x100000 0x1000 0x101000 0x1000>;
143 }; 143 };
144 }; 144 };
145 145
146 &bportals { 146 &bportals {
147 #address-cells = <0x1>; 147 #address-cells = <0x1>;
148 #size-cells = <0x1>; 148 #size-cells = <0x1>;
149 compatible = "simple-bus"; 149 compatible = "simple-bus";
150 150
151 bman-portal@0 { 151 bman-portal@0 {
152 compatible = "fsl,bman-portal" 152 compatible = "fsl,bman-portal";
153 reg = <0x0 0x4000>, <0x1000000 153 reg = <0x0 0x4000>, <0x1000000 0x1000>;
154 interrupts = <105 2 0 0>; 154 interrupts = <105 2 0 0>;
155 }; 155 };
156 bman-portal@4000 { 156 bman-portal@4000 {
157 compatible = "fsl,bman-portal" 157 compatible = "fsl,bman-portal";
158 reg = <0x4000 0x4000>, <0x1001 158 reg = <0x4000 0x4000>, <0x1001000 0x1000>;
159 interrupts = <107 2 0 0>; 159 interrupts = <107 2 0 0>;
160 }; 160 };
161 bman-portal@8000 { 161 bman-portal@8000 {
162 compatible = "fsl,bman-portal" 162 compatible = "fsl,bman-portal";
163 reg = <0x8000 0x4000>, <0x1002 163 reg = <0x8000 0x4000>, <0x1002000 0x1000>;
164 interrupts = <109 2 0 0>; 164 interrupts = <109 2 0 0>;
165 }; 165 };
166 bman-portal@c000 { 166 bman-portal@c000 {
167 compatible = "fsl,bman-portal" 167 compatible = "fsl,bman-portal";
168 reg = <0xc000 0x4000>, <0x1003 168 reg = <0xc000 0x4000>, <0x1003000 0x1000>;
169 interrupts = <111 2 0 0>; 169 interrupts = <111 2 0 0>;
170 }; 170 };
171 bman-portal@10000 { 171 bman-portal@10000 {
172 compatible = "fsl,bman-portal" 172 compatible = "fsl,bman-portal";
173 reg = <0x10000 0x4000>, <0x100 173 reg = <0x10000 0x4000>, <0x1004000 0x1000>;
174 interrupts = <113 2 0 0>; 174 interrupts = <113 2 0 0>;
175 }; 175 };
176 bman-portal@14000 { 176 bman-portal@14000 {
177 compatible = "fsl,bman-portal" 177 compatible = "fsl,bman-portal";
178 reg = <0x14000 0x4000>, <0x100 178 reg = <0x14000 0x4000>, <0x1005000 0x1000>;
179 interrupts = <115 2 0 0>; 179 interrupts = <115 2 0 0>;
180 }; 180 };
181 bman-portal@18000 { 181 bman-portal@18000 {
182 compatible = "fsl,bman-portal" 182 compatible = "fsl,bman-portal";
183 reg = <0x18000 0x4000>, <0x100 183 reg = <0x18000 0x4000>, <0x1006000 0x1000>;
184 interrupts = <117 2 0 0>; 184 interrupts = <117 2 0 0>;
185 }; 185 };
186 bman-portal@1c000 { 186 bman-portal@1c000 {
187 compatible = "fsl,bman-portal" 187 compatible = "fsl,bman-portal";
188 reg = <0x1c000 0x4000>, <0x100 188 reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
189 interrupts = <119 2 0 0>; 189 interrupts = <119 2 0 0>;
190 }; 190 };
191 bman-portal@20000 { 191 bman-portal@20000 {
192 compatible = "fsl,bman-portal" 192 compatible = "fsl,bman-portal";
193 reg = <0x20000 0x4000>, <0x100 193 reg = <0x20000 0x4000>, <0x1008000 0x1000>;
194 interrupts = <121 2 0 0>; 194 interrupts = <121 2 0 0>;
195 }; 195 };
196 bman-portal@24000 { 196 bman-portal@24000 {
197 compatible = "fsl,bman-portal" 197 compatible = "fsl,bman-portal";
198 reg = <0x24000 0x4000>, <0x100 198 reg = <0x24000 0x4000>, <0x1009000 0x1000>;
199 interrupts = <123 2 0 0>; 199 interrupts = <123 2 0 0>;
200 }; 200 };
201 bman-portal@28000 { 201 bman-portal@28000 {
202 compatible = "fsl,bman-portal" 202 compatible = "fsl,bman-portal";
203 reg = <0x28000 0x4000>, <0x100 203 reg = <0x28000 0x4000>, <0x100a000 0x1000>;
204 interrupts = <125 2 0 0>; 204 interrupts = <125 2 0 0>;
205 }; 205 };
206 bman-portal@2c000 { 206 bman-portal@2c000 {
207 compatible = "fsl,bman-portal" 207 compatible = "fsl,bman-portal";
208 reg = <0x2c000 0x4000>, <0x100 208 reg = <0x2c000 0x4000>, <0x100b000 0x1000>;
209 interrupts = <127 2 0 0>; 209 interrupts = <127 2 0 0>;
210 }; 210 };
211 bman-portal@30000 { 211 bman-portal@30000 {
212 compatible = "fsl,bman-portal" 212 compatible = "fsl,bman-portal";
213 reg = <0x30000 0x4000>, <0x100 213 reg = <0x30000 0x4000>, <0x100c000 0x1000>;
214 interrupts = <129 2 0 0>; 214 interrupts = <129 2 0 0>;
215 }; 215 };
216 bman-portal@34000 { 216 bman-portal@34000 {
217 compatible = "fsl,bman-portal" 217 compatible = "fsl,bman-portal";
218 reg = <0x34000 0x4000>, <0x100 218 reg = <0x34000 0x4000>, <0x100d000 0x1000>;
219 interrupts = <131 2 0 0>; 219 interrupts = <131 2 0 0>;
220 }; 220 };
221 }; 221 };
222 222
223 &qportals { 223 &qportals {
224 #address-cells = <0x1>; 224 #address-cells = <0x1>;
225 #size-cells = <0x1>; 225 #size-cells = <0x1>;
226 compatible = "simple-bus"; 226 compatible = "simple-bus";
227 227
228 qportal0: qman-portal@0 { 228 qportal0: qman-portal@0 {
229 compatible = "fsl,qman-portal" 229 compatible = "fsl,qman-portal";
230 reg = <0x0 0x4000>, <0x1000000 230 reg = <0x0 0x4000>, <0x1000000 0x1000>;
231 interrupts = <104 0x2 0 0>; 231 interrupts = <104 0x2 0 0>;
232 cell-index = <0x0>; 232 cell-index = <0x0>;
233 }; 233 };
234 qportal1: qman-portal@4000 { 234 qportal1: qman-portal@4000 {
235 compatible = "fsl,qman-portal" 235 compatible = "fsl,qman-portal";
236 reg = <0x4000 0x4000>, <0x1001 236 reg = <0x4000 0x4000>, <0x1001000 0x1000>;
237 interrupts = <106 0x2 0 0>; 237 interrupts = <106 0x2 0 0>;
238 cell-index = <0x1>; 238 cell-index = <0x1>;
239 }; 239 };
240 qportal2: qman-portal@8000 { 240 qportal2: qman-portal@8000 {
241 compatible = "fsl,qman-portal" 241 compatible = "fsl,qman-portal";
242 reg = <0x8000 0x4000>, <0x1002 242 reg = <0x8000 0x4000>, <0x1002000 0x1000>;
243 interrupts = <108 0x2 0 0>; 243 interrupts = <108 0x2 0 0>;
244 cell-index = <0x2>; 244 cell-index = <0x2>;
245 }; 245 };
246 qportal3: qman-portal@c000 { 246 qportal3: qman-portal@c000 {
247 compatible = "fsl,qman-portal" 247 compatible = "fsl,qman-portal";
248 reg = <0xc000 0x4000>, <0x1003 248 reg = <0xc000 0x4000>, <0x1003000 0x1000>;
249 interrupts = <110 0x2 0 0>; 249 interrupts = <110 0x2 0 0>;
250 cell-index = <0x3>; 250 cell-index = <0x3>;
251 }; 251 };
252 qportal4: qman-portal@10000 { 252 qportal4: qman-portal@10000 {
253 compatible = "fsl,qman-portal" 253 compatible = "fsl,qman-portal";
254 reg = <0x10000 0x4000>, <0x100 254 reg = <0x10000 0x4000>, <0x1004000 0x1000>;
255 interrupts = <112 0x2 0 0>; 255 interrupts = <112 0x2 0 0>;
256 cell-index = <0x4>; 256 cell-index = <0x4>;
257 }; 257 };
258 qportal5: qman-portal@14000 { 258 qportal5: qman-portal@14000 {
259 compatible = "fsl,qman-portal" 259 compatible = "fsl,qman-portal";
260 reg = <0x14000 0x4000>, <0x100 260 reg = <0x14000 0x4000>, <0x1005000 0x1000>;
261 interrupts = <114 0x2 0 0>; 261 interrupts = <114 0x2 0 0>;
262 cell-index = <0x5>; 262 cell-index = <0x5>;
263 }; 263 };
264 qportal6: qman-portal@18000 { 264 qportal6: qman-portal@18000 {
265 compatible = "fsl,qman-portal" 265 compatible = "fsl,qman-portal";
266 reg = <0x18000 0x4000>, <0x100 266 reg = <0x18000 0x4000>, <0x1006000 0x1000>;
267 interrupts = <116 0x2 0 0>; 267 interrupts = <116 0x2 0 0>;
268 cell-index = <0x6>; 268 cell-index = <0x6>;
269 }; 269 };
270 qportal7: qman-portal@1c000 { 270 qportal7: qman-portal@1c000 {
271 compatible = "fsl,qman-portal" 271 compatible = "fsl,qman-portal";
272 reg = <0x1c000 0x4000>, <0x100 272 reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
273 interrupts = <118 0x2 0 0>; 273 interrupts = <118 0x2 0 0>;
274 cell-index = <0x7>; 274 cell-index = <0x7>;
275 }; 275 };
276 qportal8: qman-portal@20000 { 276 qportal8: qman-portal@20000 {
277 compatible = "fsl,qman-portal" 277 compatible = "fsl,qman-portal";
278 reg = <0x20000 0x4000>, <0x100 278 reg = <0x20000 0x4000>, <0x1008000 0x1000>;
279 interrupts = <120 0x2 0 0>; 279 interrupts = <120 0x2 0 0>;
280 cell-index = <0x8>; 280 cell-index = <0x8>;
281 }; 281 };
282 qportal9: qman-portal@24000 { 282 qportal9: qman-portal@24000 {
283 compatible = "fsl,qman-portal" 283 compatible = "fsl,qman-portal";
284 reg = <0x24000 0x4000>, <0x100 284 reg = <0x24000 0x4000>, <0x1009000 0x1000>;
285 interrupts = <122 0x2 0 0>; 285 interrupts = <122 0x2 0 0>;
286 cell-index = <0x9>; 286 cell-index = <0x9>;
287 }; 287 };
288 qportal10: qman-portal@28000 { 288 qportal10: qman-portal@28000 {
289 compatible = "fsl,qman-portal" 289 compatible = "fsl,qman-portal";
290 reg = <0x28000 0x4000>, <0x100 290 reg = <0x28000 0x4000>, <0x100a000 0x1000>;
291 interrupts = <124 0x2 0 0>; 291 interrupts = <124 0x2 0 0>;
292 cell-index = <0xa>; 292 cell-index = <0xa>;
293 }; 293 };
294 qportal11: qman-portal@2c000 { 294 qportal11: qman-portal@2c000 {
295 compatible = "fsl,qman-portal" 295 compatible = "fsl,qman-portal";
296 reg = <0x2c000 0x4000>, <0x100 296 reg = <0x2c000 0x4000>, <0x100b000 0x1000>;
297 interrupts = <126 0x2 0 0>; 297 interrupts = <126 0x2 0 0>;
298 cell-index = <0xb>; 298 cell-index = <0xb>;
299 }; 299 };
300 qportal12: qman-portal@30000 { 300 qportal12: qman-portal@30000 {
301 compatible = "fsl,qman-portal" 301 compatible = "fsl,qman-portal";
302 reg = <0x30000 0x4000>, <0x100 302 reg = <0x30000 0x4000>, <0x100c000 0x1000>;
303 interrupts = <128 0x2 0 0>; 303 interrupts = <128 0x2 0 0>;
304 cell-index = <0xc>; 304 cell-index = <0xc>;
305 }; 305 };
306 qportal13: qman-portal@34000 { 306 qportal13: qman-portal@34000 {
307 compatible = "fsl,qman-portal" 307 compatible = "fsl,qman-portal";
308 reg = <0x34000 0x4000>, <0x100 308 reg = <0x34000 0x4000>, <0x100d000 0x1000>;
309 interrupts = <130 0x2 0 0>; 309 interrupts = <130 0x2 0 0>;
310 cell-index = <0xd>; 310 cell-index = <0xd>;
311 }; 311 };
312 }; 312 };
313 313
314 &soc { 314 &soc {
315 #address-cells = <1>; 315 #address-cells = <1>;
316 #size-cells = <1>; 316 #size-cells = <1>;
317 device_type = "soc"; 317 device_type = "soc";
318 compatible = "simple-bus"; 318 compatible = "simple-bus";
319 319
320 soc-sram-error { 320 soc-sram-error {
321 compatible = "fsl,soc-sram-err 321 compatible = "fsl,soc-sram-error";
322 interrupts = <16 2 1 2>; 322 interrupts = <16 2 1 2>;
323 }; 323 };
324 324
325 corenet-law@0 { 325 corenet-law@0 {
326 compatible = "fsl,corenet-law" 326 compatible = "fsl,corenet-law";
327 reg = <0x0 0x1000>; 327 reg = <0x0 0x1000>;
328 fsl,num-laws = <32>; 328 fsl,num-laws = <32>;
329 }; 329 };
330 330
331 ddr1: memory-controller@8000 { 331 ddr1: memory-controller@8000 {
332 compatible = "fsl,qoriq-memory 332 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
333 reg = <0x8000 0x1000>; 333 reg = <0x8000 0x1000>;
334 interrupts = <16 2 1 8>; 334 interrupts = <16 2 1 8>;
335 }; 335 };
336 336
337 cpc: l3-cache-controller@10000 { 337 cpc: l3-cache-controller@10000 {
338 compatible = "fsl,b4-l3-cache- 338 compatible = "fsl,b4-l3-cache-controller", "cache";
339 reg = <0x10000 0x1000>; 339 reg = <0x10000 0x1000>;
340 interrupts = <16 2 1 4>; 340 interrupts = <16 2 1 4>;
341 }; 341 };
342 342
343 corenet-cf@18000 { 343 corenet-cf@18000 {
344 compatible = "fsl,corenet2-cf" 344 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
345 reg = <0x18000 0x1000>; 345 reg = <0x18000 0x1000>;
346 interrupts = <16 2 1 0>; 346 interrupts = <16 2 1 0>;
347 fsl,ccf-num-csdids = <32>; 347 fsl,ccf-num-csdids = <32>;
348 fsl,ccf-num-snoopids = <32>; 348 fsl,ccf-num-snoopids = <32>;
349 }; 349 };
350 350
351 iommu@20000 { 351 iommu@20000 {
352 compatible = "fsl,pamu-v1.0", 352 compatible = "fsl,pamu-v1.0", "fsl,pamu";
353 reg = <0x20000 0x4000>; 353 reg = <0x20000 0x4000>;
354 fsl,portid-mapping = <0x8000>; 354 fsl,portid-mapping = <0x8000>;
355 #address-cells = <1>; 355 #address-cells = <1>;
356 #size-cells = <1>; 356 #size-cells = <1>;
357 interrupts = < 357 interrupts = <
358 24 2 0 0 358 24 2 0 0
359 16 2 1 1>; 359 16 2 1 1>;
360 360
361 361
362 /* PCIe, DMA, SRIO */ 362 /* PCIe, DMA, SRIO */
363 pamu0: pamu@0 { 363 pamu0: pamu@0 {
364 reg = <0 0x1000>; 364 reg = <0 0x1000>;
365 fsl,primary-cache-geom 365 fsl,primary-cache-geometry = <8 1>;
366 fsl,secondary-cache-ge 366 fsl,secondary-cache-geometry = <32 2>;
367 }; 367 };
368 368
369 /* AXI2, Maple */ 369 /* AXI2, Maple */
370 pamu1: pamu@1000 { 370 pamu1: pamu@1000 {
371 reg = <0x1000 0x1000>; 371 reg = <0x1000 0x1000>;
372 fsl,primary-cache-geom 372 fsl,primary-cache-geometry = <32 1>;
373 fsl,secondary-cache-ge 373 fsl,secondary-cache-geometry = <32 2>;
374 }; 374 };
375 375
376 /* Q/BMan */ 376 /* Q/BMan */
377 pamu2: pamu@2000 { 377 pamu2: pamu@2000 {
378 reg = <0x2000 0x1000>; 378 reg = <0x2000 0x1000>;
379 fsl,primary-cache-geom 379 fsl,primary-cache-geometry = <32 1>;
380 fsl,secondary-cache-ge 380 fsl,secondary-cache-geometry = <32 2>;
381 }; 381 };
382 382
383 /* AXI1, FMAN */ 383 /* AXI1, FMAN */
384 pamu3: pamu@3000 { 384 pamu3: pamu@3000 {
385 reg = <0x3000 0x1000>; 385 reg = <0x3000 0x1000>;
386 fsl,primary-cache-geom 386 fsl,primary-cache-geometry = <32 1>;
387 fsl,secondary-cache-ge 387 fsl,secondary-cache-geometry = <32 2>;
388 }; 388 };
389 }; 389 };
390 390
391 /include/ "qoriq-mpic4.3.dtsi" 391 /include/ "qoriq-mpic4.3.dtsi"
392 392
393 guts: global-utilities@e0000 { 393 guts: global-utilities@e0000 {
394 compatible = "fsl,b4-device-co 394 compatible = "fsl,b4-device-config";
395 reg = <0xe0000 0xe00>; 395 reg = <0xe0000 0xe00>;
396 fsl,has-rstcr; 396 fsl,has-rstcr;
397 fsl,liodn-bits = <12>; 397 fsl,liodn-bits = <12>;
398 }; 398 };
399 399
400 /include/ "qoriq-clockgen2.dtsi" 400 /include/ "qoriq-clockgen2.dtsi"
401 401
402 rcpm: global-utilities@e2000 { 402 rcpm: global-utilities@e2000 {
403 compatible = "fsl,b4-rcpm", "f 403 compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0";
404 reg = <0xe2000 0x1000>; 404 reg = <0xe2000 0x1000>;
405 }; 405 };
406 406
407 /include/ "elo3-dma-0.dtsi" 407 /include/ "elo3-dma-0.dtsi"
408 dma@100300 { 408 dma@100300 {
409 fsl,iommu-parent = <&pamu0>; 409 fsl,iommu-parent = <&pamu0>;
410 fsl,liodn-reg = <&guts 0x580>; 410 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
411 }; 411 };
412 412
413 /include/ "elo3-dma-1.dtsi" 413 /include/ "elo3-dma-1.dtsi"
414 dma@101300 { 414 dma@101300 {
415 fsl,iommu-parent = <&pamu0>; 415 fsl,iommu-parent = <&pamu0>;
416 fsl,liodn-reg = <&guts 0x584>; 416 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
417 }; 417 };
418 418
419 /include/ "qonverge-usb2-dr-0.dtsi" 419 /include/ "qonverge-usb2-dr-0.dtsi"
420 usb0: usb@210000 { 420 usb0: usb@210000 {
421 compatible = "fsl-usb2-dr-v2.4 421 compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
422 fsl,iommu-parent = <&pamu1>; 422 fsl,iommu-parent = <&pamu1>;
423 fsl,liodn-reg = <&guts 0x520>; 423 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
424 }; 424 };
425 425
426 /include/ "qoriq-espi-0.dtsi" 426 /include/ "qoriq-espi-0.dtsi"
427 spi@110000 { 427 spi@110000 {
428 fsl,espi-num-chipselects = <4> 428 fsl,espi-num-chipselects = <4>;
429 }; 429 };
430 430
431 /include/ "qoriq-esdhc-0.dtsi" 431 /include/ "qoriq-esdhc-0.dtsi"
432 sdhc@114000 { 432 sdhc@114000 {
433 sdhci,auto-cmd12; 433 sdhci,auto-cmd12;
434 fsl,iommu-parent = <&pamu1>; 434 fsl,iommu-parent = <&pamu1>;
435 fsl,liodn-reg = <&guts 0x530>; 435 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
436 }; 436 };
437 437
438 /include/ "qoriq-i2c-0.dtsi" 438 /include/ "qoriq-i2c-0.dtsi"
439 /include/ "qoriq-i2c-1.dtsi" 439 /include/ "qoriq-i2c-1.dtsi"
440 /include/ "qoriq-duart-0.dtsi" 440 /include/ "qoriq-duart-0.dtsi"
441 /include/ "qoriq-duart-1.dtsi" 441 /include/ "qoriq-duart-1.dtsi"
442 /include/ "qoriq-sec5.3-0.dtsi" 442 /include/ "qoriq-sec5.3-0.dtsi"
443 443
444 /include/ "qoriq-qman3.dtsi" 444 /include/ "qoriq-qman3.dtsi"
445 qman: qman@318000 { 445 qman: qman@318000 {
446 interrupts = <16 2 1 28>; 446 interrupts = <16 2 1 28>;
447 }; 447 };
448 448
449 /include/ "qoriq-bman1.dtsi" 449 /include/ "qoriq-bman1.dtsi"
450 bman: bman@31a000 { 450 bman: bman@31a000 {
451 interrupts = <16 2 1 29>; 451 interrupts = <16 2 1 29>;
452 }; 452 };
453 453
454 /include/ "qoriq-fman3-0.dtsi" 454 /include/ "qoriq-fman3-0.dtsi"
455 /include/ "qoriq-fman3-0-1g-0.dtsi" 455 /include/ "qoriq-fman3-0-1g-0.dtsi"
456 /include/ "qoriq-fman3-0-1g-1.dtsi" 456 /include/ "qoriq-fman3-0-1g-1.dtsi"
457 /include/ "qoriq-fman3-0-1g-2.dtsi" 457 /include/ "qoriq-fman3-0-1g-2.dtsi"
458 /include/ "qoriq-fman3-0-1g-3.dtsi" 458 /include/ "qoriq-fman3-0-1g-3.dtsi"
459 fman@400000 { 459 fman@400000 {
460 interrupts = <96 2 0 0>, <16 2 460 interrupts = <96 2 0 0>, <16 2 1 30>;
461 461
462 muram@0 { 462 muram@0 {
463 compatible = "fsl,fman 463 compatible = "fsl,fman-muram";
464 reg = <0x0 0x80000>; 464 reg = <0x0 0x80000>;
465 }; 465 };
466 466
467 enet0: ethernet@e0000 { 467 enet0: ethernet@e0000 {
468 }; 468 };
469 469
470 enet1: ethernet@e2000 { 470 enet1: ethernet@e2000 {
471 }; 471 };
472 472
473 enet2: ethernet@e4000 { 473 enet2: ethernet@e4000 {
474 }; 474 };
475 475
476 enet3: ethernet@e6000 { 476 enet3: ethernet@e6000 {
477 }; 477 };
478 478
479 mdio@fc000 { 479 mdio@fc000 {
480 interrupts = <100 1 0 480 interrupts = <100 1 0 0>;
481 }; 481 };
482 482
483 mdio@fd000 { 483 mdio@fd000 {
484 interrupts = <101 1 0 484 interrupts = <101 1 0 0>;
485 }; 485 };
486 }; 486 };
487 }; 487 };
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