1 /* 2 * C293 PCIE Device Tree Source 3 * 4 * Copyright 2013 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary 7 * modification, are permitted provided that t 8 * * Redistributions of source code must r 9 * notice, this list of conditions and t 10 * * Redistributions in binary form must r 11 * notice, this list of conditions and t 12 * documentation and/or other materials 13 * * Neither the name of Freescale Semicon 14 * names of its contributors may be used 15 * derived from this software without sp 16 * 17 * 18 * ALTERNATIVELY, this software may be distrib 19 * GNU General Public License ("GPL") as publi 20 * Foundation, either version 2 of that Licens 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT 33 */ 34 35 /include/ "c293si-pre.dtsi" 36 37 / { 38 model = "fsl,C293PCIE"; 39 compatible = "fsl,C293PCIE"; 40 41 memory { 42 device_type = "memory"; 43 }; 44 45 ifc: memory-controller@fffe1e000 { 46 reg = <0xf 0xffe1e000 0 0x2000 47 ranges = <0x0 0x0 0xf 0xec0000 48 0x1 0x0 0xf 0xff8000 49 0x2 0x0 0xf 0xffdf00 50 51 }; 52 53 soc: soc@fffe00000 { 54 ranges = <0x0 0xf 0xffe00000 0 55 }; 56 57 pci0: pcie@fffe0a000 { 58 reg = <0xf 0xffe0a000 0 0x1000 59 ranges = <0x2000000 0x0 0x8000 60 0x1000000 0x0 0x0000 61 pcie@0 { 62 ranges = <0x2000000 0x 63 0x2000000 0x 64 0x0 0x200000 65 66 0x1000000 0x 67 0x1000000 0x 68 0x0 0x100000 69 }; 70 }; 71 }; 72 73 &ifc { 74 nor@0,0 { 75 #address-cells = <1>; 76 #size-cells = <1>; 77 compatible = "cfi-flash"; 78 reg = <0x0 0x0 0x4000000>; 79 bank-width = <2>; 80 device-width = <1>; 81 82 partition@0 { 83 /* 1MB for DTB Image * 84 reg = <0x0 0x00100000> 85 label = "NOR DTB Image 86 }; 87 88 partition@100000 { 89 /* 8 MB for Linux Kern 90 reg = <0x00100000 0x00 91 label = "NOR Linux Ker 92 }; 93 94 partition@900000 { 95 /* 53MB for rootfs */ 96 reg = <0x00900000 0x03 97 label = "NOR Rootfs Im 98 }; 99 100 partition@3e00000 { 101 /* 1MB for blob encryp 102 reg = <0x03e00000 0x00 103 label = "NOR blob encr 104 }; 105 106 partition@3f00000 { 107 /* 512KB for u-boot Bo 108 reg = <0x03f00000 0x00 109 label = "NOR U-Boot Im 110 read-only; 111 }; 112 }; 113 114 nand@1,0 { 115 #address-cells = <1>; 116 #size-cells = <1>; 117 compatible = "fsl,ifc-nand"; 118 reg = <0x1 0x0 0x10000>; 119 120 partition@0 { 121 /* This location must 122 /* 1MB for u-boot Boot 123 reg = <0x0 0x00100000> 124 label = "NAND U-Boot I 125 read-only; 126 }; 127 128 partition@100000 { 129 /* 1MB for DTB Image * 130 reg = <0x00100000 0x00 131 label = "NAND DTB Imag 132 }; 133 134 partition@200000 { 135 /* 16MB for Linux Kern 136 reg = <0x00200000 0x01 137 label = "NAND Linux Ke 138 }; 139 140 partition@1200000 { 141 /* 4078MB for Root fil 142 reg = <0x00600000 0xfe 143 label = "NAND RFS Imag 144 }; 145 }; 146 147 cpld@2,0 { 148 compatible = "fsl,c293pcie-cpl 149 reg = <0x2 0x0 0x20>; 150 }; 151 }; 152 153 &soc { 154 i2c@3000 { 155 eeprom@50 { 156 compatible = "st,24c10 157 reg = <0x50>; 158 }; 159 160 adt7461@4c { 161 compatible = "adi,adt7 162 reg = <0x4c>; 163 }; 164 }; 165 166 spi@7000 { 167 flash@0 { 168 #address-cells = <1>; 169 #size-cells = <1>; 170 compatible = "spansion 171 reg = <0>; 172 spi-max-frequency = <5 173 174 partition@0 { 175 /* 1MB for u-b 176 /* 1MB for Env 177 reg = <0x0 0x0 178 label = "SPI F 179 read-only; 180 }; 181 182 partition@100000 { 183 /* 512KB for D 184 reg = <0x00100 185 label = "SPI F 186 }; 187 188 partition@180000 { 189 /* 4MB for Lin 190 reg = <0x00180 191 label = "SPI F 192 }; 193 194 partition@580000 { 195 /* 10.5MB for 196 reg = <0x00580 197 label = "SPI F 198 }; 199 }; 200 }; 201 202 mdio@24000 { 203 phy0: ethernet-phy@0 { 204 interrupts = <2 1 0 0> 205 reg = <0x0>; 206 }; 207 208 phy1: ethernet-phy@1 { 209 interrupts = <2 1 0 0> 210 reg = <0x2>; 211 }; 212 }; 213 214 enet0: ethernet@b0000 { 215 phy-handle = <&phy0>; 216 phy-connection-type = "rgmii-i 217 }; 218 219 enet1: ethernet@b1000 { 220 phy-handle = <&phy1>; 221 phy-connection-type = "rgmii-i 222 }; 223 }; 224 /include/ "c293si-post.dtsi"
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