1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * Cyrus 5020 Device Tree Source, based on p50 3 * Cyrus 5020 Device Tree Source, based on p5020ds.dts
4 * 4 *
5 * Copyright 2015 Andy Fleming 5 * Copyright 2015 Andy Fleming
6 * 6 *
7 * p5020ds.dts copyright: 7 * p5020ds.dts copyright:
8 * Copyright 2010 - 2014 Freescale Semiconduct 8 * Copyright 2010 - 2014 Freescale Semiconductor Inc.
9 */ 9 */
10 10
11 /include/ "p5020si-pre.dtsi" 11 /include/ "p5020si-pre.dtsi"
12 12
13 / { 13 / {
14 model = "varisys,CYRUS"; 14 model = "varisys,CYRUS";
15 compatible = "varisys,CYRUS"; 15 compatible = "varisys,CYRUS";
16 #address-cells = <2>; 16 #address-cells = <2>;
17 #size-cells = <2>; 17 #size-cells = <2>;
18 interrupt-parent = <&mpic>; 18 interrupt-parent = <&mpic>;
19 19
20 memory { 20 memory {
21 device_type = "memory"; 21 device_type = "memory";
22 }; 22 };
23 23
24 reserved-memory { 24 reserved-memory {
25 #address-cells = <2>; 25 #address-cells = <2>;
26 #size-cells = <2>; 26 #size-cells = <2>;
27 ranges; 27 ranges;
28 28
29 bman_fbpr: bman-fbpr { 29 bman_fbpr: bman-fbpr {
30 size = <0 0x1000000>; 30 size = <0 0x1000000>;
31 alignment = <0 0x10000 31 alignment = <0 0x1000000>;
32 }; 32 };
33 qman_fqd: qman-fqd { 33 qman_fqd: qman-fqd {
34 size = <0 0x400000>; 34 size = <0 0x400000>;
35 alignment = <0 0x40000 35 alignment = <0 0x400000>;
36 }; 36 };
37 qman_pfdr: qman-pfdr { 37 qman_pfdr: qman-pfdr {
38 size = <0 0x2000000>; 38 size = <0 0x2000000>;
39 alignment = <0 0x20000 39 alignment = <0 0x2000000>;
40 }; 40 };
41 }; 41 };
42 42
43 dcsr: dcsr@f00000000 { 43 dcsr: dcsr@f00000000 {
44 ranges = <0x00000000 0xf 0x000 44 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
45 }; 45 };
46 46
47 bportals: bman-portals@ff4000000 { 47 bportals: bman-portals@ff4000000 {
48 ranges = <0x0 0xf 0xf4000000 0 48 ranges = <0x0 0xf 0xf4000000 0x200000>;
49 }; 49 };
50 50
51 qportals: qman-portals@ff4200000 { 51 qportals: qman-portals@ff4200000 {
52 ranges = <0x0 0xf 0xf4200000 0 52 ranges = <0x0 0xf 0xf4200000 0x200000>;
53 }; 53 };
54 54
55 soc: soc@ffe000000 { 55 soc: soc@ffe000000 {
56 ranges = <0x00000000 0xf 0xfe0 56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
57 reg = <0xf 0xfe000000 0 0x0000 57 reg = <0xf 0xfe000000 0 0x00001000>;
58 spi@110000 { 58 spi@110000 {
59 }; 59 };
60 60
61 i2c@118100 { 61 i2c@118100 {
62 }; 62 };
63 63
64 i2c@119100 { 64 i2c@119100 {
65 rtc@6f { 65 rtc@6f {
66 compatible = " 66 compatible = "microchip,mcp7941x";
67 reg = <0x6f>; 67 reg = <0x6f>;
68 }; 68 };
69 }; 69 };
70 }; 70 };
71 71
72 rio: rapidio@ffe0c0000 { 72 rio: rapidio@ffe0c0000 {
73 reg = <0xf 0xfe0c0000 0 0x1100 73 reg = <0xf 0xfe0c0000 0 0x11000>;
74 74
75 port1 { 75 port1 {
76 ranges = <0 0 0xc 0x20 76 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
77 }; 77 };
78 port2 { 78 port2 {
79 ranges = <0 0 0xc 0x30 79 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
80 }; 80 };
81 }; 81 };
82 82
83 lbc: localbus@ffe124000 { 83 lbc: localbus@ffe124000 {
84 reg = <0xf 0xfe124000 0 0x1000 84 reg = <0xf 0xfe124000 0 0x1000>;
85 ranges = <0 0 0xf 0xe8000000 0 85 ranges = <0 0 0xf 0xe8000000 0x08000000
86 2 0 0xf 0xffa00000 0 86 2 0 0xf 0xffa00000 0x00040000
87 3 0 0xf 0xffdf0000 0 87 3 0 0xf 0xffdf0000 0x00008000>;
88 }; 88 };
89 89
90 pci0: pcie@ffe200000 { 90 pci0: pcie@ffe200000 {
91 reg = <0xf 0xfe200000 0 0x1000 91 reg = <0xf 0xfe200000 0 0x1000>;
92 ranges = <0x02000000 0 0xe0000 92 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
93 0x01000000 0 0x00000 93 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
94 pcie@0 { 94 pcie@0 {
95 ranges = <0x02000000 0 95 ranges = <0x02000000 0 0xe0000000
96 0x02000000 0 96 0x02000000 0 0xe0000000
97 0 0x20000000 97 0 0x20000000
98 98
99 0x01000000 0 99 0x01000000 0 0x00000000
100 0x01000000 0 100 0x01000000 0 0x00000000
101 0 0x00010000 101 0 0x00010000>;
102 }; 102 };
103 }; 103 };
104 104
105 pci1: pcie@ffe201000 { 105 pci1: pcie@ffe201000 {
106 reg = <0xf 0xfe201000 0 0x1000 106 reg = <0xf 0xfe201000 0 0x1000>;
107 ranges = <0x02000000 0x0 0xe00 107 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
108 0x01000000 0x0 0x000 108 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
109 pcie@0 { 109 pcie@0 {
110 ranges = <0x02000000 0 110 ranges = <0x02000000 0 0xe0000000
111 0x02000000 0 111 0x02000000 0 0xe0000000
112 0 0x20000000 112 0 0x20000000
113 113
114 0x01000000 0 114 0x01000000 0 0x00000000
115 0x01000000 0 115 0x01000000 0 0x00000000
116 0 0x00010000 116 0 0x00010000>;
117 }; 117 };
118 }; 118 };
119 119
120 pci2: pcie@ffe202000 { 120 pci2: pcie@ffe202000 {
121 reg = <0xf 0xfe202000 0 0x1000 121 reg = <0xf 0xfe202000 0 0x1000>;
122 ranges = <0x02000000 0 0xe0000 122 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
123 0x01000000 0 0x00000 123 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
124 pcie@0 { 124 pcie@0 {
125 ranges = <0x02000000 0 125 ranges = <0x02000000 0 0xe0000000
126 0x02000000 0 126 0x02000000 0 0xe0000000
127 0 0x20000000 127 0 0x20000000
128 128
129 0x01000000 0 129 0x01000000 0 0x00000000
130 0x01000000 0 130 0x01000000 0 0x00000000
131 0 0x00010000 131 0 0x00010000>;
132 }; 132 };
133 }; 133 };
134 134
135 pci3: pcie@ffe203000 { 135 pci3: pcie@ffe203000 {
136 reg = <0xf 0xfe203000 0 0x1000 136 reg = <0xf 0xfe203000 0 0x1000>;
137 ranges = <0x02000000 0 0xe0000 137 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
138 0x01000000 0 0x00000 138 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
139 pcie@0 { 139 pcie@0 {
140 ranges = <0x02000000 0 140 ranges = <0x02000000 0 0xe0000000
141 0x02000000 0 141 0x02000000 0 0xe0000000
142 0 0x20000000 142 0 0x20000000
143 143
144 0x01000000 0 144 0x01000000 0 0x00000000
145 0x01000000 0 145 0x01000000 0 0x00000000
146 0 0x00010000 146 0 0x00010000>;
147 }; 147 };
148 }; 148 };
149 }; 149 };
150 150
151 /include/ "p5020si-post.dtsi" 151 /include/ "p5020si-post.dtsi"
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.