1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * Keymile kmcent2 Device Tree Source, based o 3 * Keymile kmcent2 Device Tree Source, based on T1040RDB DTS
4 * 4 *
5 * (C) Copyright 2016 5 * (C) Copyright 2016
6 * Valentin Longchamp, Keymile AG, valentin.lo 6 * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
7 * 7 *
8 * Copyright 2014 - 2015 Freescale Semiconduct 8 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
9 */ 9 */
10 10
11 /include/ "t104xsi-pre.dtsi" 11 /include/ "t104xsi-pre.dtsi"
12 12
13 / { 13 / {
14 model = "keymile,kmcent2"; 14 model = "keymile,kmcent2";
15 compatible = "keymile,kmcent2"; 15 compatible = "keymile,kmcent2";
16 16
17 aliases { 17 aliases {
18 front_phy = &front_phy; 18 front_phy = &front_phy;
19 }; 19 };
20 20
21 reserved-memory { 21 reserved-memory {
22 #address-cells = <2>; 22 #address-cells = <2>;
23 #size-cells = <2>; 23 #size-cells = <2>;
24 ranges; 24 ranges;
25 25
26 bman_fbpr: bman-fbpr { 26 bman_fbpr: bman-fbpr {
27 size = <0 0x1000000>; 27 size = <0 0x1000000>;
28 alignment = <0 0x10000 28 alignment = <0 0x1000000>;
29 }; 29 };
30 qman_fqd: qman-fqd { 30 qman_fqd: qman-fqd {
31 size = <0 0x400000>; 31 size = <0 0x400000>;
32 alignment = <0 0x40000 32 alignment = <0 0x400000>;
33 }; 33 };
34 qman_pfdr: qman-pfdr { 34 qman_pfdr: qman-pfdr {
35 size = <0 0x2000000>; 35 size = <0 0x2000000>;
36 alignment = <0 0x20000 36 alignment = <0 0x2000000>;
37 }; 37 };
38 }; 38 };
39 39
40 ifc: localbus@ffe124000 { 40 ifc: localbus@ffe124000 {
41 reg = <0xf 0xfe124000 0 0x2000 41 reg = <0xf 0xfe124000 0 0x2000>;
42 ranges = <0 0 0xf 0xe8000000 0 42 ranges = <0 0 0xf 0xe8000000 0x04000000
43 1 0 0xf 0xfa000000 0 43 1 0 0xf 0xfa000000 0x00010000
44 2 0 0xf 0xfb000000 0 44 2 0 0xf 0xfb000000 0x00010000
45 4 0 0xf 0xc0000000 0 45 4 0 0xf 0xc0000000 0x08000000
46 6 0 0xf 0xd0000000 0 46 6 0 0xf 0xd0000000 0x08000000
47 7 0 0xf 0xd8000000 0 47 7 0 0xf 0xd8000000 0x08000000>;
48 48
49 nor@0,0 { 49 nor@0,0 {
50 #address-cells = <1>; 50 #address-cells = <1>;
51 #size-cells = <1>; 51 #size-cells = <1>;
52 compatible = "cfi-flas 52 compatible = "cfi-flash";
53 reg = <0x0 0x0 0x04000 53 reg = <0x0 0x0 0x04000000>;
54 bank-width = <2>; 54 bank-width = <2>;
55 device-width = <2>; 55 device-width = <2>;
56 }; 56 };
57 57
58 nand@1,0 { 58 nand@1,0 {
59 #address-cells = <1>; 59 #address-cells = <1>;
60 #size-cells = <1>; 60 #size-cells = <1>;
61 compatible = "fsl,ifc- 61 compatible = "fsl,ifc-nand";
62 reg = <0x1 0x0 0x10000 62 reg = <0x1 0x0 0x10000>;
63 }; 63 };
64 64
65 board-control@2,0 { 65 board-control@2,0 {
66 compatible = "keymile, 66 compatible = "keymile,qriox";
67 reg = <0x2 0x0 0x80>; 67 reg = <0x2 0x0 0x80>;
68 }; 68 };
69 69
70 chassis-mgmt@6,0 { 70 chassis-mgmt@6,0 {
71 compatible = "keymile, 71 compatible = "keymile,bfticu";
72 reg = <6 0 0x100>; 72 reg = <6 0 0x100>;
73 interrupt-controller; 73 interrupt-controller;
74 interrupt-parent = <&m 74 interrupt-parent = <&mpic>;
75 interrupts = <11 1 0 0 75 interrupts = <11 1 0 0>;
76 #interrupt-cells = <1> 76 #interrupt-cells = <1>;
77 }; 77 };
78 78
79 }; 79 };
80 80
81 memory { 81 memory {
82 device_type = "memory"; 82 device_type = "memory";
83 }; 83 };
84 84
85 dcsr: dcsr@f00000000 { 85 dcsr: dcsr@f00000000 {
86 ranges = <0x00000000 0xf 0x000 86 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
87 }; 87 };
88 88
89 bportals: bman-portals@ff4000000 { 89 bportals: bman-portals@ff4000000 {
90 ranges = <0x0 0xf 0xf4000000 0 90 ranges = <0x0 0xf 0xf4000000 0x2000000>;
91 }; 91 };
92 92
93 qportals: qman-portals@ff6000000 { 93 qportals: qman-portals@ff6000000 {
94 ranges = <0x0 0xf 0xf6000000 0 94 ranges = <0x0 0xf 0xf6000000 0x2000000>;
95 }; 95 };
96 96
97 soc: soc@ffe000000 { 97 soc: soc@ffe000000 {
98 ranges = <0x00000000 0xf 0xfe0 98 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
99 reg = <0xf 0xfe000000 0 0x0000 99 reg = <0xf 0xfe000000 0 0x00001000>;
100 100
101 spi@110000 { 101 spi@110000 {
102 network-clock@1 { 102 network-clock@1 {
103 compatible = " 103 compatible = "zarlink,zl30364";
104 reg = <1>; 104 reg = <1>;
105 spi-max-freque 105 spi-max-frequency = <1000000>;
106 }; 106 };
107 }; 107 };
108 108
109 sdhc@114000 { 109 sdhc@114000 {
110 status = "disabled"; 110 status = "disabled";
111 }; 111 };
112 112
113 i2c@118000 { 113 i2c@118000 {
114 clock-frequency = <100 114 clock-frequency = <100000>;
115 115
116 mux@70 { 116 mux@70 {
117 compatible = " 117 compatible = "nxp,pca9547";
118 reg = <0x70>; 118 reg = <0x70>;
119 #address-cells 119 #address-cells = <1>;
120 #size-cells = 120 #size-cells = <0>;
121 i2c-mux-idle-d 121 i2c-mux-idle-disconnect;
122 122
123 i2c@0 { 123 i2c@0 {
124 reg = 124 reg = <0>;
125 #addre 125 #address-cells = <1>;
126 #size- 126 #size-cells = <0>;
127 127
128 eeprom 128 eeprom@54 {
129 129 compatible = "atmel,24c02";
130 130 reg = <0x54>;
131 131 pagesize = <2>;
132 132 read-only;
133 133 label = "ddr3-spd";
134 }; 134 };
135 }; 135 };
136 136
137 i2c@7 { 137 i2c@7 {
138 reg = 138 reg = <7>;
139 #addre 139 #address-cells = <1>;
140 #size- 140 #size-cells = <0>;
141 141
142 temp-s 142 temp-sensor@48 {
143 143 compatible = "national,lm75";
144 144 reg = <0x48>;
145 145 label = "SENSOR_0";
146 }; 146 };
147 temp-s 147 temp-sensor@4a {
148 148 compatible = "national,lm75";
149 149 reg = <0x4a>;
150 150 label = "SENSOR_2";
151 }; 151 };
152 temp-s 152 temp-sensor@4b {
153 153 compatible = "national,lm75";
154 154 reg = <0x4b>;
155 155 label = "SENSOR_3";
156 }; 156 };
157 }; 157 };
158 }; 158 };
159 }; 159 };
160 160
161 i2c@118100 { 161 i2c@118100 {
162 clock-frequency = <100 162 clock-frequency = <100000>;
163 163
164 eeprom@50 { 164 eeprom@50 {
165 compatible = " 165 compatible = "atmel,24c08";
166 reg = <0x50>; 166 reg = <0x50>;
167 pagesize = <16 167 pagesize = <16>;
168 }; 168 };
169 169
170 eeprom@54 { 170 eeprom@54 {
171 compatible = " 171 compatible = "atmel,24c08";
172 reg = <0x54>; 172 reg = <0x54>;
173 pagesize = <16 173 pagesize = <16>;
174 }; 174 };
175 }; 175 };
176 176
177 i2c@119000 { 177 i2c@119000 {
178 status = "disabled"; 178 status = "disabled";
179 }; 179 };
180 180
181 i2c@119100 { 181 i2c@119100 {
182 status = "disabled"; 182 status = "disabled";
183 }; 183 };
184 184
185 serial2: serial@11d500 { 185 serial2: serial@11d500 {
186 status = "disabled"; 186 status = "disabled";
187 }; 187 };
188 188
189 serial3: serial@11d600 { 189 serial3: serial@11d600 {
190 status = "disabled"; 190 status = "disabled";
191 }; 191 };
192 192
193 usb0: usb@210000 { 193 usb0: usb@210000 {
194 status = "disabled"; 194 status = "disabled";
195 }; 195 };
196 usb1: usb@211000 { 196 usb1: usb@211000 {
197 status = "disabled"; 197 status = "disabled";
198 }; 198 };
199 199
200 display@180000 { 200 display@180000 {
201 status = "disabled"; 201 status = "disabled";
202 }; 202 };
203 203
204 sata@220000 { 204 sata@220000 {
205 status = "disabled"; 205 status = "disabled";
206 }; 206 };
207 sata@221000 { 207 sata@221000 {
208 status = "disabled"; 208 status = "disabled";
209 }; 209 };
210 210
211 fman@400000 { 211 fman@400000 {
212 ethernet@e0000 { 212 ethernet@e0000 {
213 phy-mode = "sg !! 213 fixed-link = <0 1 1000 0 0>;
214 fixed-link { !! 214 phy-connection-type = "sgmii";
215 speed <<
216 full-d <<
217 }; <<
218 }; 215 };
219 216
220 ethernet@e2000 { 217 ethernet@e2000 {
221 phy-mode = "sg !! 218 fixed-link = <1 1 1000 0 0>;
222 fixed-link { !! 219 phy-connection-type = "sgmii";
223 speed <<
224 full-d <<
225 }; <<
226 }; 220 };
227 221
228 ethernet@e4000 { 222 ethernet@e4000 {
229 status = "disa 223 status = "disabled";
230 }; 224 };
231 225
232 ethernet@e6000 { 226 ethernet@e6000 {
233 status = "disa 227 status = "disabled";
234 }; 228 };
235 229
236 ethernet@e8000 { 230 ethernet@e8000 {
237 phy-handle = < 231 phy-handle = <&front_phy>;
238 phy-mode = "rg !! 232 phy-connection-type = "rgmii";
239 }; 233 };
240 234
241 mdio0: mdio@fc000 { 235 mdio0: mdio@fc000 {
242 front_phy: eth 236 front_phy: ethernet-phy@11 {
243 reg = 237 reg = <0x11>;
244 }; 238 };
245 }; 239 };
246 }; 240 };
247 }; 241 };
248 242
249 243
250 pci0: pcie@ffe240000 { 244 pci0: pcie@ffe240000 {
251 reg = <0xf 0xfe240000 0 0x1000 245 reg = <0xf 0xfe240000 0 0x10000>;
252 ranges = <0x02000000 0 0xe0000 246 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
253 0x01000000 0 0x00000 247 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
254 pcie@0 { 248 pcie@0 {
255 ranges = <0x02000000 0 249 ranges = <0x02000000 0 0xe0000000
256 0x02000000 0 250 0x02000000 0 0xe0000000
257 0 0x20000000 251 0 0x20000000
258 252
259 0x01000000 0 253 0x01000000 0 0x00000000
260 0x01000000 0 254 0x01000000 0 0x00000000
261 0 0x00010000 255 0 0x00010000>;
262 }; 256 };
263 }; 257 };
264 258
265 pci1: pcie@ffe250000 { 259 pci1: pcie@ffe250000 {
266 status = "disabled"; 260 status = "disabled";
267 reg = <0xf 0xfe250000 0 0x1000 <<
268 ranges = <0x02000000 0 0xe0000 <<
269 0x01000000 0 0 0xf 0 <<
270 pcie@0 { <<
271 ranges = <0x02000000 0 <<
272 0x02000000 0 <<
273 0 0x10000000 <<
274 <<
275 0x01000000 0 <<
276 0x01000000 0 <<
277 0 0x00010000 <<
278 }; <<
279 }; 261 };
280 262
281 pci2: pcie@ffe260000 { 263 pci2: pcie@ffe260000 {
282 status = "disabled"; 264 status = "disabled";
283 reg = <0xf 0xfe260000 0 0x1000 <<
284 ranges = <0x02000000 0 0xe0000 <<
285 0x01000000 0 0x00000 <<
286 pcie@0 { <<
287 ranges = <0x02000000 0 <<
288 0x02000000 0 <<
289 0 0x10000000 <<
290 <<
291 0x01000000 0 <<
292 0x01000000 0 <<
293 0 0x00010000 <<
294 }; <<
295 }; 265 };
296 266
297 pci3: pcie@ffe270000 { 267 pci3: pcie@ffe270000 {
298 status = "disabled"; 268 status = "disabled";
299 reg = <0xf 0xfe270000 0 0x1000 <<
300 ranges = <0x02000000 0 0xe0000 <<
301 0x01000000 0 0x00000 <<
302 pcie@0 { <<
303 ranges = <0x02000000 0 <<
304 0x02000000 0 <<
305 0 0x10000000 <<
306 <<
307 0x01000000 0 <<
308 0x01000000 0 <<
309 0 0x00010000 <<
310 }; <<
311 }; 269 };
312 270
313 qe: qe@ffe140000 { 271 qe: qe@ffe140000 {
314 ranges = <0x0 0xf 0xfe140000 0 272 ranges = <0x0 0xf 0xfe140000 0x40000>;
315 reg = <0xf 0xfe140000 0 0x480> 273 reg = <0xf 0xfe140000 0 0x480>;
316 brg-frequency = <0>; 274 brg-frequency = <0>;
317 bus-frequency = <0>; 275 bus-frequency = <0>;
318 276
319 si1: si@700 { 277 si1: si@700 {
320 compatible = "fsl,t104 278 compatible = "fsl,t1040-qe-si";
321 reg = <0x700 0x80>; 279 reg = <0x700 0x80>;
322 }; 280 };
323 281
324 siram1: siram@1000 { 282 siram1: siram@1000 {
325 compatible = "fsl,t104 283 compatible = "fsl,t1040-qe-siram";
326 reg = <0x1000 0x800>; 284 reg = <0x1000 0x800>;
327 }; 285 };
328 286
329 ucc_hdlc: ucc@2000 { 287 ucc_hdlc: ucc@2000 {
330 device_type = "hdlc"; 288 device_type = "hdlc";
331 compatible = "fsl,ucc- 289 compatible = "fsl,ucc-hdlc";
332 rx-clock-name = "clk9" 290 rx-clock-name = "clk9";
333 tx-clock-name = "clk9" 291 tx-clock-name = "clk9";
334 fsl,hdlc-bus; 292 fsl,hdlc-bus;
335 }; 293 };
336 }; 294 };
337 }; 295 };
338 296
339 #include "t1040si-post.dtsi" 297 #include "t1040si-post.dtsi"
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