1 // SPDX-License-Identifier: GPL-2.0-or-later <<
2 /* 1 /*
3 * MPC8536 DS Device Tree Source 2 * MPC8536 DS Device Tree Source
4 * 3 *
5 * Copyright 2008, 2011 Freescale Semiconducto 4 * Copyright 2008, 2011 Freescale Semiconductor, Inc.
>> 5 *
>> 6 * This program is free software; you can redistribute it and/or modify it
>> 7 * under the terms of the GNU General Public License as published by the
>> 8 * Free Software Foundation; either version 2 of the License, or (at your
>> 9 * option) any later version.
6 */ 10 */
7 11
8 /include/ "mpc8536si-pre.dtsi" 12 /include/ "mpc8536si-pre.dtsi"
9 13
10 / { 14 / {
11 model = "fsl,mpc8536ds"; 15 model = "fsl,mpc8536ds";
12 compatible = "fsl,mpc8536ds"; 16 compatible = "fsl,mpc8536ds";
13 17
14 cpus { 18 cpus {
15 #cpus = <1>; 19 #cpus = <1>;
16 #address-cells = <1>; 20 #address-cells = <1>;
17 #size-cells = <0>; 21 #size-cells = <0>;
18 22
19 PowerPC,8536@0 { 23 PowerPC,8536@0 {
20 device_type = "cpu"; 24 device_type = "cpu";
21 reg = <0>; 25 reg = <0>;
22 next-level-cache = <&L 26 next-level-cache = <&L2>;
23 }; 27 };
24 }; 28 };
25 29
26 memory { 30 memory {
27 device_type = "memory"; 31 device_type = "memory";
28 reg = <0 0 0 0>; // Fil 32 reg = <0 0 0 0>; // Filled by U-Boot
29 }; 33 };
30 34
31 lbc: localbus@ffe05000 { 35 lbc: localbus@ffe05000 {
32 reg = <0 0xffe05000 0 0x1000>; 36 reg = <0 0xffe05000 0 0x1000>;
33 37
34 ranges = <0x0 0x0 0x0 0xe80000 38 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
35 0x2 0x0 0x0 0xffa000 39 0x2 0x0 0x0 0xffa00000 0x00040000
36 0x3 0x0 0x0 0xffdf00 40 0x3 0x0 0x0 0xffdf0000 0x00008000>;
37 }; 41 };
38 42
39 board_soc: soc: soc@ffe00000 { 43 board_soc: soc: soc@ffe00000 {
40 ranges = <0x0 0 0xffe00000 0x1 44 ranges = <0x0 0 0xffe00000 0x100000>;
41 }; 45 };
42 46
43 pci0: pci@ffe08000 { 47 pci0: pci@ffe08000 {
44 reg = <0 0xffe08000 0 0x1000>; 48 reg = <0 0xffe08000 0 0x1000>;
45 ranges = <0x02000000 0 0x80000 49 ranges = <0x02000000 0 0x80000000 0 0x80000000 0 0x10000000
46 0x01000000 0 0x00000 50 0x01000000 0 0x00000000 0 0xffc00000 0 0x00010000>;
47 clock-frequency = <66666666>; 51 clock-frequency = <66666666>;
48 interrupt-map-mask = <0xf800 0 52 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
49 interrupt-map = < 53 interrupt-map = <
50 54
51 /* IDSEL 0x11 J17 Slot 55 /* IDSEL 0x11 J17 Slot 1 */
52 0x8800 0 0 1 &mpic 1 1 56 0x8800 0 0 1 &mpic 1 1 0 0
53 0x8800 0 0 2 &mpic 2 1 57 0x8800 0 0 2 &mpic 2 1 0 0
54 0x8800 0 0 3 &mpic 3 1 58 0x8800 0 0 3 &mpic 3 1 0 0
55 0x8800 0 0 4 &mpic 4 1 59 0x8800 0 0 4 &mpic 4 1 0 0>;
56 }; 60 };
57 61
58 pci1: pcie@ffe09000 { 62 pci1: pcie@ffe09000 {
59 reg = <0 0xffe09000 0 0x1000>; 63 reg = <0 0xffe09000 0 0x1000>;
60 ranges = <0x02000000 0 0x98000 64 ranges = <0x02000000 0 0x98000000 0 0x98000000 0 0x08000000
61 0x01000000 0 0x00000 65 0x01000000 0 0x00000000 0 0xffc20000 0 0x00010000>;
62 pcie@0 { 66 pcie@0 {
63 ranges = <0x02000000 0 67 ranges = <0x02000000 0 0x98000000
64 0x02000000 0 68 0x02000000 0 0x98000000
65 0 0x08000000 69 0 0x08000000
66 70
67 0x01000000 0 71 0x01000000 0 0x00000000
68 0x01000000 0 72 0x01000000 0 0x00000000
69 0 0x00010000 73 0 0x00010000>;
70 }; 74 };
71 }; 75 };
72 76
73 pci2: pcie@ffe0a000 { 77 pci2: pcie@ffe0a000 {
74 reg = <0 0xffe0a000 0 0x1000>; 78 reg = <0 0xffe0a000 0 0x1000>;
75 ranges = <0x02000000 0 0x90000 79 ranges = <0x02000000 0 0x90000000 0 0x90000000 0 0x08000000
76 0x01000000 0 0x00000 80 0x01000000 0 0x00000000 0 0xffc10000 0 0x00010000>;
77 pcie@0 { 81 pcie@0 {
78 ranges = <0x02000000 0 82 ranges = <0x02000000 0 0x90000000
79 0x02000000 0 83 0x02000000 0 0x90000000
80 0 0x08000000 84 0 0x08000000
81 85
82 0x01000000 0 86 0x01000000 0 0x00000000
83 0x01000000 0 87 0x01000000 0 0x00000000
84 0 0x00010000 88 0 0x00010000>;
85 }; 89 };
86 }; 90 };
87 91
88 pci3: pcie@ffe0b000 { 92 pci3: pcie@ffe0b000 {
89 reg = <0 0xffe0b000 0 0x1000>; 93 reg = <0 0xffe0b000 0 0x1000>;
90 ranges = <0x02000000 0 0xa0000 94 ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000
91 0x01000000 0 0x00000 95 0x01000000 0 0x00000000 0 0xffc30000 0 0x00010000>;
92 pcie@0 { 96 pcie@0 {
93 ranges = <0x02000000 0 97 ranges = <0x02000000 0 0xa0000000
94 0x02000000 0 98 0x02000000 0 0xa0000000
95 0 0x20000000 99 0 0x20000000
96 100
97 0x01000000 0 101 0x01000000 0 0x00000000
98 0x01000000 0 102 0x01000000 0 0x00000000
99 0 0x00100000 103 0 0x00100000>;
100 }; 104 };
101 }; 105 };
102 }; 106 };
103 107
104 /include/ "mpc8536si-post.dtsi" 108 /include/ "mpc8536si-post.dtsi"
105 /include/ "mpc8536ds.dtsi" 109 /include/ "mpc8536ds.dtsi"
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