1 /*
2 * MPC8568 Silicon/SoC Device Tree Source (pos
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT
33 */
34
35 &lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8568-localbus", "
39 interrupts = <19 2 0 0>;
40 sleep = <&pmc 0x08000000>;
41 };
42
43 /* controller at 0x8000 */
44 &pci0 {
45 compatible = "fsl,mpc8540-pci";
46 device_type = "pci";
47 interrupts = <24 0x2 0 0>;
48 bus-range = <0 0xff>;
49 #interrupt-cells = <1>;
50 #size-cells = <2>;
51 #address-cells = <3>;
52 sleep = <&pmc 0x80000000>;
53 };
54
55 /* controller at 0xa000 */
56 &pci1 {
57 compatible = "fsl,mpc8548-pcie";
58 device_type = "pci";
59 #size-cells = <2>;
60 #address-cells = <3>;
61 bus-range = <0 255>;
62 clock-frequency = <33333333>;
63 interrupts = <26 2 0 0>;
64 sleep = <&pmc 0x20000000>;
65
66 pcie@0 {
67 reg = <0 0 0 0 0>;
68 #interrupt-cells = <1>;
69 #size-cells = <2>;
70 #address-cells = <3>;
71 device_type = "pci";
72 interrupts = <26 2 0 0>;
73 interrupt-map-mask = <0xf800 0
74 interrupt-map = <
75 /* IDSEL 0x0 */
76 0000 0x0 0x0 0x1 &mpic
77 0000 0x0 0x0 0x2 &mpic
78 0000 0x0 0x0 0x3 &mpic
79 0000 0x0 0x0 0x4 &mpic
80 >;
81 };
82 };
83
84 &rio {
85 compatible = "fsl,srio";
86 interrupts = <48 2 0 0>;
87 #address-cells = <2>;
88 #size-cells = <2>;
89 fsl,srio-rmu-handle = <&rmu>;
90 sleep = <&pmc 0x00080000>;
91 ranges;
92
93 port1 {
94 #address-cells = <2>;
95 #size-cells = <2>;
96 cell-index = <1>;
97 };
98 };
99
100 &soc {
101 #address-cells = <1>;
102 #size-cells = <1>;
103 device_type = "soc";
104 compatible = "fsl,mpc8568-immr", "simp
105 bus-frequency = <0>; // Fil
106
107 ecm-law@0 {
108 compatible = "fsl,ecm-law";
109 reg = <0x0 0x1000>;
110 fsl,num-laws = <10>;
111 };
112
113 ecm@1000 {
114 compatible = "fsl,mpc8568-ecm"
115 reg = <0x1000 0x1000>;
116 interrupts = <17 2 0 0>;
117 };
118
119 memory-controller@2000 {
120 compatible = "fsl,mpc8568-memo
121 reg = <0x2000 0x1000>;
122 interrupts = <18 2 0 0>;
123 };
124
125 i2c-sleep-nexus {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "simple-bus";
129 sleep = <&pmc 0x00000004>;
130 ranges;
131
132 /include/ "pq3-i2c-0.dtsi"
133 /include/ "pq3-i2c-1.dtsi"
134
135 };
136
137 duart-sleep-nexus {
138 #address-cells = <1>;
139 #size-cells = <1>;
140 compatible = "simple-bus";
141 sleep = <&pmc 0x00000002>;
142 ranges;
143
144 /include/ "pq3-duart-0.dtsi"
145
146 };
147
148 L2: l2-cache-controller@20000 {
149 compatible = "fsl,mpc8568-l2-c
150 reg = <0x20000 0x1000>;
151 cache-line-size = <32>; // 32
152 cache-size = <0x80000>; // L2,
153 interrupts = <16 2 0 0>;
154 };
155
156 /include/ "pq3-dma-0.dtsi"
157 dma@21300 {
158 sleep = <&pmc 0x00000400>;
159 };
160
161 /include/ "pq3-etsec1-0.dtsi"
162 ethernet@24000 {
163 sleep = <&pmc 0x00000080>;
164 };
165
166 /include/ "pq3-etsec1-1.dtsi"
167 ethernet@25000 {
168 sleep = <&pmc 0x00000040>;
169 };
170
171 par_io@e0100 {
172 reg = <0xe0100 0x100>;
173 device_type = "par_io";
174 };
175
176 /include/ "pq3-sec2.1-0.dtsi"
177 crypto@30000 {
178 sleep = <&pmc 0x01000000>;
179 };
180
181 /include/ "pq3-mpic.dtsi"
182 /include/ "pq3-rmu-0.dtsi"
183 rmu@d3000 {
184 sleep = <&pmc 0x00040000>;
185 };
186
187 global-utilities@e0000 {
188 #address-cells = <1>;
189 #size-cells = <1>;
190 compatible = "fsl,mpc8568-guts
191 reg = <0xe0000 0x1000>;
192 ranges = <0 0xe0000 0x1000>;
193 fsl,has-rstcr;
194
195 pmc: power@70 {
196 compatible = "fsl,mpc8
197 "fsl,mpc8
198 reg = <0x70 0x20>;
199 };
200 };
201 };
202
203 &qe {
204 #address-cells = <1>;
205 #size-cells = <1>;
206 device_type = "qe";
207 compatible = "fsl,qe";
208 sleep = <&pmc 0x00000800>;
209 brg-frequency = <0>;
210 bus-frequency = <396000000>;
211 fsl,qe-num-riscs = <2>;
212 fsl,qe-num-snums = <28>;
213
214 qeic: interrupt-controller@80 {
215 interrupt-controller;
216 compatible = "fsl,qe-ic";
217 #address-cells = <0>;
218 #interrupt-cells = <1>;
219 reg = <0x80 0x80>;
220 interrupts = <46 2 0 0 46 2 0
221 interrupt-parent = <&mpic>;
222 };
223
224 spi@4c0 {
225 #address-cells = <1>;
226 #size-cells = <0>;
227 compatible = "fsl,spi";
228 reg = <0x4c0 0x40>;
229 cell-index = <0>;
230 interrupts = <2>;
231 interrupt-parent = <&qeic>;
232 };
233
234 spi@500 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 cell-index = <1>;
238 compatible = "fsl,spi";
239 reg = <0x500 0x40>;
240 interrupts = <1>;
241 interrupt-parent = <&qeic>;
242 };
243
244 ucc@2000 {
245 cell-index = <1>;
246 reg = <0x2000 0x200>;
247 interrupts = <32>;
248 interrupt-parent = <&qeic>;
249 };
250
251 ucc@3000 {
252 cell-index = <2>;
253 reg = <0x3000 0x200>;
254 interrupts = <33>;
255 interrupt-parent = <&qeic>;
256 };
257
258 muram@10000 {
259 #address-cells = <1>;
260 #size-cells = <1>;
261 compatible = "fsl,qe-muram", "
262 ranges = <0x0 0x10000 0x10000>
263
264 data-only@0 {
265 compatible = "fsl,qe-m
266 "fsl,cpm-
267 reg = <0x0 0x10000>;
268 };
269 };
270 };
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