1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * MPC8569E MDS Device Tree Source 3 * MPC8569E MDS Device Tree Source
4 * 4 *
5 * Copyright (C) 2009 Freescale Semiconductor 5 * Copyright (C) 2009 Freescale Semiconductor Inc.
6 */ 6 */
7 7
8 /include/ "mpc8569si-pre.dtsi" 8 /include/ "mpc8569si-pre.dtsi"
9 9
10 / { 10 / {
11 model = "MPC8569EMDS"; 11 model = "MPC8569EMDS";
12 compatible = "fsl,MPC8569EMDS"; 12 compatible = "fsl,MPC8569EMDS";
13 #address-cells = <2>; 13 #address-cells = <2>;
14 #size-cells = <2>; 14 #size-cells = <2>;
15 interrupt-parent = <&mpic>; 15 interrupt-parent = <&mpic>;
16 16
17 aliases { 17 aliases {
18 ethernet2 = &enet2; 18 ethernet2 = &enet2;
19 ethernet3 = &enet3; 19 ethernet3 = &enet3;
20 ethernet5 = &enet5; 20 ethernet5 = &enet5;
21 ethernet7 = &enet7; 21 ethernet7 = &enet7;
22 rapidio0 = &rio; 22 rapidio0 = &rio;
23 }; 23 };
24 24
25 memory { 25 memory {
26 device_type = "memory"; 26 device_type = "memory";
27 }; 27 };
28 28
29 lbc: localbus@e0005000 { 29 lbc: localbus@e0005000 {
30 reg = <0x0 0xe0005000 0x0 0x10 30 reg = <0x0 0xe0005000 0x0 0x1000>;
31 31
32 ranges = <0x0 0x0 0x0 0xfe0000 32 ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
33 0x1 0x0 0x0 0xf80000 33 0x1 0x0 0x0 0xf8000000 0x00008000
34 0x2 0x0 0x0 0xf00000 34 0x2 0x0 0x0 0xf0000000 0x04000000
35 0x3 0x0 0x0 0xfc0000 35 0x3 0x0 0x0 0xfc000000 0x00008000
36 0x4 0x0 0x0 0xf80080 36 0x4 0x0 0x0 0xf8008000 0x00008000
37 0x5 0x0 0x0 0xf80100 37 0x5 0x0 0x0 0xf8010000 0x00008000>;
38 38
39 nor@0,0 { 39 nor@0,0 {
40 #address-cells = <1>; 40 #address-cells = <1>;
41 #size-cells = <1>; 41 #size-cells = <1>;
42 compatible = "cfi-flas 42 compatible = "cfi-flash";
43 reg = <0x0 0x0 0x02000 43 reg = <0x0 0x0 0x02000000>;
44 bank-width = <1>; 44 bank-width = <1>;
45 device-width = <1>; 45 device-width = <1>;
46 partition@0 { 46 partition@0 {
47 label = "ramdi 47 label = "ramdisk";
48 reg = <0x00000 48 reg = <0x00000000 0x01c00000>;
49 }; 49 };
50 partition@1c00000 { 50 partition@1c00000 {
51 label = "kerne 51 label = "kernel";
52 reg = <0x01c00 52 reg = <0x01c00000 0x002e0000>;
53 }; 53 };
54 partition@1ee0000 { 54 partition@1ee0000 {
55 label = "dtb"; 55 label = "dtb";
56 reg = <0x01ee0 56 reg = <0x01ee0000 0x00020000>;
57 }; 57 };
58 partition@1f00000 { 58 partition@1f00000 {
59 label = "firmw 59 label = "firmware";
60 reg = <0x01f00 60 reg = <0x01f00000 0x00080000>;
61 read-only; 61 read-only;
62 }; 62 };
63 partition@1f80000 { 63 partition@1f80000 {
64 label = "u-boo 64 label = "u-boot";
65 reg = <0x01f80 65 reg = <0x01f80000 0x00080000>;
66 read-only; 66 read-only;
67 }; 67 };
68 }; 68 };
69 69
70 bcsr@1,0 { 70 bcsr@1,0 {
71 #address-cells = <1>; 71 #address-cells = <1>;
72 #size-cells = <1>; 72 #size-cells = <1>;
73 compatible = "fsl,mpc8 73 compatible = "fsl,mpc8569mds-bcsr";
74 reg = <1 0 0x8000>; 74 reg = <1 0 0x8000>;
75 ranges = <0 1 0 0x8000 75 ranges = <0 1 0 0x8000>;
76 76
77 bcsr17: gpio-controlle 77 bcsr17: gpio-controller@11 {
78 #gpio-cells = 78 #gpio-cells = <2>;
79 compatible = " 79 compatible = "fsl,mpc8569mds-bcsr-gpio";
80 reg = <0x11 0x 80 reg = <0x11 0x1>;
81 gpio-controlle 81 gpio-controller;
82 }; 82 };
83 }; 83 };
84 84
85 nand@3,0 { 85 nand@3,0 {
86 compatible = "fsl,mpc8 86 compatible = "fsl,mpc8569-fcm-nand",
87 "fsl,elbc 87 "fsl,elbc-fcm-nand";
88 reg = <3 0 0x8000>; 88 reg = <3 0 0x8000>;
89 }; 89 };
90 90
91 pib@4,0 { 91 pib@4,0 {
92 compatible = "fsl,mpc8 92 compatible = "fsl,mpc8569mds-pib";
93 reg = <4 0 0x8000>; 93 reg = <4 0 0x8000>;
94 }; 94 };
95 95
96 pib@5,0 { 96 pib@5,0 {
97 compatible = "fsl,mpc8 97 compatible = "fsl,mpc8569mds-pib";
98 reg = <5 0 0x8000>; 98 reg = <5 0 0x8000>;
99 }; 99 };
100 }; 100 };
101 101
102 soc: soc@e0000000 { 102 soc: soc@e0000000 {
103 ranges = <0x0 0x0 0xe0000000 0 103 ranges = <0x0 0x0 0xe0000000 0x100000>;
104 104
105 i2c-sleep-nexus { 105 i2c-sleep-nexus {
106 i2c@3000 { 106 i2c@3000 {
107 rtc@68 { 107 rtc@68 {
108 compat 108 compatible = "dallas,ds1374";
109 reg = 109 reg = <0x68>;
110 interr 110 interrupts = <3 1 0 0>;
111 }; 111 };
112 }; 112 };
113 }; 113 };
114 114
115 sdhc@2e000 { 115 sdhc@2e000 {
116 status = "disabled"; 116 status = "disabled";
117 sdhci,1-bit-only; 117 sdhci,1-bit-only;
118 bus-width = <1>; 118 bus-width = <1>;
119 }; 119 };
120 120
121 par_io@e0100 { 121 par_io@e0100 {
122 num-ports = <7>; 122 num-ports = <7>;
123 123
124 qe_pio_e: gpio-control 124 qe_pio_e: gpio-controller@80 {
125 #gpio-cells = 125 #gpio-cells = <2>;
126 compatible = " 126 compatible = "fsl,mpc8569-qe-pario-bank",
127 " 127 "fsl,mpc8323-qe-pario-bank";
128 reg = <0x80 0x 128 reg = <0x80 0x18>;
129 gpio-controlle 129 gpio-controller;
130 }; 130 };
131 131
132 qe_pio_f: gpio-control 132 qe_pio_f: gpio-controller@a0 {
133 #gpio-cells = 133 #gpio-cells = <2>;
134 compatible = " 134 compatible = "fsl,mpc8569-qe-pario-bank",
135 " 135 "fsl,mpc8323-qe-pario-bank";
136 reg = <0xa0 0x 136 reg = <0xa0 0x18>;
137 gpio-controlle 137 gpio-controller;
138 }; 138 };
139 139
140 pio1: ucc_pin@1 { 140 pio1: ucc_pin@1 {
141 pio-map = < 141 pio-map = <
142 /* port pin dir ope 142 /* port pin dir open_drain assignment has_irq */
143 0x2 0 143 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
144 0x2 0 144 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
145 0x2 0 145 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
146 0x0 0 146 0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */
147 0x0 0 147 0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */
148 0x0 0 148 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */
149 0x0 0 149 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
150 0x0 0 150 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */
151 0x0 0 151 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */
152 0x0 0 152 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
153 0x0 0 153 0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
154 0x0 0 154 0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
155 0x0 0 155 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */
156 0x2 0 156 0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */
157 0x2 0 157 0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */
158 }; 158 };
159 159
160 pio2: ucc_pin@2 { 160 pio2: ucc_pin@2 {
161 pio-map = < 161 pio-map = <
162 /* port pin dir ope 162 /* port pin dir open_drain assignment has_irq */
163 0x2 0 163 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
164 0x2 0 164 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
165 0x2 0 165 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
166 0x0 0 166 0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */
167 0x0 0 167 0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */
168 0x0 0 168 0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */
169 0x0 0 169 0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */
170 0x0 0 170 0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */
171 0x0 0 171 0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */
172 0x0 0 172 0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */
173 0x0 0 173 0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */
174 0x0 0 174 0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */
175 0x0 0 175 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */
176 0x2 0 176 0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */
177 0x2 0 177 0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */
178 }; 178 };
179 179
180 pio3: ucc_pin@3 { 180 pio3: ucc_pin@3 {
181 pio-map = < 181 pio-map = <
182 /* port pin dir ope 182 /* port pin dir open_drain assignment has_irq */
183 0x2 0 183 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
184 0x2 0 184 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
185 0x2 0 185 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
186 0x0 0 186 0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */
187 0x0 0 187 0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */
188 0x0 0 188 0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */
189 0x1 0 189 0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */
190 0x1 0 190 0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */
191 0x1 0 191 0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */
192 0x1 0 192 0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */
193 0x1 0 193 0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */
194 0x1 0 194 0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */
195 0x1 0 195 0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */
196 0x2 0 196 0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */
197 0x2 0 197 0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */
198 }; 198 };
199 199
200 pio4: ucc_pin@4 { 200 pio4: ucc_pin@4 {
201 pio-map = < 201 pio-map = <
202 /* port pin dir ope 202 /* port pin dir open_drain assignment has_irq */
203 0x2 0 203 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
204 0x2 0 204 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
205 0x2 0 205 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
206 0x1 0 206 0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */
207 0x1 0 207 0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */
208 0x1 0 208 0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */
209 0x1 0 209 0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */
210 0x1 0 210 0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */
211 0x1 0 211 0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */
212 0x1 0 212 0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */
213 0x1 0 213 0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */
214 0x1 0 214 0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */
215 0x1 0 215 0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */
216 0x2 0 216 0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */
217 0x2 0 217 0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */
218 }; 218 };
219 }; 219 };
220 }; 220 };
221 221
222 qe: qe@e0080000 { 222 qe: qe@e0080000 {
223 ranges = <0x0 0x0 0xe0080000 0 223 ranges = <0x0 0x0 0xe0080000 0x40000>;
224 reg = <0x0 0xe0080000 0x0 0x48 224 reg = <0x0 0xe0080000 0x0 0x480>;
225 225
226 spi@4c0 { 226 spi@4c0 {
227 gpios = <&qe_pio_e 30 227 gpios = <&qe_pio_e 30 0>;
228 mode = "cpu-qe"; 228 mode = "cpu-qe";
229 229
230 serial-flash@0 { 230 serial-flash@0 {
231 compatible = " 231 compatible = "st,m25p40";
232 reg = <0>; 232 reg = <0>;
233 spi-max-freque 233 spi-max-frequency = <25000000>;
234 }; 234 };
235 }; 235 };
236 236
237 spi@500 { 237 spi@500 {
238 mode = "cpu"; 238 mode = "cpu";
239 }; 239 };
240 240
241 usb@6c0 { 241 usb@6c0 {
242 fsl,fullspeed-clock = 242 fsl,fullspeed-clock = "clk5";
243 fsl,lowspeed-clock = " 243 fsl,lowspeed-clock = "brg10";
244 gpios = <&qe_pio_f 3 0 244 gpios = <&qe_pio_f 3 0 /* USBOE */
245 &qe_pio_f 4 0 245 &qe_pio_f 4 0 /* USBTP */
246 &qe_pio_f 5 0 246 &qe_pio_f 5 0 /* USBTN */
247 &qe_pio_f 6 0 247 &qe_pio_f 6 0 /* USBRP */
248 &qe_pio_f 8 0 248 &qe_pio_f 8 0 /* USBRN */
249 &bcsr17 1 0 249 &bcsr17 1 0 /* SPEED */
250 &bcsr17 2 0 250 &bcsr17 2 0>; /* POWER */
251 }; 251 };
252 252
253 enet0: ucc@2000 { 253 enet0: ucc@2000 {
254 device_type = "network 254 device_type = "network";
255 compatible = "ucc_geth 255 compatible = "ucc_geth";
256 local-mac-address = [ 256 local-mac-address = [ 00 00 00 00 00 00 ];
257 rx-clock-name = "none" 257 rx-clock-name = "none";
258 tx-clock-name = "clk12 258 tx-clock-name = "clk12";
259 pio-handle = <&pio1>; 259 pio-handle = <&pio1>;
260 tbi-handle = <&tbi1>; 260 tbi-handle = <&tbi1>;
261 phy-handle = <&qe_phy0 261 phy-handle = <&qe_phy0>;
262 phy-connection-type = 262 phy-connection-type = "rgmii-id";
263 }; 263 };
264 264
265 mdio@2120 { 265 mdio@2120 {
266 #address-cells = <1>; 266 #address-cells = <1>;
267 #size-cells = <0>; 267 #size-cells = <0>;
268 reg = <0x2120 0x18>; 268 reg = <0x2120 0x18>;
269 compatible = "fsl,ucc- 269 compatible = "fsl,ucc-mdio";
270 270
271 qe_phy0: ethernet-phy@ 271 qe_phy0: ethernet-phy@7 {
272 interrupt-pare 272 interrupt-parent = <&mpic>;
273 interrupts = < 273 interrupts = <1 1 0 0>;
274 reg = <0x7>; 274 reg = <0x7>;
275 }; 275 };
276 qe_phy1: ethernet-phy@ 276 qe_phy1: ethernet-phy@1 {
277 interrupt-pare 277 interrupt-parent = <&mpic>;
278 interrupts = < 278 interrupts = <2 1 0 0>;
279 reg = <0x1>; 279 reg = <0x1>;
280 }; 280 };
281 qe_phy2: ethernet-phy@ 281 qe_phy2: ethernet-phy@2 {
282 interrupt-pare 282 interrupt-parent = <&mpic>;
283 interrupts = < 283 interrupts = <3 1 0 0>;
284 reg = <0x2>; 284 reg = <0x2>;
285 }; 285 };
286 qe_phy3: ethernet-phy@ 286 qe_phy3: ethernet-phy@3 {
287 interrupt-pare 287 interrupt-parent = <&mpic>;
288 interrupts = < 288 interrupts = <4 1 0 0>;
289 reg = <0x3>; 289 reg = <0x3>;
290 }; 290 };
291 qe_phy5: ethernet-phy@ 291 qe_phy5: ethernet-phy@4 {
292 reg = <0x04>; 292 reg = <0x04>;
293 }; 293 };
294 qe_phy7: ethernet-phy@ 294 qe_phy7: ethernet-phy@6 {
295 reg = <0x6>; 295 reg = <0x6>;
296 }; 296 };
297 tbi1: tbi-phy@11 { 297 tbi1: tbi-phy@11 {
298 reg = <0x11>; 298 reg = <0x11>;
299 device_type = 299 device_type = "tbi-phy";
300 }; 300 };
301 }; 301 };
302 mdio@3520 { 302 mdio@3520 {
303 #address-cells = <1>; 303 #address-cells = <1>;
304 #size-cells = <0>; 304 #size-cells = <0>;
305 reg = <0x3520 0x18>; 305 reg = <0x3520 0x18>;
306 compatible = "fsl,ucc- 306 compatible = "fsl,ucc-mdio";
307 307
308 tbi6: tbi-phy@15 { 308 tbi6: tbi-phy@15 {
309 reg = <0x15>; 309 reg = <0x15>;
310 device_type = "tbi-phy 310 device_type = "tbi-phy";
311 }; 311 };
312 }; 312 };
313 mdio@3720 { 313 mdio@3720 {
314 #address-cells = <1>; 314 #address-cells = <1>;
315 #size-cells = <0>; 315 #size-cells = <0>;
316 reg = <0x3720 0x38>; 316 reg = <0x3720 0x38>;
317 compatible = "fsl,ucc- 317 compatible = "fsl,ucc-mdio";
318 tbi8: tbi-phy@17 { 318 tbi8: tbi-phy@17 {
319 reg = <0x17>; 319 reg = <0x17>;
320 device_type = 320 device_type = "tbi-phy";
321 }; 321 };
322 }; 322 };
323 323
324 enet2: ucc@2200 { 324 enet2: ucc@2200 {
325 device_type = "network 325 device_type = "network";
326 compatible = "ucc_geth 326 compatible = "ucc_geth";
327 local-mac-address = [ 327 local-mac-address = [ 00 00 00 00 00 00 ];
328 rx-clock-name = "none" 328 rx-clock-name = "none";
329 tx-clock-name = "clk12 329 tx-clock-name = "clk12";
330 pio-handle = <&pio3>; 330 pio-handle = <&pio3>;
331 tbi-handle = <&tbi3>; 331 tbi-handle = <&tbi3>;
332 phy-handle = <&qe_phy2 332 phy-handle = <&qe_phy2>;
333 phy-connection-type = 333 phy-connection-type = "rgmii-id";
334 }; 334 };
335 335
336 mdio@2320 { 336 mdio@2320 {
337 #address-cells = <1>; 337 #address-cells = <1>;
338 #size-cells = <0>; 338 #size-cells = <0>;
339 reg = <0x2320 0x18>; 339 reg = <0x2320 0x18>;
340 compatible = "fsl,ucc- 340 compatible = "fsl,ucc-mdio";
341 tbi3: tbi-phy@11 { 341 tbi3: tbi-phy@11 {
342 reg = <0x11>; 342 reg = <0x11>;
343 device_type = 343 device_type = "tbi-phy";
344 }; 344 };
345 }; 345 };
346 346
347 enet1: ucc@3000 { 347 enet1: ucc@3000 {
348 device_type = "network 348 device_type = "network";
349 compatible = "ucc_geth 349 compatible = "ucc_geth";
350 local-mac-address = [ 350 local-mac-address = [ 00 00 00 00 00 00 ];
351 rx-clock-name = "none" 351 rx-clock-name = "none";
352 tx-clock-name = "clk17 352 tx-clock-name = "clk17";
353 pio-handle = <&pio2>; 353 pio-handle = <&pio2>;
354 tbi-handle = <&tbi2>; 354 tbi-handle = <&tbi2>;
355 phy-handle = <&qe_phy1 355 phy-handle = <&qe_phy1>;
356 phy-connection-type = 356 phy-connection-type = "rgmii-id";
357 }; 357 };
358 358
359 mdio@3120 { 359 mdio@3120 {
360 #address-cells = <1>; 360 #address-cells = <1>;
361 #size-cells = <0>; 361 #size-cells = <0>;
362 reg = <0x3120 0x18>; 362 reg = <0x3120 0x18>;
363 compatible = "fsl,ucc- 363 compatible = "fsl,ucc-mdio";
364 tbi2: tbi-phy@11 { 364 tbi2: tbi-phy@11 {
365 reg = <0x11>; 365 reg = <0x11>;
366 device_type = 366 device_type = "tbi-phy";
367 }; 367 };
368 }; 368 };
369 369
370 enet3: ucc@3200 { 370 enet3: ucc@3200 {
371 device_type = "network 371 device_type = "network";
372 compatible = "ucc_geth 372 compatible = "ucc_geth";
373 local-mac-address = [ 373 local-mac-address = [ 00 00 00 00 00 00 ];
374 rx-clock-name = "none" 374 rx-clock-name = "none";
375 tx-clock-name = "clk17 375 tx-clock-name = "clk17";
376 pio-handle = <&pio4>; 376 pio-handle = <&pio4>;
377 tbi-handle = <&tbi4>; 377 tbi-handle = <&tbi4>;
378 phy-handle = <&qe_phy3 378 phy-handle = <&qe_phy3>;
379 phy-connection-type = 379 phy-connection-type = "rgmii-id";
380 }; 380 };
381 381
382 mdio@3320 { 382 mdio@3320 {
383 #address-cells = <1>; 383 #address-cells = <1>;
384 #size-cells = <0>; 384 #size-cells = <0>;
385 reg = <0x3320 0x18>; 385 reg = <0x3320 0x18>;
386 compatible = "fsl,ucc- 386 compatible = "fsl,ucc-mdio";
387 tbi4: tbi-phy@11 { 387 tbi4: tbi-phy@11 {
388 reg = <0x11>; 388 reg = <0x11>;
389 device_type = 389 device_type = "tbi-phy";
390 }; 390 };
391 }; 391 };
392 392
393 enet5: ucc@3400 { 393 enet5: ucc@3400 {
394 device_type = "network 394 device_type = "network";
395 compatible = "ucc_geth 395 compatible = "ucc_geth";
396 local-mac-address = [ 396 local-mac-address = [ 00 00 00 00 00 00 ];
397 rx-clock-name = "none" 397 rx-clock-name = "none";
398 tx-clock-name = "none" 398 tx-clock-name = "none";
399 tbi-handle = <&tbi6>; 399 tbi-handle = <&tbi6>;
400 phy-handle = <&qe_phy5 400 phy-handle = <&qe_phy5>;
401 phy-connection-type = 401 phy-connection-type = "sgmii";
402 }; 402 };
403 403
404 enet7: ucc@3600 { 404 enet7: ucc@3600 {
405 device_type = "network 405 device_type = "network";
406 compatible = "ucc_geth 406 compatible = "ucc_geth";
407 local-mac-address = [ 407 local-mac-address = [ 00 00 00 00 00 00 ];
408 rx-clock-name = "none" 408 rx-clock-name = "none";
409 tx-clock-name = "none" 409 tx-clock-name = "none";
410 tbi-handle = <&tbi8>; 410 tbi-handle = <&tbi8>;
411 phy-handle = <&qe_phy7 411 phy-handle = <&qe_phy7>;
412 phy-connection-type = 412 phy-connection-type = "sgmii";
413 }; 413 };
414 }; 414 };
415 415
416 /* PCI Express */ 416 /* PCI Express */
417 pci1: pcie@e000a000 { 417 pci1: pcie@e000a000 {
418 reg = <0x0 0xe000a000 0x0 0x10 418 reg = <0x0 0xe000a000 0x0 0x1000>;
419 ranges = <0x2000000 0x0 0xa000 419 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000
420 0x1000000 0x0 0x0000 420 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x00800000>;
421 pcie@0 { 421 pcie@0 {
422 ranges = <0x2000000 0x 422 ranges = <0x2000000 0x0 0xa0000000
423 0x2000000 0x 423 0x2000000 0x0 0xa0000000
424 0x0 0x100000 424 0x0 0x10000000
425 425
426 0x1000000 0x 426 0x1000000 0x0 0x0
427 0x1000000 0x 427 0x1000000 0x0 0x0
428 0x0 0x800000 428 0x0 0x800000>;
429 }; 429 };
430 }; 430 };
431 431
432 rio: rapidio@e00c00000 { 432 rio: rapidio@e00c00000 {
433 reg = <0x0 0xe00c0000 0x0 0x20 433 reg = <0x0 0xe00c0000 0x0 0x20000>;
434 port1 { 434 port1 {
435 ranges = <0x0 0x0 0x0 435 ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
436 }; 436 };
437 port2 { 437 port2 {
438 status = "disabled"; 438 status = "disabled";
439 }; 439 };
440 }; 440 };
441 }; 441 };
442 442
443 /include/ "mpc8569si-post.dtsi" 443 /include/ "mpc8569si-post.dtsi"
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