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Linux/scripts/dtc/include-prefixes/powerpc/fsl/mpc8572ds.dts

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Diff markup

Differences between /scripts/dtc/include-prefixes/powerpc/fsl/mpc8572ds.dts (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/powerpc/fsl/mpc8572ds.dts (Version linux-4.17.19)


  1 // SPDX-License-Identifier: GPL-2.0-or-later   << 
  2 /*                                                  1 /*
  3  * MPC8572 DS Device Tree Source                    2  * MPC8572 DS Device Tree Source
  4  *                                                  3  *
  5  * Copyright 2007-2009 Freescale Semiconductor      4  * Copyright 2007-2009 Freescale Semiconductor Inc.
                                                   >>   5  *
                                                   >>   6  * This program is free software; you can redistribute  it and/or modify it
                                                   >>   7  * under  the terms of  the GNU General  Public License as published by the
                                                   >>   8  * Free Software Foundation;  either version 2 of the  License, or (at your
                                                   >>   9  * option) any later version.
  6  */                                                10  */
  7                                                    11 
  8 /include/ "mpc8572si-pre.dtsi"                     12 /include/ "mpc8572si-pre.dtsi"
  9                                                    13 
 10 / {                                                14 / {
 11         model = "fsl,MPC8572DS";                   15         model = "fsl,MPC8572DS";
 12         compatible = "fsl,MPC8572DS";              16         compatible = "fsl,MPC8572DS";
 13                                                    17 
 14         memory {                                   18         memory {
 15                 device_type = "memory";            19                 device_type = "memory";
 16         };                                         20         };
 17                                                    21 
 18         board_lbc: lbc: localbus@ffe05000 {        22         board_lbc: lbc: localbus@ffe05000 {
 19                 reg = <0 0xffe05000 0 0x1000>;     23                 reg = <0 0xffe05000 0 0x1000>;
 20                                                    24 
 21                 ranges = <0x0 0x0 0x0 0xe80000     25                 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
 22                           0x1 0x0 0x0 0xe00000     26                           0x1 0x0 0x0 0xe0000000 0x08000000
 23                           0x2 0x0 0x0 0xffa000     27                           0x2 0x0 0x0 0xffa00000 0x00040000
 24                           0x3 0x0 0x0 0xffdf00     28                           0x3 0x0 0x0 0xffdf0000 0x00008000
 25                           0x4 0x0 0x0 0xffa400     29                           0x4 0x0 0x0 0xffa40000 0x00040000
 26                           0x5 0x0 0x0 0xffa800     30                           0x5 0x0 0x0 0xffa80000 0x00040000
 27                           0x6 0x0 0x0 0xffac00     31                           0x6 0x0 0x0 0xffac0000 0x00040000>;
 28         };                                         32         };
 29                                                    33 
 30         board_soc: soc: soc8572@ffe00000 {         34         board_soc: soc: soc8572@ffe00000 {
 31                 ranges = <0x0 0 0xffe00000 0x1     35                 ranges = <0x0 0 0xffe00000 0x100000>;
 32         };                                         36         };
 33                                                    37 
 34         board_pci0: pci0: pcie@ffe08000 {          38         board_pci0: pci0: pcie@ffe08000 {
 35                 reg = <0 0xffe08000 0 0x1000>;     39                 reg = <0 0xffe08000 0 0x1000>;
 36                 ranges = <0x2000000 0x0 0x8000     40                 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
 37                           0x1000000 0x0 0x0000     41                           0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>;
 38                 pcie@0 {                           42                 pcie@0 {
 39                         ranges = <0x2000000 0x     43                         ranges = <0x2000000 0x0 0x80000000
 40                                   0x2000000 0x     44                                   0x2000000 0x0 0x80000000
 41                                   0x0 0x200000     45                                   0x0 0x20000000
 42                                                    46 
 43                                   0x1000000 0x     47                                   0x1000000 0x0 0x0
 44                                   0x1000000 0x     48                                   0x1000000 0x0 0x0
 45                                   0x0 0x10000>     49                                   0x0 0x10000>;
 46                 };                                 50                 };
 47         };                                         51         };
 48                                                    52 
 49         pci1: pcie@ffe09000 {                      53         pci1: pcie@ffe09000 {
 50                 reg = <0 0xffe09000 0 0x1000>;     54                 reg = <0 0xffe09000 0 0x1000>;
 51                 ranges = <0x2000000 0x0 0xa000     55                 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
 52                           0x1000000 0x0 0x0000     56                           0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>;
 53                 pcie@0 {                           57                 pcie@0 {
 54                         ranges = <0x2000000 0x     58                         ranges = <0x2000000 0x0 0xa0000000
 55                                   0x2000000 0x     59                                   0x2000000 0x0 0xa0000000
 56                                   0x0 0x200000     60                                   0x0 0x20000000
 57                                                    61 
 58                                   0x1000000 0x     62                                   0x1000000 0x0 0x0
 59                                   0x1000000 0x     63                                   0x1000000 0x0 0x0
 60                                   0x0 0x10000>     64                                   0x0 0x10000>;
 61                 };                                 65                 };
 62         };                                         66         };
 63                                                    67 
 64         pci2: pcie@ffe0a000 {                      68         pci2: pcie@ffe0a000 {
 65                 reg = <0 0xffe0a000 0 0x1000>;     69                 reg = <0 0xffe0a000 0 0x1000>;
 66                 ranges = <0x2000000 0x0 0xc000     70                 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
 67                           0x1000000 0x0 0x0000     71                           0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>;
 68                 pcie@0 {                           72                 pcie@0 {
 69                         ranges = <0x2000000 0x     73                         ranges = <0x2000000 0x0 0xc0000000
 70                                   0x2000000 0x     74                                   0x2000000 0x0 0xc0000000
 71                                   0x0 0x200000     75                                   0x0 0x20000000
 72                                                    76 
 73                                   0x1000000 0x     77                                   0x1000000 0x0 0x0
 74                                   0x1000000 0x     78                                   0x1000000 0x0 0x0
 75                                   0x0 0x10000>     79                                   0x0 0x10000>;
 76                 };                                 80                 };
 77         };                                         81         };
 78 };                                                 82 };
 79                                                    83 
 80 /*                                                 84 /*
 81  * mpc8572ds.dtsi must be last to ensure board     85  * mpc8572ds.dtsi must be last to ensure board_pci0 overrides pci0 settings
 82  * for interrupt-map & interrupt-map-mask          86  * for interrupt-map & interrupt-map-mask
 83  */                                                87  */
 84                                                    88 
 85 /include/ "mpc8572si-post.dtsi"                    89 /include/ "mpc8572si-post.dtsi"
 86 /include/ "mpc8572ds.dtsi"                         90 /include/ "mpc8572ds.dtsi"
                                                      

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