1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * MPC8641 Silicon/SoC Device Tree Source (pre 3 * MPC8641 Silicon/SoC Device Tree Source (pre include)
4 * 4 *
5 * Copyright 2016 Elettra-Sincrotrone Trieste 5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
6 */ 6 */
7 7
8 /dts-v1/; 8 /dts-v1/;
9 9
10 / { 10 / {
11 #address-cells = <1>; 11 #address-cells = <1>;
12 #size-cells = <1>; 12 #size-cells = <1>;
13 interrupt-parent = <&mpic>; 13 interrupt-parent = <&mpic>;
14 14
15 aliases { 15 aliases {
16 ethernet0 = &enet0; 16 ethernet0 = &enet0;
17 ethernet1 = &enet1; 17 ethernet1 = &enet1;
18 ethernet2 = &enet2; 18 ethernet2 = &enet2;
19 ethernet3 = &enet3; 19 ethernet3 = &enet3;
20 serial0 = &serial0; 20 serial0 = &serial0;
21 serial1 = &serial1; 21 serial1 = &serial1;
22 pci0 = &pci0; 22 pci0 = &pci0;
23 pci1 = &pci1; 23 pci1 = &pci1;
24 }; 24 };
25 25
26 cpus { 26 cpus {
27 #address-cells = <1>; 27 #address-cells = <1>;
28 #size-cells = <0>; 28 #size-cells = <0>;
29 29
30 PowerPC,8641@0 { 30 PowerPC,8641@0 {
31 device_type = "cpu"; 31 device_type = "cpu";
32 reg = <0>; 32 reg = <0>;
33 d-cache-line-size = <3 33 d-cache-line-size = <32>;
34 i-cache-line-size = <3 34 i-cache-line-size = <32>;
35 d-cache-size = <32768> 35 d-cache-size = <32768>;
36 i-cache-size = <32768> 36 i-cache-size = <32768>;
37 timebase-frequency = < 37 timebase-frequency = <0>;
38 bus-frequency = <0>; 38 bus-frequency = <0>;
39 clock-frequency = <0>; 39 clock-frequency = <0>;
40 }; 40 };
41 41
42 PowerPC,8641@1 { 42 PowerPC,8641@1 {
43 device_type = "cpu"; 43 device_type = "cpu";
44 reg = <1>; 44 reg = <1>;
45 d-cache-line-size = <3 45 d-cache-line-size = <32>;
46 i-cache-line-size = <3 46 i-cache-line-size = <32>;
47 d-cache-size = <32768> 47 d-cache-size = <32768>;
48 i-cache-size = <32768> 48 i-cache-size = <32768>;
49 timebase-frequency = < 49 timebase-frequency = <0>;
50 bus-frequency = <0>; 50 bus-frequency = <0>;
51 clock-frequency = <0>; 51 clock-frequency = <0>;
52 }; 52 };
53 }; 53 };
54 }; 54 };
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