1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Device tree source for the Emerson/Artesyn
4 *
5 * Copyright 2014 Elettra-Sincrotrone Trieste
6 *
7 * Based on: P2020 DS Device Tree Source
8 * Copyright 2009 Freescale Semiconductor Inc.
9 */
10
11 /include/ "p2020si-pre.dtsi"
12
13 / {
14 model = "MVME2500";
15 compatible = "artesyn,MVME2500";
16
17 aliases {
18 serial2 = &serial2;
19 serial3 = &serial3;
20 serial4 = &serial4;
21 serial5 = &serial5;
22 };
23
24 memory {
25 device_type = "memory";
26 };
27
28 soc: soc@ffe00000 {
29 ranges = <0x0 0 0xffe00000 0x1
30
31 i2c@3000 {
32 hwmon@4c {
33 compatible = "
34 reg = <0x4c>;
35 };
36
37 rtc@68 {
38 compatible = "
39 reg = <0x68>;
40 interrupts = <
41 };
42
43 eeprom@54 {
44 compatible = "
45 reg = <0x54>;
46 };
47
48 eeprom@52 {
49 compatible = "
50 reg = <0x52>;
51 };
52
53 eeprom@53 {
54 compatible = "
55 reg = <0x53>;
56 };
57
58 eeprom@50 {
59 compatible = "
60 reg = <0x50>;
61 };
62
63 };
64
65 spi0: spi@7000 {
66 fsl,espi-num-chipselec
67
68 flash@0 {
69 compatible = "
70 reg = <0>;
71 spi-max-freque
72 };
73 flash@1 {
74 compatible = "
75 reg = <1>;
76 spi-max-freque
77 };
78 };
79
80 usb@22000 {
81 dr_mode = "host";
82 phy_type = "ulpi";
83 };
84
85 enet0: ethernet@24000 {
86 tbi-handle = <&tbi0>;
87 phy-handle = <&phy1>;
88 phy-connection-type =
89 };
90
91 mdio@24520 {
92 phy1: ethernet-phy@1 {
93 compatible = "
94 interrupts = <
95 reg = <0x1>;
96 };
97
98 phy2: ethernet-phy@2 {
99 compatible = "
100 interrupts = <
101 reg = <0x2>;
102 };
103
104 phy3: ethernet-phy@3 {
105 compatible = "
106 interrupts = <
107 reg = <0x3>;
108 };
109
110 phy7: ethernet-phy@7 {
111 compatible = "
112 interrupts = <
113 reg = <0x7>;
114 };
115
116 tbi0: tbi-phy@11 {
117 reg = <0x11>;
118 device_type =
119 };
120 };
121
122 enet1: ethernet@25000 {
123 tbi-handle = <&tbi1>;
124 phy-handle = <&phy7>;
125 phy-connection-type =
126 };
127
128 mdio@25520 {
129 tbi1: tbi-phy@11 {
130 reg = <0x11>;
131 device_type =
132 };
133 };
134
135 enet2: ethernet@26000 {
136 tbi-handle = <&tbi2>;
137 phy-handle = <&phy3>;
138 phy-connection-type =
139 };
140
141 mdio@26520 {
142 tbi2: tbi-phy@11 {
143 reg = <0x11>;
144 device_type =
145 };
146 };
147 };
148
149 lbc: localbus@ffe05000 {
150 reg = <0 0xffe05000 0 0x1000>;
151
152 ranges = <0x0 0x0 0x0 0xfff000
153 0x1 0x0 0x0 0xffc400
154 0x2 0x0 0x0 0xffc500
155 0x3 0x0 0x0 0xffc600
156 0x4 0x0 0x0 0xffc700
157 0x6 0x0 0x0 0xffc800
158 0x5 0x0 0x0 0xffdf00
159
160 serial2: serial@1,0 {
161 device_type = "serial"
162 compatible = "ns16550"
163 reg = <0x1 0x0 0x100>;
164 clock-frequency = <184
165 interrupts = <11 2 0 0
166 };
167
168 serial3: serial@2,0 {
169 device_type = "serial"
170 compatible = "ns16550"
171 reg = <0x2 0x0 0x100>;
172 clock-frequency = <184
173 interrupts = <1 2 0 0>
174 };
175
176 serial4: serial@3,0 {
177 device_type = "serial"
178 compatible = "ns16550"
179 reg = <0x3 0x0 0x100>;
180 clock-frequency = <184
181 interrupts = <2 2 0 0>
182 };
183
184 serial5: serial@4,0 {
185 device_type = "serial"
186 compatible = "ns16550"
187 reg = <0x4 0x0 0x100>;
188 clock-frequency = <184
189 interrupts = <3 2 0 0>
190 };
191
192 mram@0,0 {
193 compatible = "everspin
194 reg = <0x0 0x0 0x80000
195 bank-width = <2>;
196 };
197
198 board-control@5,0 {
199 compatible = "artesyn,
200 reg = <0x5 0x0 0x01000
201 };
202
203 cpld@6,0 {
204 compatible = "artesyn,
205 reg = <0x6 0x0 0x10000
206 interrupts = <9 1 0 0>
207 };
208 };
209
210 pci0: pcie@ffe08000 {
211 reg = <0 0xffe08000 0 0x1000>;
212 ranges = <0x2000000 0x0 0x8000
213 0x1000000 0x0 0x0000
214 pcie@0 {
215 ranges = <0x2000000 0x
216 0x2000000 0x
217 0x0 0x200000
218
219 0x1000000 0x
220 0x1000000 0x
221 0x0 0x10000>
222 };
223 };
224
225 pci1: pcie@ffe09000 {
226 reg = <0 0xffe09000 0 0x1000>;
227 ranges = <0x2000000 0x0 0xa000
228 0x1000000 0x0 0x0000
229 pcie@0 {
230 ranges = <0x2000000 0x
231 0x2000000 0x
232 0x0 0x200000
233
234 0x1000000 0x
235 0x1000000 0x
236 0x0 0x10000>
237 };
238
239 };
240
241 pci2: pcie@ffe0a000 {
242 reg = <0 0xffe0a000 0 0x1000>;
243 ranges = <0x2000000 0x0 0xc000
244 0x1000000 0x0 0x0000
245 pcie@0 {
246 ranges = <0x2000000 0x
247 0x2000000 0x
248 0x0 0x200000
249
250 0x1000000 0x
251 0x1000000 0x
252 0x0 0x10000>
253 };
254 };
255 };
256
257 /include/ "p2020si-post.dtsi"
258
259 / {
260 soc@ffe00000 {
261 serial@4600 {
262 status = "disabled";
263 };
264
265 i2c@3100 {
266 status = "disabled";
267 };
268
269 sdhc@2e000 {
270 compatible = "fsl,p202
271 non-removable;
272 };
273
274 };
275
276 };
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