1 /*
2 * P1020 RDB-PD Device Tree Source (32-bit add
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT
33 */
34
35 /include/ "p1020si-pre.dtsi"
36 / {
37 model = "fsl,P1020RDB-PD";
38 compatible = "fsl,P1020RDB-PD";
39
40 memory {
41 device_type = "memory";
42 };
43
44 lbc: localbus@ffe05000 {
45 reg = <0x0 0xffe05000 0x0 0x10
46
47 /* NOR, NAND flash, L2 switch
48 ranges = <0x0 0x0 0x0 0xec0000
49 0x1 0x0 0x0 0xff8000
50 0x2 0x0 0x0 0xffa000
51 0x3 0x0 0x0 0xffb000
52
53 nor@0,0 {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 compatible = "cfi-flas
57 reg = <0x0 0x0 0x40000
58 bank-width = <2>;
59 device-width = <1>;
60
61 partition@0 {
62 /* 128KB for D
63 reg = <0x0 0x0
64 label = "NOR D
65 };
66
67 partition@20000 {
68 /* 3.875 MB fo
69 reg = <0x00020
70 label = "NOR L
71 };
72
73 partition@400000 {
74 /* 58MB for Ro
75 reg = <0x00400
76 label = "NOR R
77 };
78
79 partition@3e00000 {
80 /* This locati
81 /* 1M for Vite
82 reg = <0x3e000
83 label = "NOR V
84 read-only;
85 };
86
87 partition@3f00000 {
88 /* This locati
89 /* 512KB for u
90 /* 512KB for u
91 reg = <0x03f00
92 label = "NOR U
93 read-only;
94 };
95 };
96
97 nand@1,0 {
98 #address-cells = <1>;
99 #size-cells = <1>;
100 compatible = "fsl,p102
101 "fsl,elbc
102 reg = <0x1 0x0 0x40000
103
104 partition@0 {
105 /* This locati
106 /* 1MB for u-b
107 reg = <0x0 0x0
108 label = "NAND
109 read-only;
110 };
111
112 partition@100000 {
113 /* 1MB for DTB
114 reg = <0x00100
115 label = "NAND
116 };
117
118 partition@200000 {
119 /* 4MB for Lin
120 reg = <0x00200
121 label = "NAND
122 };
123
124 partition@600000 {
125 /* 122MB for F
126 reg = <0x00600
127 label = "NAND
128 };
129 };
130
131 cpld@2,0 {
132 compatible = "fsl,p102
133 reg = <0x2 0x0 0x20000
134 };
135
136 L2switch@3,0 {
137 #address-cells = <1>;
138 #size-cells = <1>;
139 compatible = "vitesse-
140 reg = <0x3 0x0 0x20000
141 };
142 };
143
144 soc: soc@ffe00000 {
145 ranges = <0x0 0x0 0xffe00000 0
146
147 i2c@3000 {
148 rtc@68 {
149 compatible = "
150 reg = <0x68>;
151 };
152 };
153
154 spi@7000 {
155 flash@0 {
156 #address-cells
157 #size-cells =
158 compatible = "
159 reg = <0>;
160 /* input clock
161 spi-max-freque
162
163 partition@0 {
164 /* 512
165 reg =
166 label
167 read-o
168 };
169
170 partition@8000
171 /* 512
172 reg =
173 label
174 };
175
176 partition@1000
177 /* 4MB
178 reg =
179 label
180 };
181
182 partition@5000
183 /* 11M
184 reg =
185 label
186 };
187 };
188
189 slic@0 {
190 compatible = "
191 reg = <1>;
192 spi-max-freque
193 };
194
195 slic@1 {
196 compatible = "
197 reg = <2>;
198 spi-max-freque
199 };
200 };
201
202 mdio@24000 {
203 phy0: ethernet-phy@0 {
204 interrupts = <
205 reg = <0x0>;
206 };
207
208 phy1: ethernet-phy@1 {
209 interrupts = <
210 reg = <0x1>;
211 };
212 };
213
214 mdio@25000 {
215 tbi1: tbi-phy@11 {
216 reg = <0x11>;
217 device_type =
218 };
219 };
220
221 mdio@26000 {
222 tbi2: tbi-phy@11 {
223 reg = <0x11>;
224 device_type =
225 };
226 };
227
228 ptp_clock@b0e00 {
229 compatible = "fsl,etse
230 reg = <0xb0e00 0xb0>;
231 interrupts = <68 2 0 0
232 fsl,tclk-period = <10>
233 fsl,tmr-prsc = <2>;
234 fsl,tmr-add = <0x8
235 fsl,tmr-fiper1 = <999
236 fsl,tmr-fiper2 = <999
237 fsl,max-adj = <199
238 };
239
240 enet0: ethernet@b0000 {
241 fixed-link = <1 1 1000
242 phy-connection-type =
243 };
244
245 enet1: ethernet@b1000 {
246 phy-handle = <&phy0>;
247 tbi-handle = <&tbi1>;
248 phy-connection-type =
249 };
250
251 enet2: ethernet@b2000 {
252 phy-handle = <&phy1>;
253 phy-connection-type =
254 };
255
256 usb@22000 {
257 phy_type = "ulpi";
258 };
259 };
260
261 pci0: pcie@ffe09000 {
262 reg = <0x0 0xffe09000 0x0 0x10
263 ranges = <0x2000000 0x0 0xa000
264 0x1000000 0x0 0x0000
265 pcie@0 {
266 ranges = <0x2000000 0x
267 0x2000000 0x
268 0x0 0x200000
269
270 0x1000000 0x
271 0x1000000 0x
272 0x0 0x100000
273 };
274 };
275
276 pci1: pcie@ffe0a000 {
277 reg = <0x0 0xffe0a000 0x0 0x10
278 ranges = <0x2000000 0x0 0x8000
279 0x1000000 0x0 0x0000
280 pcie@0 {
281 ranges = <0x2000000 0x
282 0x2000000 0x
283 0x0 0x200000
284
285 0x1000000 0x
286 0x1000000 0x
287 0x0 0x100000
288 };
289 };
290 };
291
292 /include/ "p1020si-post.dtsi"
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