1 /* 1 /*
2 * P1020 RDB-PD Device Tree Source (32-bit add 2 * P1020 RDB-PD Device Tree Source (32-bit address map)
3 * 3 *
4 * Copyright 2013 Freescale Semiconductor Inc. 4 * Copyright 2013 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that t 7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must r 8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and t 9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must r 10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and t 11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials 12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semicon 13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used 14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without sp 15 * derived from this software without specific prior written permission.
16 * 16 *
17 * 17 *
18 * ALTERNATIVELY, this software may be distrib 18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as publi 19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that Licens 20 * Foundation, either version 2 of that License or (at your option) any
21 * later version. 21 * later version.
22 * 22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35 /include/ "p1020si-pre.dtsi" 35 /include/ "p1020si-pre.dtsi"
36 / { 36 / {
37 model = "fsl,P1020RDB-PD"; 37 model = "fsl,P1020RDB-PD";
38 compatible = "fsl,P1020RDB-PD"; 38 compatible = "fsl,P1020RDB-PD";
39 39
40 memory { 40 memory {
41 device_type = "memory"; 41 device_type = "memory";
42 }; 42 };
43 43
44 lbc: localbus@ffe05000 { 44 lbc: localbus@ffe05000 {
45 reg = <0x0 0xffe05000 0x0 0x10 45 reg = <0x0 0xffe05000 0x0 0x1000>;
46 46
47 /* NOR, NAND flash, L2 switch 47 /* NOR, NAND flash, L2 switch and CPLD */
48 ranges = <0x0 0x0 0x0 0xec0000 48 ranges = <0x0 0x0 0x0 0xec000000 0x04000000
49 0x1 0x0 0x0 0xff8000 49 0x1 0x0 0x0 0xff800000 0x00040000
50 0x2 0x0 0x0 0xffa000 50 0x2 0x0 0x0 0xffa00000 0x00020000
51 0x3 0x0 0x0 0xffb000 51 0x3 0x0 0x0 0xffb00000 0x00020000>;
52 52
53 nor@0,0 { 53 nor@0,0 {
54 #address-cells = <1>; 54 #address-cells = <1>;
55 #size-cells = <1>; 55 #size-cells = <1>;
56 compatible = "cfi-flas 56 compatible = "cfi-flash";
57 reg = <0x0 0x0 0x40000 57 reg = <0x0 0x0 0x4000000>;
58 bank-width = <2>; 58 bank-width = <2>;
59 device-width = <1>; 59 device-width = <1>;
60 60
61 partition@0 { 61 partition@0 {
62 /* 128KB for D 62 /* 128KB for DTB Image */
63 reg = <0x0 0x0 63 reg = <0x0 0x00020000>;
64 label = "NOR D 64 label = "NOR DTB Image";
65 }; 65 };
66 66
67 partition@20000 { 67 partition@20000 {
68 /* 3.875 MB fo 68 /* 3.875 MB for Linux Kernel Image */
69 reg = <0x00020 69 reg = <0x00020000 0x003e0000>;
70 label = "NOR L 70 label = "NOR Linux Kernel Image";
71 }; 71 };
72 72
73 partition@400000 { 73 partition@400000 {
74 /* 58MB for Ro 74 /* 58MB for Root file System */
75 reg = <0x00400 75 reg = <0x00400000 0x03a00000>;
76 label = "NOR R 76 label = "NOR Root File System";
77 }; 77 };
78 78
79 partition@3e00000 { 79 partition@3e00000 {
80 /* This locati 80 /* This location must not be altered */
81 /* 1M for Vite 81 /* 1M for Vitesse 7385 Switch firmware */
82 reg = <0x3e000 82 reg = <0x3e00000 0x00100000>;
83 label = "NOR V 83 label = "NOR Vitesse-7385 Firmware";
84 read-only; 84 read-only;
85 }; 85 };
86 86
87 partition@3f00000 { 87 partition@3f00000 {
88 /* This locati 88 /* This location must not be altered */
89 /* 512KB for u 89 /* 512KB for u-boot Bootloader Image */
90 /* 512KB for u 90 /* 512KB for u-boot Environment Variables */
91 reg = <0x03f00 91 reg = <0x03f00000 0x00100000>;
92 label = "NOR U 92 label = "NOR U-Boot Image";
93 read-only; 93 read-only;
94 }; 94 };
95 }; 95 };
96 96
97 nand@1,0 { 97 nand@1,0 {
98 #address-cells = <1>; 98 #address-cells = <1>;
99 #size-cells = <1>; 99 #size-cells = <1>;
100 compatible = "fsl,p102 100 compatible = "fsl,p1020-fcm-nand",
101 "fsl,elbc 101 "fsl,elbc-fcm-nand";
102 reg = <0x1 0x0 0x40000 102 reg = <0x1 0x0 0x40000>;
103 103
104 partition@0 { 104 partition@0 {
105 /* This locati 105 /* This location must not be altered */
106 /* 1MB for u-b 106 /* 1MB for u-boot Bootloader Image */
107 reg = <0x0 0x0 107 reg = <0x0 0x00100000>;
108 label = "NAND 108 label = "NAND U-Boot Image";
109 read-only; 109 read-only;
110 }; 110 };
111 111
112 partition@100000 { 112 partition@100000 {
113 /* 1MB for DTB 113 /* 1MB for DTB Image */
114 reg = <0x00100 114 reg = <0x00100000 0x00100000>;
115 label = "NAND 115 label = "NAND DTB Image";
116 }; 116 };
117 117
118 partition@200000 { 118 partition@200000 {
119 /* 4MB for Lin 119 /* 4MB for Linux Kernel Image */
120 reg = <0x00200 120 reg = <0x00200000 0x00400000>;
121 label = "NAND 121 label = "NAND Linux Kernel Image";
122 }; 122 };
123 123
124 partition@600000 { 124 partition@600000 {
125 /* 122MB for F 125 /* 122MB for File System Image */
126 reg = <0x00600 126 reg = <0x00600000 0x07a00000>;
127 label = "NAND 127 label = "NAND File System Image";
128 }; 128 };
129 }; 129 };
130 130
131 cpld@2,0 { 131 cpld@2,0 {
132 compatible = "fsl,p102 132 compatible = "fsl,p1020rdb-pd-cpld";
133 reg = <0x2 0x0 0x20000 133 reg = <0x2 0x0 0x20000>;
134 }; 134 };
135 135
136 L2switch@3,0 { 136 L2switch@3,0 {
137 #address-cells = <1>; 137 #address-cells = <1>;
138 #size-cells = <1>; 138 #size-cells = <1>;
139 compatible = "vitesse- 139 compatible = "vitesse-7385";
140 reg = <0x3 0x0 0x20000 140 reg = <0x3 0x0 0x20000>;
141 }; 141 };
142 }; 142 };
143 143
144 soc: soc@ffe00000 { 144 soc: soc@ffe00000 {
145 ranges = <0x0 0x0 0xffe00000 0 145 ranges = <0x0 0x0 0xffe00000 0x100000>;
146 146
147 i2c@3000 { 147 i2c@3000 {
148 rtc@68 { 148 rtc@68 {
149 compatible = " 149 compatible = "dallas,ds1339";
150 reg = <0x68>; 150 reg = <0x68>;
151 }; 151 };
152 }; 152 };
153 153
154 spi@7000 { 154 spi@7000 {
155 flash@0 { 155 flash@0 {
156 #address-cells 156 #address-cells = <1>;
157 #size-cells = 157 #size-cells = <1>;
158 compatible = " 158 compatible = "spansion,s25sl12801", "jedec,spi-nor";
159 reg = <0>; 159 reg = <0>;
160 /* input clock 160 /* input clock */
161 spi-max-freque 161 spi-max-frequency = <40000000>;
162 162
163 partition@0 { 163 partition@0 {
164 /* 512 164 /* 512KB for u-boot Bootloader Image */
165 reg = 165 reg = <0x0 0x00080000>;
166 label 166 label = "SPI U-Boot Image";
167 read-o 167 read-only;
168 }; 168 };
169 169
170 partition@8000 170 partition@80000 {
171 /* 512 171 /* 512KB for DTB Image*/
172 reg = 172 reg = <0x00080000 0x00080000>;
173 label 173 label = "SPI DTB Image";
174 }; 174 };
175 175
176 partition@1000 176 partition@100000 {
177 /* 4MB 177 /* 4MB for Linux Kernel Image */
178 reg = 178 reg = <0x00100000 0x00400000>;
179 label 179 label = "SPI Linux Kernel Image";
180 }; 180 };
181 181
182 partition@5000 182 partition@500000 {
183 /* 11M 183 /* 11MB for FS System Image */
184 reg = 184 reg = <0x00500000 0x00b00000>;
185 label 185 label = "SPI File System Image";
186 }; 186 };
187 }; 187 };
188 188
189 slic@0 { 189 slic@0 {
190 compatible = " 190 compatible = "zarlink,le88266";
191 reg = <1>; 191 reg = <1>;
192 spi-max-freque 192 spi-max-frequency = <8000000>;
193 }; 193 };
194 194
195 slic@1 { 195 slic@1 {
196 compatible = " 196 compatible = "zarlink,le88266";
197 reg = <2>; 197 reg = <2>;
198 spi-max-freque 198 spi-max-frequency = <8000000>;
199 }; 199 };
200 }; 200 };
201 201
202 mdio@24000 { 202 mdio@24000 {
203 phy0: ethernet-phy@0 { 203 phy0: ethernet-phy@0 {
204 interrupts = < 204 interrupts = <3 1 0 0>;
205 reg = <0x0>; 205 reg = <0x0>;
206 }; 206 };
207 207
208 phy1: ethernet-phy@1 { 208 phy1: ethernet-phy@1 {
209 interrupts = < 209 interrupts = <2 1 0 0>;
210 reg = <0x1>; 210 reg = <0x1>;
211 }; 211 };
212 }; 212 };
213 213
214 mdio@25000 { 214 mdio@25000 {
215 tbi1: tbi-phy@11 { 215 tbi1: tbi-phy@11 {
216 reg = <0x11>; 216 reg = <0x11>;
217 device_type = 217 device_type = "tbi-phy";
218 }; 218 };
219 }; 219 };
220 220
221 mdio@26000 { 221 mdio@26000 {
222 tbi2: tbi-phy@11 { 222 tbi2: tbi-phy@11 {
223 reg = <0x11>; 223 reg = <0x11>;
224 device_type = 224 device_type = "tbi-phy";
225 }; 225 };
226 }; 226 };
227 227
228 ptp_clock@b0e00 { 228 ptp_clock@b0e00 {
229 compatible = "fsl,etse 229 compatible = "fsl,etsec-ptp";
230 reg = <0xb0e00 0xb0>; 230 reg = <0xb0e00 0xb0>;
231 interrupts = <68 2 0 0 231 interrupts = <68 2 0 0 69 2 0 0>;
232 fsl,tclk-period = <10> 232 fsl,tclk-period = <10>;
233 fsl,tmr-prsc = <2>; 233 fsl,tmr-prsc = <2>;
234 fsl,tmr-add = <0x8 234 fsl,tmr-add = <0x80000016>;
235 fsl,tmr-fiper1 = <999 235 fsl,tmr-fiper1 = <999999990>;
236 fsl,tmr-fiper2 = <999 236 fsl,tmr-fiper2 = <99990>;
237 fsl,max-adj = <199 237 fsl,max-adj = <199999999>;
238 }; 238 };
239 239
240 enet0: ethernet@b0000 { 240 enet0: ethernet@b0000 {
241 fixed-link = <1 1 1000 241 fixed-link = <1 1 1000 0 0>;
242 phy-connection-type = 242 phy-connection-type = "rgmii-id";
243 }; 243 };
244 244
245 enet1: ethernet@b1000 { 245 enet1: ethernet@b1000 {
246 phy-handle = <&phy0>; 246 phy-handle = <&phy0>;
247 tbi-handle = <&tbi1>; 247 tbi-handle = <&tbi1>;
248 phy-connection-type = 248 phy-connection-type = "sgmii";
249 }; 249 };
250 250
251 enet2: ethernet@b2000 { 251 enet2: ethernet@b2000 {
252 phy-handle = <&phy1>; 252 phy-handle = <&phy1>;
253 phy-connection-type = 253 phy-connection-type = "rgmii-id";
254 }; 254 };
255 255
256 usb@22000 { 256 usb@22000 {
257 phy_type = "ulpi"; 257 phy_type = "ulpi";
258 }; 258 };
259 }; 259 };
260 260
261 pci0: pcie@ffe09000 { 261 pci0: pcie@ffe09000 {
262 reg = <0x0 0xffe09000 0x0 0x10 262 reg = <0x0 0xffe09000 0x0 0x1000>;
263 ranges = <0x2000000 0x0 0xa000 263 ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000
264 0x1000000 0x0 0x0000 264 0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
265 pcie@0 { 265 pcie@0 {
266 ranges = <0x2000000 0x 266 ranges = <0x2000000 0x0 0xa0000000
267 0x2000000 0x 267 0x2000000 0x0 0xa0000000
268 0x0 0x200000 268 0x0 0x20000000
269 269
270 0x1000000 0x 270 0x1000000 0x0 0x0
271 0x1000000 0x 271 0x1000000 0x0 0x0
272 0x0 0x100000 272 0x0 0x100000>;
273 }; 273 };
274 }; 274 };
275 275
276 pci1: pcie@ffe0a000 { 276 pci1: pcie@ffe0a000 {
277 reg = <0x0 0xffe0a000 0x0 0x10 277 reg = <0x0 0xffe0a000 0x0 0x1000>;
278 ranges = <0x2000000 0x0 0x8000 278 ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
279 0x1000000 0x0 0x0000 279 0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>;
280 pcie@0 { 280 pcie@0 {
281 ranges = <0x2000000 0x 281 ranges = <0x2000000 0x0 0x80000000
282 0x2000000 0x 282 0x2000000 0x0 0x80000000
283 0x0 0x200000 283 0x0 0x20000000
284 284
285 0x1000000 0x 285 0x1000000 0x0 0x0
286 0x1000000 0x 286 0x1000000 0x0 0x0
287 0x0 0x100000 287 0x0 0x100000>;
288 }; 288 };
289 }; 289 };
290 }; 290 };
291 291
292 /include/ "p1020si-post.dtsi" 292 /include/ "p1020si-post.dtsi"
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.