1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * P1020 RDB Device Tree Source (36-bit addres 3 * P1020 RDB Device Tree Source (36-bit address map)
4 * 4 *
5 * Copyright 2009-2011 Freescale Semiconductor 5 * Copyright 2009-2011 Freescale Semiconductor Inc.
6 */ 6 */
7 7
8 /include/ "p1020si-pre.dtsi" 8 /include/ "p1020si-pre.dtsi"
9 / { 9 / {
10 model = "fsl,P1020RDB"; 10 model = "fsl,P1020RDB";
11 compatible = "fsl,P1020RDB"; 11 compatible = "fsl,P1020RDB";
12 12
13 memory { 13 memory {
14 device_type = "memory"; 14 device_type = "memory";
15 }; 15 };
16 16
17 board_lbc: lbc: localbus@fffe05000 { 17 board_lbc: lbc: localbus@fffe05000 {
18 reg = <0xf 0xffe05000 0 0x1000 18 reg = <0xf 0xffe05000 0 0x1000>;
19 19
20 /* NOR, NAND Flashes and Vites 20 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
21 ranges = <0x0 0x0 0xf 0xef0000 21 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
22 0x1 0x0 0xf 0xffa000 22 0x1 0x0 0xf 0xffa00000 0x00040000
23 0x2 0x0 0xf 0xffb000 23 0x2 0x0 0xf 0xffb00000 0x00020000>;
24 }; 24 };
25 25
26 board_soc: soc: soc@fffe00000 { 26 board_soc: soc: soc@fffe00000 {
27 ranges = <0x0 0xf 0xffe00000 0 27 ranges = <0x0 0xf 0xffe00000 0x100000>;
28 }; 28 };
29 29
30 pci0: pcie@fffe09000 { 30 pci0: pcie@fffe09000 {
31 reg = <0xf 0xffe09000 0 0x1000 31 reg = <0xf 0xffe09000 0 0x1000>;
32 ranges = <0x2000000 0x0 0xc000 32 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
33 0x1000000 0x0 0x0000 33 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
34 pcie@0 { 34 pcie@0 {
35 ranges = <0x2000000 0x 35 ranges = <0x2000000 0x0 0xc0000000
36 0x2000000 0x 36 0x2000000 0x0 0xc0000000
37 0x0 0x200000 37 0x0 0x20000000
38 38
39 0x1000000 0x 39 0x1000000 0x0 0x0
40 0x1000000 0x 40 0x1000000 0x0 0x0
41 0x0 0x100000 41 0x0 0x100000>;
42 }; 42 };
43 }; 43 };
44 44
45 pci1: pcie@fffe0a000 { 45 pci1: pcie@fffe0a000 {
46 reg = <0xf 0xffe0a000 0 0x1000 46 reg = <0xf 0xffe0a000 0 0x1000>;
47 ranges = <0x2000000 0x0 0x8000 47 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
48 0x1000000 0x0 0x0000 48 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
49 pcie@0 { 49 pcie@0 {
50 ranges = <0x2000000 0x 50 ranges = <0x2000000 0x0 0x80000000
51 0x2000000 0x 51 0x2000000 0x0 0x80000000
52 0x0 0x200000 52 0x0 0x20000000
53 53
54 0x1000000 0x 54 0x1000000 0x0 0x0
55 0x1000000 0x 55 0x1000000 0x0 0x0
56 0x0 0x100000 56 0x0 0x100000>;
57 }; 57 };
58 }; 58 };
59 }; 59 };
60 60
61 /include/ "p1020rdb.dtsi" 61 /include/ "p1020rdb.dtsi"
62 /include/ "p1020si-post.dtsi" 62 /include/ "p1020si-post.dtsi"
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