1 /*
2 * P1022 RDK 32-bit Physical Address Map Devic
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT
33 */
34
35 /include/ "p1022si-pre.dtsi"
36 / {
37 model = "fsl,P1022RDK";
38 compatible = "fsl,P1022RDK";
39
40 memory {
41 device_type = "memory";
42 };
43
44 board_lbc: lbc: localbus@ffe05000 {
45 /* The P1022 RDK does not have
46 status = "disabled";
47 };
48
49 board_soc: soc: soc@ffe00000 {
50 ranges = <0x0 0x0 0xffe00000 0
51
52 i2c@3100 {
53 wm8960:codec@1a {
54 compatible = "
55 reg = <0x1a>;
56 /* MCLK source
57 clock-frequenc
58 };
59 rtc@68 {
60 compatible = "
61 reg = <0x68>;
62 };
63 adt7461@4c {
64 compatible = "
65 reg = <0x4c>;
66 };
67 zl6100@21 {
68 compatible = "
69 reg = <0x21>;
70 };
71 zl6100@24 {
72 compatible = "
73 reg = <0x24>;
74 };
75 zl6100@26 {
76 compatible = "
77 reg = <0x26>;
78 };
79 zl6100@29 {
80 compatible = "
81 reg = <0x29>;
82 };
83 };
84
85 spi@7000 {
86 flash@0 {
87 #address-cells
88 #size-cells =
89 compatible = "
90 reg = <0>;
91 spi-max-freque
92 partition@0 {
93 label
94 reg =
95 };
96 };
97 };
98
99 ssi@15000 {
100 fsl,mode = "i2s-slave"
101 codec-handle = <&wm896
102 };
103
104 usb@22000 {
105 phy_type = "ulpi";
106 };
107
108 usb@23000 {
109 phy_type = "ulpi";
110 };
111
112 mdio@24000 {
113 phy0: ethernet-phy@0 {
114 interrupts = <
115 reg = <0x1>;
116 };
117 phy1: ethernet-phy@1 {
118 interrupts = <
119 reg = <0x2>;
120 };
121 };
122
123 mdio@25000 {
124 tbi0: tbi-phy@11 {
125 reg = <0x11>;
126 device_type =
127 };
128 };
129
130 ethernet@b0000 {
131 phy-handle = <&phy0>;
132 phy-connection-type =
133 };
134
135 ethernet@b1000 {
136 phy-handle = <&phy1>;
137 tbi-handle = <&tbi0>;
138 phy-connection-type =
139 };
140 };
141
142 pci0: pcie@ffe09000 {
143 ranges = <0x2000000 0x0 0xe000
144 0x1000000 0x0 0x0000
145 reg = <0x0 0xffe09000 0 0x1000
146 pcie@0 {
147 ranges = <0x2000000 0x
148 0x2000000 0x
149 0x0 0x200000
150
151 0x1000000 0x
152 0x1000000 0x
153 0x0 0x100000
154 };
155 };
156
157 pci1: pcie@ffe0a000 {
158 ranges = <0x2000000 0x0 0xe000
159 0x1000000 0x0 0x0000
160 reg = <0 0xffe0a000 0 0x1000>;
161 pcie@0 {
162 ranges = <0x2000000 0x
163 0x2000000 0x
164 0x0 0x200000
165
166 0x1000000 0x
167 0x1000000 0x
168 0x0 0x100000
169 };
170 };
171
172 pci2: pcie@ffe0b000 {
173 ranges = <0x2000000 0x0 0xe000
174 0x1000000 0x0 0x0000
175 reg = <0 0xffe0b000 0 0x1000>;
176 pcie@0 {
177 ranges = <0x2000000 0x
178 0x2000000 0x
179 0x0 0x200000
180
181 0x1000000 0x
182 0x1000000 0x
183 0x0 0x100000
184 };
185 };
186 };
187
188 /include/ "p1022si-post.dtsi"
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