1 // SPDX-License-Identifier: GPL-2.0-or-later <<
2 /* 1 /*
3 * P2020 DS Device Tree Source 2 * P2020 DS Device Tree Source
4 * 3 *
5 * Copyright 2009-2011 Freescale Semiconductor 4 * Copyright 2009-2011 Freescale Semiconductor Inc.
>> 5 *
>> 6 * This program is free software; you can redistribute it and/or modify it
>> 7 * under the terms of the GNU General Public License as published by the
>> 8 * Free Software Foundation; either version 2 of the License, or (at your
>> 9 * option) any later version.
6 */ 10 */
7 11
8 /include/ "p2020si-pre.dtsi" 12 /include/ "p2020si-pre.dtsi"
9 13
10 / { 14 / {
11 model = "fsl,P2020DS"; 15 model = "fsl,P2020DS";
12 compatible = "fsl,P2020DS"; 16 compatible = "fsl,P2020DS";
13 17
14 memory { 18 memory {
15 device_type = "memory"; 19 device_type = "memory";
16 }; 20 };
17 21
18 board_lbc: lbc: localbus@ffe05000 { 22 board_lbc: lbc: localbus@ffe05000 {
19 ranges = <0x0 0x0 0x0 0xe80000 23 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
20 0x1 0x0 0x0 0xe00000 24 0x1 0x0 0x0 0xe0000000 0x08000000
21 0x2 0x0 0x0 0xffa000 25 0x2 0x0 0x0 0xffa00000 0x00040000
22 0x3 0x0 0x0 0xffdf00 26 0x3 0x0 0x0 0xffdf0000 0x00008000
23 0x4 0x0 0x0 0xffa400 27 0x4 0x0 0x0 0xffa40000 0x00040000
24 0x5 0x0 0x0 0xffa800 28 0x5 0x0 0x0 0xffa80000 0x00040000
25 0x6 0x0 0x0 0xffac00 29 0x6 0x0 0x0 0xffac0000 0x00040000>;
26 reg = <0 0xffe05000 0 0x1000>; 30 reg = <0 0xffe05000 0 0x1000>;
27 }; 31 };
28 32
29 board_soc: soc: soc@ffe00000 { 33 board_soc: soc: soc@ffe00000 {
30 ranges = <0x0 0x0 0xffe00000 0 34 ranges = <0x0 0x0 0xffe00000 0x100000>;
31 }; 35 };
32 36
33 pci2: pcie@ffe08000 { 37 pci2: pcie@ffe08000 {
34 ranges = <0x2000000 0x0 0x8000 38 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
35 0x1000000 0x0 0x0000 39 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
36 reg = <0 0xffe08000 0 0x1000>; 40 reg = <0 0xffe08000 0 0x1000>;
37 pcie@0 { 41 pcie@0 {
38 ranges = <0x2000000 0x 42 ranges = <0x2000000 0x0 0x80000000
39 0x2000000 0x 43 0x2000000 0x0 0x80000000
40 0x0 0x200000 44 0x0 0x20000000
41 45
42 0x1000000 0x 46 0x1000000 0x0 0x0
43 0x1000000 0x 47 0x1000000 0x0 0x0
44 0x0 0x10000> 48 0x0 0x10000>;
45 }; 49 };
46 }; 50 };
47 51
48 board_pci1: pci1: pcie@ffe09000 { 52 board_pci1: pci1: pcie@ffe09000 {
49 ranges = <0x2000000 0x0 0xa000 53 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
50 0x1000000 0x0 0x0000 54 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
51 reg = <0 0xffe09000 0 0x1000>; 55 reg = <0 0xffe09000 0 0x1000>;
52 pcie@0 { 56 pcie@0 {
53 ranges = <0x2000000 0x 57 ranges = <0x2000000 0x0 0xa0000000
54 0x2000000 0x 58 0x2000000 0x0 0xa0000000
55 0x0 0x200000 59 0x0 0x20000000
56 60
57 0x1000000 0x 61 0x1000000 0x0 0x0
58 0x1000000 0x 62 0x1000000 0x0 0x0
59 0x0 0x10000> 63 0x0 0x10000>;
60 }; 64 };
61 }; 65 };
62 66
63 pci0: pcie@ffe0a000 { 67 pci0: pcie@ffe0a000 {
64 ranges = <0x2000000 0x0 0xc000 68 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
65 0x1000000 0x0 0x0000 69 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
66 reg = <0 0xffe0a000 0 0x1000>; 70 reg = <0 0xffe0a000 0 0x1000>;
67 pcie@0 { 71 pcie@0 {
68 ranges = <0x2000000 0x 72 ranges = <0x2000000 0x0 0xc0000000
69 0x2000000 0x 73 0x2000000 0x0 0xc0000000
70 0x0 0x200000 74 0x0 0x20000000
71 75
72 0x1000000 0x 76 0x1000000 0x0 0x0
73 0x1000000 0x 77 0x1000000 0x0 0x0
74 0x0 0x10000> 78 0x0 0x10000>;
75 }; 79 };
76 }; 80 };
77 }; 81 };
78 82
79 /* 83 /*
80 * p2020ds.dtsi must be last to ensure board_p 84 * p2020ds.dtsi must be last to ensure board_pci0 overrides pci0 settings
81 * for interrupt-map & interrupt-map-mask 85 * for interrupt-map & interrupt-map-mask
82 */ 86 */
83 87
84 /include/ "p2020si-post.dtsi" 88 /include/ "p2020si-post.dtsi"
85 /include/ "p2020ds.dtsi" 89 /include/ "p2020ds.dtsi"
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