1 /* 1 /*
2 * P3041 Silicon/SoC Device Tree Source (post 2 * P3041 Silicon/SoC Device Tree Source (post include)
3 * 3 *
4 * Copyright 2011 - 2015 Freescale Semiconduct 4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that t 7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must r 8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and t 9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must r 10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and t 11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials 12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semicon 13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used 14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without sp 15 * derived from this software without specific prior written permission.
16 * 16 *
17 * 17 *
18 * ALTERNATIVELY, this software may be distrib 18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as publi 19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that Licens 20 * Foundation, either version 2 of that License or (at your option) any
21 * later version. 21 * later version.
22 * 22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35 &bman_fbpr { 35 &bman_fbpr {
36 compatible = "fsl,bman-fbpr"; 36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>; 37 alloc-ranges = <0 0 0x10 0>;
38 }; 38 };
39 39
40 &qman_fqd { 40 &qman_fqd {
41 compatible = "fsl,qman-fqd"; 41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>; 42 alloc-ranges = <0 0 0x10 0>;
43 }; 43 };
44 44
45 &qman_pfdr { 45 &qman_pfdr {
46 compatible = "fsl,qman-pfdr"; 46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>; 47 alloc-ranges = <0 0 0x10 0>;
48 }; 48 };
49 49
50 &lbc { 50 &lbc {
51 compatible = "fsl,p3041-elbc", "fsl,el 51 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
52 interrupts = <25 2 0 0>; 52 interrupts = <25 2 0 0>;
53 #address-cells = <2>; 53 #address-cells = <2>;
54 #size-cells = <1>; 54 #size-cells = <1>;
55 }; 55 };
56 56
57 /* controller at 0x200000 */ 57 /* controller at 0x200000 */
58 &pci0 { 58 &pci0 {
59 compatible = "fsl,p3041-pcie", "fsl,qo 59 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
60 device_type = "pci"; 60 device_type = "pci";
61 #size-cells = <2>; 61 #size-cells = <2>;
62 #address-cells = <3>; 62 #address-cells = <3>;
63 bus-range = <0x0 0xff>; 63 bus-range = <0x0 0xff>;
64 clock-frequency = <33333333>; 64 clock-frequency = <33333333>;
65 interrupts = <16 2 1 15>; 65 interrupts = <16 2 1 15>;
66 fsl,iommu-parent = <&pamu0>; 66 fsl,iommu-parent = <&pamu0>;
67 fsl,liodn-reg = <&guts 0x500>; /* PEX1 67 fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
68 pcie@0 { 68 pcie@0 {
69 reg = <0 0 0 0 0>; 69 reg = <0 0 0 0 0>;
70 #interrupt-cells = <1>; 70 #interrupt-cells = <1>;
71 #size-cells = <2>; 71 #size-cells = <2>;
72 #address-cells = <3>; 72 #address-cells = <3>;
73 device_type = "pci"; 73 device_type = "pci";
74 interrupts = <16 2 1 15>; 74 interrupts = <16 2 1 15>;
75 interrupt-map-mask = <0xf800 0 75 interrupt-map-mask = <0xf800 0 0 7>;
76 interrupt-map = < 76 interrupt-map = <
77 /* IDSEL 0x0 */ 77 /* IDSEL 0x0 */
78 0000 0 0 1 &mpic 40 1 78 0000 0 0 1 &mpic 40 1 0 0
79 0000 0 0 2 &mpic 1 1 0 79 0000 0 0 2 &mpic 1 1 0 0
80 0000 0 0 3 &mpic 2 1 0 80 0000 0 0 3 &mpic 2 1 0 0
81 0000 0 0 4 &mpic 3 1 0 81 0000 0 0 4 &mpic 3 1 0 0
82 >; 82 >;
83 }; 83 };
84 }; 84 };
85 85
86 /* controller at 0x201000 */ 86 /* controller at 0x201000 */
87 &pci1 { 87 &pci1 {
88 compatible = "fsl,p3041-pcie", "fsl,qo 88 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
89 device_type = "pci"; 89 device_type = "pci";
90 #size-cells = <2>; 90 #size-cells = <2>;
91 #address-cells = <3>; 91 #address-cells = <3>;
92 bus-range = <0 0xff>; 92 bus-range = <0 0xff>;
93 clock-frequency = <33333333>; 93 clock-frequency = <33333333>;
94 interrupts = <16 2 1 14>; 94 interrupts = <16 2 1 14>;
95 fsl,iommu-parent = <&pamu0>; 95 fsl,iommu-parent = <&pamu0>;
96 fsl,liodn-reg = <&guts 0x504>; /* PEX2 96 fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
97 pcie@0 { 97 pcie@0 {
98 reg = <0 0 0 0 0>; 98 reg = <0 0 0 0 0>;
99 #interrupt-cells = <1>; 99 #interrupt-cells = <1>;
100 #size-cells = <2>; 100 #size-cells = <2>;
101 #address-cells = <3>; 101 #address-cells = <3>;
102 device_type = "pci"; 102 device_type = "pci";
103 interrupts = <16 2 1 14>; 103 interrupts = <16 2 1 14>;
104 interrupt-map-mask = <0xf800 0 104 interrupt-map-mask = <0xf800 0 0 7>;
105 interrupt-map = < 105 interrupt-map = <
106 /* IDSEL 0x0 */ 106 /* IDSEL 0x0 */
107 0000 0 0 1 &mpic 41 1 107 0000 0 0 1 &mpic 41 1 0 0
108 0000 0 0 2 &mpic 5 1 0 108 0000 0 0 2 &mpic 5 1 0 0
109 0000 0 0 3 &mpic 6 1 0 109 0000 0 0 3 &mpic 6 1 0 0
110 0000 0 0 4 &mpic 7 1 0 110 0000 0 0 4 &mpic 7 1 0 0
111 >; 111 >;
112 }; 112 };
113 }; 113 };
114 114
115 /* controller at 0x202000 */ 115 /* controller at 0x202000 */
116 &pci2 { 116 &pci2 {
117 compatible = "fsl,p3041-pcie", "fsl,qo 117 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
118 device_type = "pci"; 118 device_type = "pci";
119 #size-cells = <2>; 119 #size-cells = <2>;
120 #address-cells = <3>; 120 #address-cells = <3>;
121 bus-range = <0x0 0xff>; 121 bus-range = <0x0 0xff>;
122 clock-frequency = <33333333>; 122 clock-frequency = <33333333>;
123 interrupts = <16 2 1 13>; 123 interrupts = <16 2 1 13>;
124 fsl,iommu-parent = <&pamu0>; 124 fsl,iommu-parent = <&pamu0>;
125 fsl,liodn-reg = <&guts 0x508>; /* PEX3 125 fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
126 pcie@0 { 126 pcie@0 {
127 reg = <0 0 0 0 0>; 127 reg = <0 0 0 0 0>;
128 #interrupt-cells = <1>; 128 #interrupt-cells = <1>;
129 #size-cells = <2>; 129 #size-cells = <2>;
130 #address-cells = <3>; 130 #address-cells = <3>;
131 device_type = "pci"; 131 device_type = "pci";
132 interrupts = <16 2 1 13>; 132 interrupts = <16 2 1 13>;
133 interrupt-map-mask = <0xf800 0 133 interrupt-map-mask = <0xf800 0 0 7>;
134 interrupt-map = < 134 interrupt-map = <
135 /* IDSEL 0x0 */ 135 /* IDSEL 0x0 */
136 0000 0 0 1 &mpic 42 1 136 0000 0 0 1 &mpic 42 1 0 0
137 0000 0 0 2 &mpic 9 1 0 137 0000 0 0 2 &mpic 9 1 0 0
138 0000 0 0 3 &mpic 10 1 138 0000 0 0 3 &mpic 10 1 0 0
139 0000 0 0 4 &mpic 11 1 139 0000 0 0 4 &mpic 11 1 0 0
140 >; 140 >;
141 }; 141 };
142 }; 142 };
143 143
144 /* controller at 0x203000 */ 144 /* controller at 0x203000 */
145 &pci3 { 145 &pci3 {
146 compatible = "fsl,p3041-pcie", "fsl,qo 146 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
147 device_type = "pci"; 147 device_type = "pci";
148 #size-cells = <2>; 148 #size-cells = <2>;
149 #address-cells = <3>; 149 #address-cells = <3>;
150 bus-range = <0x0 0xff>; 150 bus-range = <0x0 0xff>;
151 clock-frequency = <33333333>; 151 clock-frequency = <33333333>;
152 interrupts = <16 2 1 12>; 152 interrupts = <16 2 1 12>;
153 pcie@0 { 153 pcie@0 {
154 reg = <0 0 0 0 0>; 154 reg = <0 0 0 0 0>;
155 #interrupt-cells = <1>; 155 #interrupt-cells = <1>;
156 #size-cells = <2>; 156 #size-cells = <2>;
157 #address-cells = <3>; 157 #address-cells = <3>;
158 device_type = "pci"; 158 device_type = "pci";
159 interrupts = <16 2 1 12>; 159 interrupts = <16 2 1 12>;
160 interrupt-map-mask = <0xf800 0 160 interrupt-map-mask = <0xf800 0 0 7>;
161 interrupt-map = < 161 interrupt-map = <
162 /* IDSEL 0x0 */ 162 /* IDSEL 0x0 */
163 0000 0 0 1 &mpic 43 1 163 0000 0 0 1 &mpic 43 1 0 0
164 0000 0 0 2 &mpic 0 1 0 164 0000 0 0 2 &mpic 0 1 0 0
165 0000 0 0 3 &mpic 4 1 0 165 0000 0 0 3 &mpic 4 1 0 0
166 0000 0 0 4 &mpic 8 1 0 166 0000 0 0 4 &mpic 8 1 0 0
167 >; 167 >;
168 }; 168 };
169 }; 169 };
170 170
171 &rio { 171 &rio {
172 compatible = "fsl,srio"; 172 compatible = "fsl,srio";
173 interrupts = <16 2 1 11>; 173 interrupts = <16 2 1 11>;
174 #address-cells = <2>; 174 #address-cells = <2>;
175 #size-cells = <2>; 175 #size-cells = <2>;
176 fsl,iommu-parent = <&pamu0>; 176 fsl,iommu-parent = <&pamu0>;
177 ranges; 177 ranges;
178 178
179 port1 { 179 port1 {
180 #address-cells = <2>; 180 #address-cells = <2>;
181 #size-cells = <2>; 181 #size-cells = <2>;
182 cell-index = <1>; 182 cell-index = <1>;
183 fsl,liodn-reg = <&guts 0x510>; 183 fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
184 }; 184 };
185 185
186 port2 { 186 port2 {
187 #address-cells = <2>; 187 #address-cells = <2>;
188 #size-cells = <2>; 188 #size-cells = <2>;
189 cell-index = <2>; 189 cell-index = <2>;
190 fsl,liodn-reg = <&guts 0x514>; 190 fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
191 }; 191 };
192 }; 192 };
193 193
194 &dcsr { 194 &dcsr {
195 #address-cells = <1>; 195 #address-cells = <1>;
196 #size-cells = <1>; 196 #size-cells = <1>;
197 compatible = "fsl,dcsr", "simple-bus"; 197 compatible = "fsl,dcsr", "simple-bus";
198 198
199 dcsr-epu@0 { 199 dcsr-epu@0 {
200 compatible = "fsl,p3041-dcsr-e 200 compatible = "fsl,p3041-dcsr-epu", "fsl,dcsr-epu";
201 interrupts = <52 2 0 0 201 interrupts = <52 2 0 0
202 84 2 0 0 202 84 2 0 0
203 85 2 0 0>; 203 85 2 0 0>;
204 reg = <0x0 0x1000>; 204 reg = <0x0 0x1000>;
205 }; 205 };
206 dcsr-npc { 206 dcsr-npc {
207 compatible = "fsl,dcsr-npc"; 207 compatible = "fsl,dcsr-npc";
208 reg = <0x1000 0x1000 0x1000000 208 reg = <0x1000 0x1000 0x1000000 0x8000>;
209 }; 209 };
210 dcsr-nxc@2000 { 210 dcsr-nxc@2000 {
211 compatible = "fsl,dcsr-nxc"; 211 compatible = "fsl,dcsr-nxc";
212 reg = <0x2000 0x1000>; 212 reg = <0x2000 0x1000>;
213 }; 213 };
214 dcsr-corenet { 214 dcsr-corenet {
215 compatible = "fsl,dcsr-corenet 215 compatible = "fsl,dcsr-corenet";
216 reg = <0x8000 0x1000 0xB0000 0 216 reg = <0x8000 0x1000 0xB0000 0x1000>;
217 }; 217 };
218 dcsr-dpaa@9000 { 218 dcsr-dpaa@9000 {
219 compatible = "fsl,p3041-dcsr-d 219 compatible = "fsl,p3041-dcsr-dpaa", "fsl,dcsr-dpaa";
220 reg = <0x9000 0x1000>; 220 reg = <0x9000 0x1000>;
221 }; 221 };
222 dcsr-ocn@11000 { 222 dcsr-ocn@11000 {
223 compatible = "fsl,p3041-dcsr-o 223 compatible = "fsl,p3041-dcsr-ocn", "fsl,dcsr-ocn";
224 reg = <0x11000 0x1000>; 224 reg = <0x11000 0x1000>;
225 }; 225 };
226 dcsr-ddr@12000 { 226 dcsr-ddr@12000 {
227 compatible = "fsl,dcsr-ddr"; 227 compatible = "fsl,dcsr-ddr";
228 dev-handle = <&ddr1>; 228 dev-handle = <&ddr1>;
229 reg = <0x12000 0x1000>; 229 reg = <0x12000 0x1000>;
230 }; 230 };
231 dcsr-nal@18000 { 231 dcsr-nal@18000 {
232 compatible = "fsl,p3041-dcsr-n 232 compatible = "fsl,p3041-dcsr-nal", "fsl,dcsr-nal";
233 reg = <0x18000 0x1000>; 233 reg = <0x18000 0x1000>;
234 }; 234 };
235 dcsr-rcpm@22000 { 235 dcsr-rcpm@22000 {
236 compatible = "fsl,p3041-dcsr-r 236 compatible = "fsl,p3041-dcsr-rcpm", "fsl,dcsr-rcpm";
237 reg = <0x22000 0x1000>; 237 reg = <0x22000 0x1000>;
238 }; 238 };
239 dcsr-cpu-sb-proxy@40000 { 239 dcsr-cpu-sb-proxy@40000 {
240 compatible = "fsl,dcsr-e500mc- 240 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
241 cpu-handle = <&cpu0>; 241 cpu-handle = <&cpu0>;
242 reg = <0x40000 0x1000>; 242 reg = <0x40000 0x1000>;
243 }; 243 };
244 dcsr-cpu-sb-proxy@41000 { 244 dcsr-cpu-sb-proxy@41000 {
245 compatible = "fsl,dcsr-e500mc- 245 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
246 cpu-handle = <&cpu1>; 246 cpu-handle = <&cpu1>;
247 reg = <0x41000 0x1000>; 247 reg = <0x41000 0x1000>;
248 }; 248 };
249 dcsr-cpu-sb-proxy@42000 { 249 dcsr-cpu-sb-proxy@42000 {
250 compatible = "fsl,dcsr-e500mc- 250 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
251 cpu-handle = <&cpu2>; 251 cpu-handle = <&cpu2>;
252 reg = <0x42000 0x1000>; 252 reg = <0x42000 0x1000>;
253 }; 253 };
254 dcsr-cpu-sb-proxy@43000 { 254 dcsr-cpu-sb-proxy@43000 {
255 compatible = "fsl,dcsr-e500mc- 255 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
256 cpu-handle = <&cpu3>; 256 cpu-handle = <&cpu3>;
257 reg = <0x43000 0x1000>; 257 reg = <0x43000 0x1000>;
258 }; 258 };
259 }; 259 };
260 260
261 /include/ "qoriq-bman1-portals.dtsi" 261 /include/ "qoriq-bman1-portals.dtsi"
262 262
263 /include/ "qoriq-qman1-portals.dtsi" 263 /include/ "qoriq-qman1-portals.dtsi"
264 264
265 &soc { 265 &soc {
266 #address-cells = <1>; 266 #address-cells = <1>;
267 #size-cells = <1>; 267 #size-cells = <1>;
268 device_type = "soc"; 268 device_type = "soc";
269 compatible = "simple-bus"; 269 compatible = "simple-bus";
270 270
271 soc-sram-error { 271 soc-sram-error {
272 compatible = "fsl,soc-sram-err 272 compatible = "fsl,soc-sram-error";
273 interrupts = <16 2 1 29>; 273 interrupts = <16 2 1 29>;
274 }; 274 };
275 275
276 corenet-law@0 { 276 corenet-law@0 {
277 compatible = "fsl,corenet-law" 277 compatible = "fsl,corenet-law";
278 reg = <0x0 0x1000>; 278 reg = <0x0 0x1000>;
279 fsl,num-laws = <32>; 279 fsl,num-laws = <32>;
280 }; 280 };
281 281
282 ddr1: memory-controller@8000 { 282 ddr1: memory-controller@8000 {
283 compatible = "fsl,qoriq-memory 283 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
284 reg = <0x8000 0x1000>; 284 reg = <0x8000 0x1000>;
285 interrupts = <16 2 1 23>; 285 interrupts = <16 2 1 23>;
286 }; 286 };
287 287
288 cpc: l3-cache-controller@10000 { 288 cpc: l3-cache-controller@10000 {
289 compatible = "fsl,p3041-l3-cac 289 compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
290 reg = <0x10000 0x1000>; 290 reg = <0x10000 0x1000>;
291 interrupts = <16 2 1 27>; 291 interrupts = <16 2 1 27>;
292 }; 292 };
293 293
294 corenet-cf@18000 { 294 corenet-cf@18000 {
295 compatible = "fsl,corenet1-cf" 295 compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
296 reg = <0x18000 0x1000>; 296 reg = <0x18000 0x1000>;
297 interrupts = <16 2 1 31>; 297 interrupts = <16 2 1 31>;
298 fsl,ccf-num-csdids = <32>; 298 fsl,ccf-num-csdids = <32>;
299 fsl,ccf-num-snoopids = <32>; 299 fsl,ccf-num-snoopids = <32>;
300 }; 300 };
301 301
302 iommu@20000 { 302 iommu@20000 {
303 compatible = "fsl,pamu-v1.0", 303 compatible = "fsl,pamu-v1.0", "fsl,pamu";
304 reg = <0x20000 0x4000>; /* for 304 reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */
305 ranges = <0 0x20000 0x4000>; 305 ranges = <0 0x20000 0x4000>;
306 #address-cells = <1>; 306 #address-cells = <1>;
307 #size-cells = <1>; 307 #size-cells = <1>;
308 interrupts = < 308 interrupts = <
309 24 2 0 0 309 24 2 0 0
310 16 2 1 30>; 310 16 2 1 30>;
311 fsl,portid-mapping = <0x0f0000 311 fsl,portid-mapping = <0x0f000000>;
312 312
313 pamu0: pamu@0 { 313 pamu0: pamu@0 {
314 reg = <0 0x1000>; 314 reg = <0 0x1000>;
315 fsl,primary-cache-geom 315 fsl,primary-cache-geometry = <32 1>;
316 fsl,secondary-cache-ge 316 fsl,secondary-cache-geometry = <128 2>;
317 }; 317 };
318 318
319 pamu1: pamu@1000 { 319 pamu1: pamu@1000 {
320 reg = <0x1000 0x1000>; 320 reg = <0x1000 0x1000>;
321 fsl,primary-cache-geom 321 fsl,primary-cache-geometry = <32 1>;
322 fsl,secondary-cache-ge 322 fsl,secondary-cache-geometry = <128 2>;
323 }; 323 };
324 324
325 pamu2: pamu@2000 { 325 pamu2: pamu@2000 {
326 reg = <0x2000 0x1000>; 326 reg = <0x2000 0x1000>;
327 fsl,primary-cache-geom 327 fsl,primary-cache-geometry = <32 1>;
328 fsl,secondary-cache-ge 328 fsl,secondary-cache-geometry = <128 2>;
329 }; 329 };
330 330
331 pamu3: pamu@3000 { 331 pamu3: pamu@3000 {
332 reg = <0x3000 0x1000>; 332 reg = <0x3000 0x1000>;
333 fsl,primary-cache-geom 333 fsl,primary-cache-geometry = <32 1>;
334 fsl,secondary-cache-ge 334 fsl,secondary-cache-geometry = <128 2>;
335 }; 335 };
336 }; 336 };
337 337
338 /include/ "qoriq-mpic.dtsi" 338 /include/ "qoriq-mpic.dtsi"
339 339
340 guts: global-utilities@e0000 { 340 guts: global-utilities@e0000 {
341 compatible = "fsl,qoriq-device 341 compatible = "fsl,qoriq-device-config-1.0";
342 reg = <0xe0000 0xe00>; 342 reg = <0xe0000 0xe00>;
343 fsl,has-rstcr; 343 fsl,has-rstcr;
344 #sleep-cells = <1>; 344 #sleep-cells = <1>;
345 fsl,liodn-bits = <12>; 345 fsl,liodn-bits = <12>;
346 }; 346 };
347 347
348 pins: global-utilities@e0e00 { 348 pins: global-utilities@e0e00 {
349 compatible = "fsl,qoriq-pin-co 349 compatible = "fsl,qoriq-pin-control-1.0";
350 reg = <0xe0e00 0x200>; 350 reg = <0xe0e00 0x200>;
351 #sleep-cells = <2>; 351 #sleep-cells = <2>;
352 }; 352 };
353 353
354 /include/ "qoriq-clockgen1.dtsi" 354 /include/ "qoriq-clockgen1.dtsi"
355 global-utilities@e1000 { 355 global-utilities@e1000 {
356 compatible = "fsl,p3041-clockg 356 compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
>> 357
>> 358 mux2: mux2@40 {
>> 359 #clock-cells = <0>;
>> 360 reg = <0x40 0x4>;
>> 361 compatible = "fsl,qoriq-core-mux-1.0";
>> 362 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
>> 363 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
>> 364 clock-output-names = "cmux2";
>> 365 };
>> 366
>> 367 mux3: mux3@60 {
>> 368 #clock-cells = <0>;
>> 369 reg = <0x60 0x4>;
>> 370 compatible = "fsl,qoriq-core-mux-1.0";
>> 371 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
>> 372 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
>> 373 clock-output-names = "cmux3";
>> 374 };
357 }; 375 };
358 376
359 rcpm: global-utilities@e2000 { 377 rcpm: global-utilities@e2000 {
360 compatible = "fsl,qoriq-rcpm-1 378 compatible = "fsl,qoriq-rcpm-1.0";
361 reg = <0xe2000 0x1000>; 379 reg = <0xe2000 0x1000>;
362 #sleep-cells = <1>; 380 #sleep-cells = <1>;
363 }; 381 };
364 382
365 sfp: sfp@e8000 { 383 sfp: sfp@e8000 {
366 compatible = "fsl,p3041-sfp", 384 compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0";
367 reg = <0xe8000 0x1000>; 385 reg = <0xe8000 0x1000>;
368 }; 386 };
369 387
370 serdes: serdes@ea000 { 388 serdes: serdes@ea000 {
371 compatible = "fsl,p3041-serdes 389 compatible = "fsl,p3041-serdes";
372 reg = <0xea000 0x1000>; 390 reg = <0xea000 0x1000>;
373 }; 391 };
374 392
375 /include/ "qoriq-dma-0.dtsi" 393 /include/ "qoriq-dma-0.dtsi"
376 dma@100300 { 394 dma@100300 {
377 fsl,iommu-parent = <&pamu0>; 395 fsl,iommu-parent = <&pamu0>;
378 fsl,liodn-reg = <&guts 0x580>; 396 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
379 }; 397 };
380 398
381 /include/ "qoriq-dma-1.dtsi" 399 /include/ "qoriq-dma-1.dtsi"
382 dma@101300 { 400 dma@101300 {
383 fsl,iommu-parent = <&pamu0>; 401 fsl,iommu-parent = <&pamu0>;
384 fsl,liodn-reg = <&guts 0x584>; 402 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
385 }; 403 };
386 404
387 /include/ "qoriq-espi-0.dtsi" 405 /include/ "qoriq-espi-0.dtsi"
388 spi@110000 { 406 spi@110000 {
389 fsl,espi-num-chipselects = <4> 407 fsl,espi-num-chipselects = <4>;
390 }; 408 };
391 409
392 /include/ "qoriq-esdhc-0.dtsi" 410 /include/ "qoriq-esdhc-0.dtsi"
393 sdhc@114000 { 411 sdhc@114000 {
394 compatible = "fsl,p3041-esdhc" 412 compatible = "fsl,p3041-esdhc", "fsl,esdhc";
395 fsl,iommu-parent = <&pamu1>; 413 fsl,iommu-parent = <&pamu1>;
396 fsl,liodn-reg = <&guts 0x530>; 414 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
397 sdhci,auto-cmd12; 415 sdhci,auto-cmd12;
398 }; 416 };
399 417
400 /include/ "qoriq-i2c-0.dtsi" 418 /include/ "qoriq-i2c-0.dtsi"
401 /include/ "qoriq-i2c-1.dtsi" 419 /include/ "qoriq-i2c-1.dtsi"
402 /include/ "qoriq-duart-0.dtsi" 420 /include/ "qoriq-duart-0.dtsi"
403 /include/ "qoriq-duart-1.dtsi" 421 /include/ "qoriq-duart-1.dtsi"
404 /include/ "qoriq-gpio-0.dtsi" 422 /include/ "qoriq-gpio-0.dtsi"
405 /include/ "qoriq-usb2-mph-0.dtsi" 423 /include/ "qoriq-usb2-mph-0.dtsi"
406 usb0: usb@210000 { 424 usb0: usb@210000 {
407 compatible = "fsl-usb2-mph-v1. 425 compatible = "fsl-usb2-mph-v1.6", "fsl-usb2-mph";
408 phy_type = "utmi"; 426 phy_type = "utmi";
409 fsl,iommu-parent = <&pamu1>; 427 fsl,iommu-parent = <&pamu1>;
410 fsl,liodn-reg = <&guts 0x520>; 428 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
411 port0; 429 port0;
412 }; 430 };
413 431
414 /include/ "qoriq-usb2-dr-0.dtsi" 432 /include/ "qoriq-usb2-dr-0.dtsi"
415 usb1: usb@211000 { 433 usb1: usb@211000 {
416 compatible = "fsl-usb2-dr-v1.6 434 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
417 fsl,iommu-parent = <&pamu1>; 435 fsl,iommu-parent = <&pamu1>;
418 fsl,liodn-reg = <&guts 0x524>; 436 fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
419 dr_mode = "host"; 437 dr_mode = "host";
420 phy_type = "utmi"; 438 phy_type = "utmi";
421 }; 439 };
422 440
423 /include/ "qoriq-sata2-0.dtsi" 441 /include/ "qoriq-sata2-0.dtsi"
424 sata@220000 { 442 sata@220000 {
425 fsl,iommu-parent = <&pamu1>; 443 fsl,iommu-parent = <&pamu1>;
426 fsl,liodn-reg = <&guts 0x550>; 444 fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
427 }; 445 };
428 446
429 /include/ "qoriq-sata2-1.dtsi" 447 /include/ "qoriq-sata2-1.dtsi"
430 sata@221000 { 448 sata@221000 {
431 fsl,iommu-parent = <&pamu1>; 449 fsl,iommu-parent = <&pamu1>;
432 fsl,liodn-reg = <&guts 0x554>; 450 fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
433 }; 451 };
434 452
435 /include/ "qoriq-sec4.2-0.dtsi" 453 /include/ "qoriq-sec4.2-0.dtsi"
436 crypto: crypto@300000 { 454 crypto: crypto@300000 {
437 fsl,iommu-parent = <&pamu1>; 455 fsl,iommu-parent = <&pamu1>;
438 }; 456 };
439 457
440 /include/ "qoriq-qman1.dtsi" 458 /include/ "qoriq-qman1.dtsi"
441 /include/ "qoriq-bman1.dtsi" 459 /include/ "qoriq-bman1.dtsi"
442 460
443 /include/ "qoriq-fman-0.dtsi" 461 /include/ "qoriq-fman-0.dtsi"
444 /include/ "qoriq-fman-0-1g-0.dtsi" 462 /include/ "qoriq-fman-0-1g-0.dtsi"
445 /include/ "qoriq-fman-0-1g-1.dtsi" 463 /include/ "qoriq-fman-0-1g-1.dtsi"
446 /include/ "qoriq-fman-0-1g-2.dtsi" 464 /include/ "qoriq-fman-0-1g-2.dtsi"
447 /include/ "qoriq-fman-0-1g-3.dtsi" 465 /include/ "qoriq-fman-0-1g-3.dtsi"
448 /include/ "qoriq-fman-0-1g-4.dtsi" 466 /include/ "qoriq-fman-0-1g-4.dtsi"
449 /include/ "qoriq-fman-0-10g-0.dtsi" 467 /include/ "qoriq-fman-0-10g-0.dtsi"
450 fman@400000 { 468 fman@400000 {
451 enet0: ethernet@e0000 { 469 enet0: ethernet@e0000 {
452 }; 470 };
453 471
454 enet1: ethernet@e2000 { 472 enet1: ethernet@e2000 {
455 }; 473 };
456 474
457 enet2: ethernet@e4000 { 475 enet2: ethernet@e4000 {
458 }; 476 };
459 477
460 enet3: ethernet@e6000 { 478 enet3: ethernet@e6000 {
461 }; 479 };
462 480
463 enet4: ethernet@e8000 { 481 enet4: ethernet@e8000 {
464 }; 482 };
465 483
466 enet5: ethernet@f0000 { 484 enet5: ethernet@f0000 {
467 }; 485 };
468 }; 486 };
469 }; 487 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.