1 /*
2 * P5020DS Device Tree Source
3 *
4 * Copyright 2010 - 2015 Freescale Semiconduct
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT
33 */
34
35 /include/ "p5020si-pre.dtsi"
36
37 / {
38 model = "fsl,P5020DS";
39 compatible = "fsl,P5020DS";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 aliases {
45 phy_rgmii_0 = &phy_rgmii_0;
46 phy_rgmii_1 = &phy_rgmii_1;
47 phy_sgmii_1c = &phy_sgmii_1c;
48 phy_sgmii_1d = &phy_sgmii_1d;
49 phy_sgmii_1e = &phy_sgmii_1e;
50 phy_sgmii_1f = &phy_sgmii_1f;
51 phy_xgmii_1 = &phy_xgmii_1;
52 phy_xgmii_2 = &phy_xgmii_2;
53 emi1_rgmii = &hydra_mdio_rgmii
54 emi1_sgmii = &hydra_mdio_sgmii
55 emi2_xgmii = &hydra_mdio_xgmii
56 };
57
58 memory {
59 device_type = "memory";
60 };
61
62 reserved-memory {
63 #address-cells = <2>;
64 #size-cells = <2>;
65 ranges;
66
67 bman_fbpr: bman-fbpr {
68 size = <0 0x1000000>;
69 alignment = <0 0x10000
70 };
71 qman_fqd: qman-fqd {
72 size = <0 0x400000>;
73 alignment = <0 0x40000
74 };
75 qman_pfdr: qman-pfdr {
76 size = <0 0x2000000>;
77 alignment = <0 0x20000
78 };
79 };
80
81 dcsr: dcsr@f00000000 {
82 ranges = <0x00000000 0xf 0x000
83 };
84
85 bportals: bman-portals@ff4000000 {
86 ranges = <0x0 0xf 0xf4000000 0
87 };
88
89 qportals: qman-portals@ff4200000 {
90 ranges = <0x0 0xf 0xf4200000 0
91 };
92
93 soc: soc@ffe000000 {
94 ranges = <0x00000000 0xf 0xfe0
95 reg = <0xf 0xfe000000 0 0x0000
96 spi@110000 {
97 flash@0 {
98 #address-cells
99 #size-cells =
100 compatible = "
101 reg = <0>;
102 spi-max-freque
103 partition@u-bo
104 label
105 reg =
106 read-o
107 };
108 partition@kern
109 label
110 reg =
111 read-o
112 };
113 partition@dtb
114 label
115 reg =
116 read-o
117 };
118 partition@fs {
119 label
120 reg =
121 };
122 };
123 };
124
125 i2c@118100 {
126 eeprom@51 {
127 compatible = "
128 reg = <0x51>;
129 };
130 eeprom@52 {
131 compatible = "
132 reg = <0x52>;
133 };
134 };
135
136 i2c@119100 {
137 rtc@68 {
138 compatible = "
139 reg = <0x68>;
140 interrupts = <
141 };
142 ina220@40 {
143 compatible = "
144 reg = <0x40>;
145 shunt-resistor
146 };
147 ina220@41 {
148 compatible = "
149 reg = <0x41>;
150 shunt-resistor
151 };
152 ina220@44 {
153 compatible = "
154 reg = <0x44>;
155 shunt-resistor
156 };
157 ina220@45 {
158 compatible = "
159 reg = <0x45>;
160 shunt-resistor
161 };
162 adt7461@4c {
163 compatible = "
164 reg = <0x4c>;
165 };
166 };
167
168 fman@400000 {
169 ethernet@e0000 {
170 phy-handle = <
171 phy-connection
172 };
173
174 ethernet@e2000 {
175 phy-handle = <
176 phy-connection
177 };
178
179 ethernet@e4000 {
180 phy-handle = <
181 phy-connection
182 };
183
184 ethernet@e6000 {
185 phy-handle = <
186 phy-connection
187 };
188
189 ethernet@e8000 {
190 phy-handle = <
191 phy-connection
192 };
193
194 ethernet@f0000 {
195 phy-handle = <
196 phy-connection
197 };
198
199 hydra_mdio_xgmii: mdio
200 status = "disa
201
202 phy_xgmii_1: e
203 compat
204 reg =
205 };
206
207 phy_xgmii_2: e
208 compat
209 reg =
210 };
211 };
212 };
213 };
214
215 rio: rapidio@ffe0c0000 {
216 reg = <0xf 0xfe0c0000 0 0x1100
217
218 port1 {
219 ranges = <0 0 0xc 0x20
220 };
221 port2 {
222 ranges = <0 0 0xc 0x30
223 };
224 };
225
226 lbc: localbus@ffe124000 {
227 reg = <0xf 0xfe124000 0 0x1000
228 ranges = <0 0 0xf 0xe8000000 0
229 2 0 0xf 0xffa00000 0
230 3 0 0xf 0xffdf0000 0
231
232 flash@0,0 {
233 compatible = "cfi-flas
234 reg = <0 0 0x08000000>
235 bank-width = <2>;
236 device-width = <2>;
237 };
238
239 nand@2,0 {
240 #address-cells = <1>;
241 #size-cells = <1>;
242 compatible = "fsl,elbc
243 reg = <0x2 0x0 0x40000
244
245 partition@0 {
246 label = "NAND
247 reg = <0x0 0x0
248 read-only;
249 };
250
251 partition@2000000 {
252 label = "NAND
253 reg = <0x02000
254 };
255
256 partition@12000000 {
257 label = "NAND
258 reg = <0x12000
259 };
260
261 partition@1a000000 {
262 label = "NAND
263 reg = <0x1a000
264 };
265
266 partition@1e000000 {
267 label = "NAND
268 reg = <0x1e000
269 };
270
271 partition@1f000000 {
272 label = "NAND
273 reg = <0x1f000
274 };
275 };
276
277 board-control@3,0 {
278 #address-cells = <1>;
279 #size-cells = <1>;
280 compatible = "fsl,p502
281 reg = <3 0 0x30>;
282 ranges = <0 3 0 0x30>;
283
284 mdio-mux-emi1 {
285 #address-cells
286 #size-cells =
287 compatible = "
288 mdio-parent-bu
289 reg = <9 1>;
290 mux-mask = <0x
291
292 hydra_mdio_rgm
293 #addre
294 #size-
295 reg =
296 status
297
298 phy_rg
299
300 };
301
302 phy_rg
303
304 };
305 };
306
307 hydra_mdio_sgm
308 #addre
309 #size-
310 reg =
311 status
312
313 phy_sg
314
315 };
316
317 phy_sg
318
319 };
320
321 phy_sg
322
323 };
324
325 phy_sg
326
327 };
328 };
329 };
330 };
331 };
332
333 pci0: pcie@ffe200000 {
334 reg = <0xf 0xfe200000 0 0x1000
335 ranges = <0x02000000 0 0xe0000
336 0x01000000 0 0x00000
337 pcie@0 {
338 ranges = <0x02000000 0
339 0x02000000 0
340 0 0x20000000
341
342 0x01000000 0
343 0x01000000 0
344 0 0x00010000
345 };
346 };
347
348 pci1: pcie@ffe201000 {
349 reg = <0xf 0xfe201000 0 0x1000
350 ranges = <0x02000000 0x0 0xe00
351 0x01000000 0x0 0x000
352 pcie@0 {
353 ranges = <0x02000000 0
354 0x02000000 0
355 0 0x20000000
356
357 0x01000000 0
358 0x01000000 0
359 0 0x00010000
360 };
361 };
362
363 pci2: pcie@ffe202000 {
364 reg = <0xf 0xfe202000 0 0x1000
365 ranges = <0x02000000 0 0xe0000
366 0x01000000 0 0x00000
367 pcie@0 {
368 ranges = <0x02000000 0
369 0x02000000 0
370 0 0x20000000
371
372 0x01000000 0
373 0x01000000 0
374 0 0x00010000
375 };
376 };
377
378 pci3: pcie@ffe203000 {
379 reg = <0xf 0xfe203000 0 0x1000
380 ranges = <0x02000000 0 0xe0000
381 0x01000000 0 0x00000
382 pcie@0 {
383 ranges = <0x02000000 0
384 0x02000000 0
385 0 0x20000000
386
387 0x01000000 0
388 0x01000000 0
389 0 0x00010000
390 };
391 };
392 };
393
394 /include/ "p5020si-post.dtsi"
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