1 /*
2 * P5040DS Device Tree Source
3 *
4 * Copyright 2012 - 2015 Freescale Semiconduct
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * This software is provided by Freescale Semi
24 * express or implied warranties, including, b
25 * warranties of merchantability and fitness f
26 * disclaimed. In no event shall Freescale Sem
27 * direct, indirect, incidental, special, exem
28 * (including, but not limited to, procurement
29 * loss of use, data, or profits; or business
30 * on any theory of liability, whether in cont
31 * (including negligence or otherwise) arising
32 * software, even if advised of the possibilit
33 */
34
35 /include/ "p5040si-pre.dtsi"
36
37 / {
38 model = "fsl,P5040DS";
39 compatible = "fsl,P5040DS";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 aliases {
45 phy_sgmii_slot2_1c = &phy_sgmi
46 phy_sgmii_slot2_1d = &phy_sgmi
47 phy_sgmii_slot2_1e = &phy_sgmi
48 phy_sgmii_slot2_1f = &phy_sgmi
49 phy_sgmii_slot3_1c = &phy_sgmi
50 phy_sgmii_slot3_1d = &phy_sgmi
51 phy_sgmii_slot3_1e = &phy_sgmi
52 phy_sgmii_slot3_1f = &phy_sgmi
53 phy_sgmii_slot5_1c = &phy_sgmi
54 phy_sgmii_slot5_1d = &phy_sgmi
55 phy_sgmii_slot5_1e = &phy_sgmi
56 phy_sgmii_slot5_1f = &phy_sgmi
57 phy_sgmii_slot6_1c = &phy_sgmi
58 phy_sgmii_slot6_1d = &phy_sgmi
59 phy_sgmii_slot6_1e = &phy_sgmi
60 phy_sgmii_slot6_1f = &phy_sgmi
61 hydra_rg = &hydra_rg;
62 hydra_sg_slot2 = &hydra_sg_slo
63 hydra_sg_slot3 = &hydra_sg_slo
64 hydra_sg_slot5 = &hydra_sg_slo
65 hydra_sg_slot6 = &hydra_sg_slo
66 hydra_xg_slot1 = &hydra_xg_slo
67 hydra_xg_slot2 = &hydra_xg_slo
68 };
69
70 memory {
71 device_type = "memory";
72 };
73
74 reserved-memory {
75 #address-cells = <2>;
76 #size-cells = <2>;
77 ranges;
78
79 bman_fbpr: bman-fbpr {
80 size = <0 0x1000000>;
81 alignment = <0 0x10000
82 };
83 qman_fqd: qman-fqd {
84 size = <0 0x400000>;
85 alignment = <0 0x40000
86 };
87 qman_pfdr: qman-pfdr {
88 size = <0 0x2000000>;
89 alignment = <0 0x20000
90 };
91 };
92
93 dcsr: dcsr@f00000000 {
94 ranges = <0x00000000 0xf 0x000
95 };
96
97 bportals: bman-portals@ff4000000 {
98 ranges = <0x0 0xf 0xf4000000 0
99 };
100
101 qportals: qman-portals@ff4200000 {
102 ranges = <0x0 0xf 0xf4200000 0
103 };
104
105 soc: soc@ffe000000 {
106 ranges = <0x00000000 0xf 0xfe0
107 reg = <0xf 0xfe000000 0 0x0000
108 spi@110000 {
109 flash@0 {
110 #address-cells
111 #size-cells =
112 compatible = "
113 reg = <0>;
114 spi-max-freque
115 partition@u-bo
116 label
117 reg =
118 };
119 partition@kern
120 label
121 reg =
122 };
123 partition@dtb
124 label
125 reg =
126 };
127 partition@fs {
128 label
129 reg =
130 };
131 };
132 };
133
134 i2c@118100 {
135 eeprom@51 {
136 compatible = "
137 reg = <0x51>;
138 };
139 eeprom@52 {
140 compatible = "
141 reg = <0x52>;
142 };
143 };
144
145 i2c@119100 {
146 rtc@68 {
147 compatible = "
148 reg = <0x68>;
149 interrupts = <
150 };
151 ina220@40 {
152 compatible = "
153 reg = <0x40>;
154 shunt-resistor
155 };
156 ina220@41 {
157 compatible = "
158 reg = <0x41>;
159 shunt-resistor
160 };
161 ina220@44 {
162 compatible = "
163 reg = <0x44>;
164 shunt-resistor
165 };
166 ina220@45 {
167 compatible = "
168 reg = <0x45>;
169 shunt-resistor
170 };
171 adt7461@4c {
172 compatible = "
173 reg = <0x4c>;
174 };
175 };
176
177 fman@400000 {
178 ethernet@e0000 {
179 phy-connection
180 };
181
182 ethernet@e2000 {
183 phy-connection
184 };
185
186 ethernet@e4000 {
187 phy-connection
188 };
189
190 ethernet@e6000 {
191 phy-connection
192 };
193
194 ethernet@e8000 {
195 phy-handle = <
196 phy-connection
197 };
198
199 ethernet@f0000 {
200 phy-handle = <
201 phy-connection
202 };
203 };
204
205 fman@500000 {
206 ethernet@e0000 {
207 phy-connection
208 };
209
210 ethernet@e2000 {
211 phy-connection
212 };
213
214 ethernet@e4000 {
215 phy-connection
216 };
217
218 ethernet@e6000 {
219 phy-connection
220 };
221
222 ethernet@e8000 {
223 phy-handle = <
224 phy-connection
225 };
226
227 ethernet@f0000 {
228 phy-handle = <
229 phy-connection
230 };
231 };
232 };
233
234 lbc: localbus@ffe124000 {
235 reg = <0xf 0xfe124000 0 0x1000
236 ranges = <0 0 0xf 0xe8000000 0
237 2 0 0xf 0xffa00000 0
238 3 0 0xf 0xffdf0000 0
239
240 flash@0,0 {
241 compatible = "cfi-flas
242 reg = <0 0 0x08000000>
243 bank-width = <2>;
244 device-width = <2>;
245 };
246
247 nand@2,0 {
248 #address-cells = <1>;
249 #size-cells = <1>;
250 compatible = "fsl,elbc
251 reg = <0x2 0x0 0x40000
252
253 partition@0 {
254 label = "NAND
255 reg = <0x0 0x0
256 };
257
258 partition@2000000 {
259 label = "NAND
260 reg = <0x02000
261 };
262
263 partition@12000000 {
264 label = "NAND
265 reg = <0x12000
266 };
267
268 partition@1a000000 {
269 label = "NAND
270 reg = <0x1a000
271 };
272
273 partition@1e000000 {
274 label = "NAND
275 reg = <0x1e000
276 };
277
278 partition@1f000000 {
279 label = "NAND
280 reg = <0x1f000
281 };
282 };
283
284 board-control@3,0 {
285 #address-cells = <1>;
286 #size-cells = <1>;
287 compatible = "fsl,p504
288 reg = <3 0 0x40>;
289 ranges = <0 3 0 0x40>;
290
291 mdio-mux-emi1 {
292 #address-cells
293 #size-cells =
294 compatible = "
295 mdio-parent-bu
296 reg = <9 1>;
297 mux-mask = <0x
298
299 hydra_rg:rgmii
300 #addre
301 #size-
302 reg =
303 status
304
305 phy_rg
306
307 };
308
309 phy_rg
310
311 };
312 };
313
314 hydra_sg_slot2
315 #addre
316 #size-
317 reg =
318 status
319
320 phy_sg
321
322 };
323
324 phy_sg
325
326 };
327
328 phy_sg
329
330 };
331
332 phy_sg
333
334 };
335 };
336
337 hydra_sg_slot3
338 #addre
339 #size-
340 reg =
341 status
342
343 phy_sg
344
345 };
346
347 phy_sg
348
349 };
350
351 phy_sg
352
353 };
354
355 phy_sg
356
357 };
358 };
359
360 hydra_sg_slot5
361 #addre
362 #size-
363 reg =
364 status
365
366 phy_sg
367
368 };
369
370 phy_sg
371
372 };
373
374 phy_sg
375
376 };
377
378 phy_sg
379
380 };
381 };
382 hydra_sg_slot6
383 #addre
384 #size-
385 reg =
386 status
387
388 phy_sg
389
390 };
391
392 phy_sg
393
394 };
395
396 phy_sg
397
398 };
399
400 phy_sg
401
402 };
403 };
404 };
405
406 mdio-mux-emi2 {
407 #address-cells
408 #size-cells =
409 compatible = "
410 mdio-parent-bu
411 reg = <9 1>;
412 mux-mask = <0x
413
414 hydra_xg_slot1
415 #addre
416 #size-
417 reg =
418 status
419
420 phy_xg
421
422
423 };
424 };
425
426 hydra_xg_slot2
427 #addre
428 #size-
429 reg =
430
431 phy_xg
432
433
434 };
435 };
436 };
437 };
438 };
439
440 pci0: pcie@ffe200000 {
441 reg = <0xf 0xfe200000 0 0x1000
442 ranges = <0x02000000 0 0xe0000
443 0x01000000 0 0x00000
444 pcie@0 {
445 ranges = <0x02000000 0
446 0x02000000 0
447 0 0x20000000
448
449 0x01000000 0
450 0x01000000 0
451 0 0x00010000
452 };
453 };
454
455 pci1: pcie@ffe201000 {
456 reg = <0xf 0xfe201000 0 0x1000
457 ranges = <0x02000000 0x0 0xe00
458 0x01000000 0x0 0x000
459 pcie@0 {
460 ranges = <0x02000000 0
461 0x02000000 0
462 0 0x20000000
463
464 0x01000000 0
465 0x01000000 0
466 0 0x00010000
467 };
468 };
469
470 pci2: pcie@ffe202000 {
471 reg = <0xf 0xfe202000 0 0x1000
472 ranges = <0x02000000 0 0xe0000
473 0x01000000 0 0x00000
474 pcie@0 {
475 ranges = <0x02000000 0
476 0x02000000 0
477 0 0x20000000
478
479 0x01000000 0
480 0x01000000 0
481 0 0x00010000
482 };
483 };
484 };
485
486 /include/ "p5040si-post.dtsi"
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