1 /* 1 /*
2 * P5040DS Device Tree Source 2 * P5040DS Device Tree Source
3 * 3 *
4 * Copyright 2012 - 2015 Freescale Semiconduct 4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that t 7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must r 8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and t 9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must r 10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and t 11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials 12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semicon 13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used 14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without sp 15 * derived from this software without specific prior written permission.
16 * 16 *
17 * 17 *
18 * ALTERNATIVELY, this software may be distrib 18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as publi 19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that Licens 20 * Foundation, either version 2 of that License or (at your option) any
21 * later version. 21 * later version.
22 * 22 *
23 * This software is provided by Freescale Semi 23 * This software is provided by Freescale Semiconductor "as is" and any
24 * express or implied warranties, including, b 24 * express or implied warranties, including, but not limited to, the implied
25 * warranties of merchantability and fitness f 25 * warranties of merchantability and fitness for a particular purpose are
26 * disclaimed. In no event shall Freescale Sem 26 * disclaimed. In no event shall Freescale Semiconductor be liable for any
27 * direct, indirect, incidental, special, exem 27 * direct, indirect, incidental, special, exemplary, or consequential damages
28 * (including, but not limited to, procurement 28 * (including, but not limited to, procurement of substitute goods or services;
29 * loss of use, data, or profits; or business 29 * loss of use, data, or profits; or business interruption) however caused and
30 * on any theory of liability, whether in cont 30 * on any theory of liability, whether in contract, strict liability, or tort
31 * (including negligence or otherwise) arising 31 * (including negligence or otherwise) arising in any way out of the use of this
32 * software, even if advised of the possibilit 32 * software, even if advised of the possibility of such damage.
33 */ 33 */
34 34
35 /include/ "p5040si-pre.dtsi" 35 /include/ "p5040si-pre.dtsi"
36 36
37 / { 37 / {
38 model = "fsl,P5040DS"; 38 model = "fsl,P5040DS";
39 compatible = "fsl,P5040DS"; 39 compatible = "fsl,P5040DS";
40 #address-cells = <2>; 40 #address-cells = <2>;
41 #size-cells = <2>; 41 #size-cells = <2>;
42 interrupt-parent = <&mpic>; 42 interrupt-parent = <&mpic>;
43 43
44 aliases { !! 44 aliases{
45 phy_sgmii_slot2_1c = &phy_sgmi 45 phy_sgmii_slot2_1c = &phy_sgmii_slot2_1c;
46 phy_sgmii_slot2_1d = &phy_sgmi 46 phy_sgmii_slot2_1d = &phy_sgmii_slot2_1d;
47 phy_sgmii_slot2_1e = &phy_sgmi 47 phy_sgmii_slot2_1e = &phy_sgmii_slot2_1e;
48 phy_sgmii_slot2_1f = &phy_sgmi 48 phy_sgmii_slot2_1f = &phy_sgmii_slot2_1f;
49 phy_sgmii_slot3_1c = &phy_sgmi 49 phy_sgmii_slot3_1c = &phy_sgmii_slot3_1c;
50 phy_sgmii_slot3_1d = &phy_sgmi 50 phy_sgmii_slot3_1d = &phy_sgmii_slot3_1d;
51 phy_sgmii_slot3_1e = &phy_sgmi 51 phy_sgmii_slot3_1e = &phy_sgmii_slot3_1e;
52 phy_sgmii_slot3_1f = &phy_sgmi 52 phy_sgmii_slot3_1f = &phy_sgmii_slot3_1f;
53 phy_sgmii_slot5_1c = &phy_sgmi 53 phy_sgmii_slot5_1c = &phy_sgmii_slot5_1c;
54 phy_sgmii_slot5_1d = &phy_sgmi 54 phy_sgmii_slot5_1d = &phy_sgmii_slot5_1d;
55 phy_sgmii_slot5_1e = &phy_sgmi 55 phy_sgmii_slot5_1e = &phy_sgmii_slot5_1e;
56 phy_sgmii_slot5_1f = &phy_sgmi 56 phy_sgmii_slot5_1f = &phy_sgmii_slot5_1f;
57 phy_sgmii_slot6_1c = &phy_sgmi 57 phy_sgmii_slot6_1c = &phy_sgmii_slot6_1c;
58 phy_sgmii_slot6_1d = &phy_sgmi 58 phy_sgmii_slot6_1d = &phy_sgmii_slot6_1d;
59 phy_sgmii_slot6_1e = &phy_sgmi 59 phy_sgmii_slot6_1e = &phy_sgmii_slot6_1e;
60 phy_sgmii_slot6_1f = &phy_sgmi 60 phy_sgmii_slot6_1f = &phy_sgmii_slot6_1f;
61 hydra_rg = &hydra_rg; 61 hydra_rg = &hydra_rg;
62 hydra_sg_slot2 = &hydra_sg_slo 62 hydra_sg_slot2 = &hydra_sg_slot2;
63 hydra_sg_slot3 = &hydra_sg_slo 63 hydra_sg_slot3 = &hydra_sg_slot3;
64 hydra_sg_slot5 = &hydra_sg_slo 64 hydra_sg_slot5 = &hydra_sg_slot5;
65 hydra_sg_slot6 = &hydra_sg_slo 65 hydra_sg_slot6 = &hydra_sg_slot6;
66 hydra_xg_slot1 = &hydra_xg_slo 66 hydra_xg_slot1 = &hydra_xg_slot1;
67 hydra_xg_slot2 = &hydra_xg_slo 67 hydra_xg_slot2 = &hydra_xg_slot2;
68 }; 68 };
69 69
70 memory { 70 memory {
71 device_type = "memory"; 71 device_type = "memory";
72 }; 72 };
73 73
74 reserved-memory { 74 reserved-memory {
75 #address-cells = <2>; 75 #address-cells = <2>;
76 #size-cells = <2>; 76 #size-cells = <2>;
77 ranges; 77 ranges;
78 78
79 bman_fbpr: bman-fbpr { 79 bman_fbpr: bman-fbpr {
80 size = <0 0x1000000>; 80 size = <0 0x1000000>;
81 alignment = <0 0x10000 81 alignment = <0 0x1000000>;
82 }; 82 };
83 qman_fqd: qman-fqd { 83 qman_fqd: qman-fqd {
84 size = <0 0x400000>; 84 size = <0 0x400000>;
85 alignment = <0 0x40000 85 alignment = <0 0x400000>;
86 }; 86 };
87 qman_pfdr: qman-pfdr { 87 qman_pfdr: qman-pfdr {
88 size = <0 0x2000000>; 88 size = <0 0x2000000>;
89 alignment = <0 0x20000 89 alignment = <0 0x2000000>;
90 }; 90 };
91 }; 91 };
92 92
93 dcsr: dcsr@f00000000 { 93 dcsr: dcsr@f00000000 {
94 ranges = <0x00000000 0xf 0x000 94 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
95 }; 95 };
96 96
97 bportals: bman-portals@ff4000000 { 97 bportals: bman-portals@ff4000000 {
98 ranges = <0x0 0xf 0xf4000000 0 98 ranges = <0x0 0xf 0xf4000000 0x200000>;
99 }; 99 };
100 100
101 qportals: qman-portals@ff4200000 { 101 qportals: qman-portals@ff4200000 {
102 ranges = <0x0 0xf 0xf4200000 0 102 ranges = <0x0 0xf 0xf4200000 0x200000>;
103 }; 103 };
104 104
105 soc: soc@ffe000000 { 105 soc: soc@ffe000000 {
106 ranges = <0x00000000 0xf 0xfe0 106 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
107 reg = <0xf 0xfe000000 0 0x0000 107 reg = <0xf 0xfe000000 0 0x00001000>;
108 spi@110000 { 108 spi@110000 {
109 flash@0 { 109 flash@0 {
110 #address-cells 110 #address-cells = <1>;
111 #size-cells = 111 #size-cells = <1>;
112 compatible = " 112 compatible = "spansion,s25sl12801", "jedec,spi-nor";
113 reg = <0>; 113 reg = <0>;
114 spi-max-freque 114 spi-max-frequency = <40000000>; /* input clock */
115 partition@u-bo 115 partition@u-boot {
116 label 116 label = "u-boot";
117 reg = 117 reg = <0x00000000 0x00100000>;
118 }; 118 };
119 partition@kern 119 partition@kernel {
120 label 120 label = "kernel";
121 reg = 121 reg = <0x00100000 0x00500000>;
122 }; 122 };
123 partition@dtb 123 partition@dtb {
124 label 124 label = "dtb";
125 reg = 125 reg = <0x00600000 0x00100000>;
126 }; 126 };
127 partition@fs { 127 partition@fs {
128 label 128 label = "file system";
129 reg = 129 reg = <0x00700000 0x00900000>;
130 }; 130 };
131 }; 131 };
132 }; 132 };
133 133
134 i2c@118100 { 134 i2c@118100 {
135 eeprom@51 { 135 eeprom@51 {
136 compatible = " 136 compatible = "atmel,24c256";
137 reg = <0x51>; 137 reg = <0x51>;
138 }; 138 };
139 eeprom@52 { 139 eeprom@52 {
140 compatible = " 140 compatible = "atmel,24c256";
141 reg = <0x52>; 141 reg = <0x52>;
142 }; 142 };
143 }; 143 };
144 144
145 i2c@119100 { 145 i2c@119100 {
146 rtc@68 { 146 rtc@68 {
147 compatible = " 147 compatible = "dallas,ds3232";
148 reg = <0x68>; 148 reg = <0x68>;
149 interrupts = < 149 interrupts = <0x1 0x1 0 0>;
150 }; 150 };
151 ina220@40 { 151 ina220@40 {
152 compatible = " 152 compatible = "ti,ina220";
153 reg = <0x40>; 153 reg = <0x40>;
154 shunt-resistor 154 shunt-resistor = <1000>;
155 }; 155 };
156 ina220@41 { 156 ina220@41 {
157 compatible = " 157 compatible = "ti,ina220";
158 reg = <0x41>; 158 reg = <0x41>;
159 shunt-resistor 159 shunt-resistor = <1000>;
160 }; 160 };
161 ina220@44 { 161 ina220@44 {
162 compatible = " 162 compatible = "ti,ina220";
163 reg = <0x44>; 163 reg = <0x44>;
164 shunt-resistor 164 shunt-resistor = <1000>;
165 }; 165 };
166 ina220@45 { 166 ina220@45 {
167 compatible = " 167 compatible = "ti,ina220";
168 reg = <0x45>; 168 reg = <0x45>;
169 shunt-resistor 169 shunt-resistor = <1000>;
170 }; 170 };
171 adt7461@4c { 171 adt7461@4c {
172 compatible = " 172 compatible = "adi,adt7461";
173 reg = <0x4c>; 173 reg = <0x4c>;
174 }; 174 };
175 }; 175 };
176 176
177 fman@400000 { 177 fman@400000 {
178 ethernet@e0000 { 178 ethernet@e0000 {
179 phy-connection 179 phy-connection-type = "sgmii";
180 }; 180 };
181 181
182 ethernet@e2000 { 182 ethernet@e2000 {
183 phy-connection 183 phy-connection-type = "sgmii";
184 }; 184 };
185 185
186 ethernet@e4000 { 186 ethernet@e4000 {
187 phy-connection 187 phy-connection-type = "sgmii";
188 }; 188 };
189 189
190 ethernet@e6000 { 190 ethernet@e6000 {
191 phy-connection 191 phy-connection-type = "sgmii";
192 }; 192 };
193 193
194 ethernet@e8000 { 194 ethernet@e8000 {
195 phy-handle = < 195 phy-handle = <&phy_rgmii_0>;
196 phy-connection 196 phy-connection-type = "rgmii";
197 }; 197 };
198 198
199 ethernet@f0000 { 199 ethernet@f0000 {
200 phy-handle = < 200 phy-handle = <&phy_xgmii_slot_2>;
201 phy-connection 201 phy-connection-type = "xgmii";
202 }; 202 };
203 }; 203 };
204 204
205 fman@500000 { 205 fman@500000 {
206 ethernet@e0000 { 206 ethernet@e0000 {
207 phy-connection 207 phy-connection-type = "sgmii";
208 }; 208 };
209 209
210 ethernet@e2000 { 210 ethernet@e2000 {
211 phy-connection 211 phy-connection-type = "sgmii";
212 }; 212 };
213 213
214 ethernet@e4000 { 214 ethernet@e4000 {
215 phy-connection 215 phy-connection-type = "sgmii";
216 }; 216 };
217 217
218 ethernet@e6000 { 218 ethernet@e6000 {
219 phy-connection 219 phy-connection-type = "sgmii";
220 }; 220 };
221 221
222 ethernet@e8000 { 222 ethernet@e8000 {
223 phy-handle = < 223 phy-handle = <&phy_rgmii_1>;
224 phy-connection 224 phy-connection-type = "rgmii";
225 }; 225 };
226 226
227 ethernet@f0000 { 227 ethernet@f0000 {
228 phy-handle = < 228 phy-handle = <&phy_xgmii_slot_1>;
229 phy-connection 229 phy-connection-type = "xgmii";
230 }; 230 };
231 }; 231 };
232 }; 232 };
233 233
234 lbc: localbus@ffe124000 { 234 lbc: localbus@ffe124000 {
235 reg = <0xf 0xfe124000 0 0x1000 235 reg = <0xf 0xfe124000 0 0x1000>;
236 ranges = <0 0 0xf 0xe8000000 0 236 ranges = <0 0 0xf 0xe8000000 0x08000000
237 2 0 0xf 0xffa00000 0 237 2 0 0xf 0xffa00000 0x00040000
238 3 0 0xf 0xffdf0000 0 238 3 0 0xf 0xffdf0000 0x00008000>;
239 239
240 flash@0,0 { 240 flash@0,0 {
241 compatible = "cfi-flas 241 compatible = "cfi-flash";
242 reg = <0 0 0x08000000> 242 reg = <0 0 0x08000000>;
243 bank-width = <2>; 243 bank-width = <2>;
244 device-width = <2>; 244 device-width = <2>;
245 }; 245 };
246 246
247 nand@2,0 { 247 nand@2,0 {
248 #address-cells = <1>; 248 #address-cells = <1>;
249 #size-cells = <1>; 249 #size-cells = <1>;
250 compatible = "fsl,elbc 250 compatible = "fsl,elbc-fcm-nand";
251 reg = <0x2 0x0 0x40000 251 reg = <0x2 0x0 0x40000>;
252 252
253 partition@0 { 253 partition@0 {
254 label = "NAND 254 label = "NAND U-Boot Image";
255 reg = <0x0 0x0 255 reg = <0x0 0x02000000>;
256 }; 256 };
257 257
258 partition@2000000 { 258 partition@2000000 {
259 label = "NAND 259 label = "NAND Root File System";
260 reg = <0x02000 260 reg = <0x02000000 0x10000000>;
261 }; 261 };
262 262
263 partition@12000000 { 263 partition@12000000 {
264 label = "NAND 264 label = "NAND Compressed RFS Image";
265 reg = <0x12000 265 reg = <0x12000000 0x08000000>;
266 }; 266 };
267 267
268 partition@1a000000 { 268 partition@1a000000 {
269 label = "NAND 269 label = "NAND Linux Kernel Image";
270 reg = <0x1a000 270 reg = <0x1a000000 0x04000000>;
271 }; 271 };
272 272
273 partition@1e000000 { 273 partition@1e000000 {
274 label = "NAND 274 label = "NAND DTB Image";
275 reg = <0x1e000 275 reg = <0x1e000000 0x01000000>;
276 }; 276 };
277 277
278 partition@1f000000 { 278 partition@1f000000 {
279 label = "NAND 279 label = "NAND Writable User area";
280 reg = <0x1f000 280 reg = <0x1f000000 0x01000000>;
281 }; 281 };
282 }; 282 };
283 283
284 board-control@3,0 { 284 board-control@3,0 {
285 #address-cells = <1>; 285 #address-cells = <1>;
286 #size-cells = <1>; 286 #size-cells = <1>;
287 compatible = "fsl,p504 287 compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
288 reg = <3 0 0x40>; 288 reg = <3 0 0x40>;
289 ranges = <0 3 0 0x40>; 289 ranges = <0 3 0 0x40>;
290 290
291 mdio-mux-emi1 { 291 mdio-mux-emi1 {
292 #address-cells 292 #address-cells = <1>;
293 #size-cells = 293 #size-cells = <0>;
294 compatible = " 294 compatible = "mdio-mux-mmioreg", "mdio-mux";
295 mdio-parent-bu 295 mdio-parent-bus = <&mdio0>;
296 reg = <9 1>; 296 reg = <9 1>;
297 mux-mask = <0x 297 mux-mask = <0x78>;
298 298
299 hydra_rg:rgmii 299 hydra_rg:rgmii-mdio@8 {
300 #addre 300 #address-cells = <1>;
301 #size- 301 #size-cells = <0>;
302 reg = 302 reg = <8>;
303 status 303 status = "disabled";
304 304
305 phy_rg 305 phy_rgmii_0: ethernet-phy@0 {
306 306 reg = <0x0>;
307 }; 307 };
308 308
309 phy_rg 309 phy_rgmii_1: ethernet-phy@1 {
310 310 reg = <0x1>;
311 }; 311 };
312 }; 312 };
313 313
314 hydra_sg_slot2 314 hydra_sg_slot2: sgmii-mdio@28 {
315 #addre 315 #address-cells = <1>;
316 #size- 316 #size-cells = <0>;
317 reg = 317 reg = <0x28>;
318 status 318 status = "disabled";
319 319
320 phy_sg 320 phy_sgmii_slot2_1c: ethernet-phy@1c {
321 321 reg = <0x1c>;
322 }; 322 };
323 323
324 phy_sg 324 phy_sgmii_slot2_1d: ethernet-phy@1d {
325 325 reg = <0x1d>;
326 }; 326 };
327 327
328 phy_sg 328 phy_sgmii_slot2_1e: ethernet-phy@1e {
329 329 reg = <0x1e>;
330 }; 330 };
331 331
332 phy_sg 332 phy_sgmii_slot2_1f: ethernet-phy@1f {
333 333 reg = <0x1f>;
334 }; 334 };
335 }; 335 };
336 336
337 hydra_sg_slot3 337 hydra_sg_slot3: sgmii-mdio@68 {
338 #addre 338 #address-cells = <1>;
339 #size- 339 #size-cells = <0>;
340 reg = 340 reg = <0x68>;
341 status 341 status = "disabled";
342 342
343 phy_sg 343 phy_sgmii_slot3_1c: ethernet-phy@1c {
344 344 reg = <0x1c>;
345 }; 345 };
346 346
347 phy_sg 347 phy_sgmii_slot3_1d: ethernet-phy@1d {
348 348 reg = <0x1d>;
349 }; 349 };
350 350
351 phy_sg 351 phy_sgmii_slot3_1e: ethernet-phy@1e {
352 352 reg = <0x1e>;
353 }; 353 };
354 354
355 phy_sg 355 phy_sgmii_slot3_1f: ethernet-phy@1f {
356 356 reg = <0x1f>;
357 }; 357 };
358 }; 358 };
359 359
360 hydra_sg_slot5 360 hydra_sg_slot5: sgmii-mdio@38 {
361 #addre 361 #address-cells = <1>;
362 #size- 362 #size-cells = <0>;
363 reg = 363 reg = <0x38>;
364 status 364 status = "disabled";
365 365
366 phy_sg 366 phy_sgmii_slot5_1c: ethernet-phy@1c {
367 367 reg = <0x1c>;
368 }; 368 };
369 369
370 phy_sg 370 phy_sgmii_slot5_1d: ethernet-phy@1d {
371 371 reg = <0x1d>;
372 }; 372 };
373 373
374 phy_sg 374 phy_sgmii_slot5_1e: ethernet-phy@1e {
375 375 reg = <0x1e>;
376 }; 376 };
377 377
378 phy_sg 378 phy_sgmii_slot5_1f: ethernet-phy@1f {
379 379 reg = <0x1f>;
380 }; 380 };
381 }; 381 };
382 hydra_sg_slot6 382 hydra_sg_slot6: sgmii-mdio@48 {
383 #addre 383 #address-cells = <1>;
384 #size- 384 #size-cells = <0>;
385 reg = 385 reg = <0x48>;
386 status 386 status = "disabled";
387 387
388 phy_sg 388 phy_sgmii_slot6_1c: ethernet-phy@1c {
389 389 reg = <0x1c>;
390 }; 390 };
391 391
392 phy_sg 392 phy_sgmii_slot6_1d: ethernet-phy@1d {
393 393 reg = <0x1d>;
394 }; 394 };
395 395
396 phy_sg 396 phy_sgmii_slot6_1e: ethernet-phy@1e {
397 397 reg = <0x1e>;
398 }; 398 };
399 399
400 phy_sg 400 phy_sgmii_slot6_1f: ethernet-phy@1f {
401 401 reg = <0x1f>;
402 }; 402 };
403 }; 403 };
404 }; 404 };
405 405
406 mdio-mux-emi2 { 406 mdio-mux-emi2 {
407 #address-cells 407 #address-cells = <1>;
408 #size-cells = 408 #size-cells = <0>;
409 compatible = " 409 compatible = "mdio-mux-mmioreg", "mdio-mux";
410 mdio-parent-bu 410 mdio-parent-bus = <&xmdio0>;
411 reg = <9 1>; 411 reg = <9 1>;
412 mux-mask = <0x 412 mux-mask = <0x06>;
413 413
414 hydra_xg_slot1 414 hydra_xg_slot1: hydra-xg-slot1@0 {
415 #addre 415 #address-cells = <1>;
416 #size- 416 #size-cells = <0>;
417 reg = 417 reg = <0>;
418 status 418 status = "disabled";
419 419
420 phy_xg 420 phy_xgmii_slot_1: ethernet-phy@0 {
421 421 compatible = "ethernet-phy-ieee802.3-c45";
422 422 reg = <4>;
423 }; 423 };
424 }; 424 };
425 425
426 hydra_xg_slot2 426 hydra_xg_slot2: hydra-xg-slot2@2 {
427 #addre 427 #address-cells = <1>;
428 #size- 428 #size-cells = <0>;
429 reg = 429 reg = <2>;
430 430
431 phy_xg 431 phy_xgmii_slot_2: ethernet-phy@4 {
432 432 compatible = "ethernet-phy-ieee802.3-c45";
433 433 reg = <0>;
434 }; 434 };
435 }; 435 };
436 }; 436 };
437 }; 437 };
438 }; 438 };
439 439
440 pci0: pcie@ffe200000 { 440 pci0: pcie@ffe200000 {
441 reg = <0xf 0xfe200000 0 0x1000 441 reg = <0xf 0xfe200000 0 0x1000>;
442 ranges = <0x02000000 0 0xe0000 442 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
443 0x01000000 0 0x00000 443 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
444 pcie@0 { 444 pcie@0 {
445 ranges = <0x02000000 0 445 ranges = <0x02000000 0 0xe0000000
446 0x02000000 0 446 0x02000000 0 0xe0000000
447 0 0x20000000 447 0 0x20000000
448 448
449 0x01000000 0 449 0x01000000 0 0x00000000
450 0x01000000 0 450 0x01000000 0 0x00000000
451 0 0x00010000 451 0 0x00010000>;
452 }; 452 };
453 }; 453 };
454 454
455 pci1: pcie@ffe201000 { 455 pci1: pcie@ffe201000 {
456 reg = <0xf 0xfe201000 0 0x1000 456 reg = <0xf 0xfe201000 0 0x1000>;
457 ranges = <0x02000000 0x0 0xe00 457 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
458 0x01000000 0x0 0x000 458 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
459 pcie@0 { 459 pcie@0 {
460 ranges = <0x02000000 0 460 ranges = <0x02000000 0 0xe0000000
461 0x02000000 0 461 0x02000000 0 0xe0000000
462 0 0x20000000 462 0 0x20000000
463 463
464 0x01000000 0 464 0x01000000 0 0x00000000
465 0x01000000 0 465 0x01000000 0 0x00000000
466 0 0x00010000 466 0 0x00010000>;
467 }; 467 };
468 }; 468 };
469 469
470 pci2: pcie@ffe202000 { 470 pci2: pcie@ffe202000 {
471 reg = <0xf 0xfe202000 0 0x1000 471 reg = <0xf 0xfe202000 0 0x1000>;
472 ranges = <0x02000000 0 0xe0000 472 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
473 0x01000000 0 0x00000 473 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
474 pcie@0 { 474 pcie@0 {
475 ranges = <0x02000000 0 475 ranges = <0x02000000 0 0xe0000000
476 0x02000000 0 476 0x02000000 0 0xe0000000
477 0 0x20000000 477 0 0x20000000
478 478
479 0x01000000 0 479 0x01000000 0 0x00000000
480 0x01000000 0 480 0x01000000 0 0x00000000
481 0 0x00010000 481 0 0x00010000>;
482 }; 482 };
483 }; 483 };
484 }; 484 };
485 485
486 /include/ "p5040si-post.dtsi" 486 /include/ "p5040si-post.dtsi"
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