1 /* 1 /* 2 * QorIQ FMan device tree stub [ controller @ 2 * QorIQ FMan device tree stub [ controller @ offset 0x400000 ] 3 * 3 * 4 * Copyright 2011 - 2015 Freescale Semiconduct 4 * Copyright 2011 - 2015 Freescale Semiconductor Inc. 5 * 5 * 6 * Redistribution and use in source and binary 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that t 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must r 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and t 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must r 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and t 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semicon 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without sp 15 * derived from this software without specific prior written permission. 16 * 16 * 17 * 17 * 18 * ALTERNATIVELY, this software may be distrib 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as publi 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that Licens 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 21 * later version. 22 * 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 33 */ 34 34 35 fman0: fman@400000 { 35 fman0: fman@400000 { 36 #address-cells = <1>; 36 #address-cells = <1>; 37 #size-cells = <1>; 37 #size-cells = <1>; 38 cell-index = <0>; 38 cell-index = <0>; 39 compatible = "fsl,fman"; 39 compatible = "fsl,fman"; 40 ranges = <0 0x400000 0xfe000>; 40 ranges = <0 0x400000 0xfe000>; 41 reg = <0x400000 0xfe000>; 41 reg = <0x400000 0xfe000>; 42 interrupts = <96 2 0 0>, <16 2 1 1>; 42 interrupts = <96 2 0 0>, <16 2 1 1>; 43 clocks = <&clockgen 3 0>; 43 clocks = <&clockgen 3 0>; 44 clock-names = "fmanclk"; 44 clock-names = "fmanclk"; 45 fsl,qman-channel-range = <0x40 0xc>; 45 fsl,qman-channel-range = <0x40 0xc>; 46 ptimer-handle = <&ptp_timer0>; 46 ptimer-handle = <&ptp_timer0>; 47 47 48 muram@0 { 48 muram@0 { 49 compatible = "fsl,fman-muram"; 49 compatible = "fsl,fman-muram"; 50 reg = <0x0 0x28000>; 50 reg = <0x0 0x28000>; 51 }; 51 }; 52 52 53 fman0_oh_0x1: port@81000 { 53 fman0_oh_0x1: port@81000 { 54 cell-index = <0x1>; 54 cell-index = <0x1>; 55 compatible = "fsl,fman-v2-port 55 compatible = "fsl,fman-v2-port-oh"; 56 reg = <0x81000 0x1000>; 56 reg = <0x81000 0x1000>; 57 }; 57 }; 58 58 59 fman0_oh_0x2: port@82000 { 59 fman0_oh_0x2: port@82000 { 60 cell-index = <0x2>; 60 cell-index = <0x2>; 61 compatible = "fsl,fman-v2-port 61 compatible = "fsl,fman-v2-port-oh"; 62 reg = <0x82000 0x1000>; 62 reg = <0x82000 0x1000>; 63 }; 63 }; 64 64 65 fman0_oh_0x3: port@83000 { 65 fman0_oh_0x3: port@83000 { 66 cell-index = <0x3>; 66 cell-index = <0x3>; 67 compatible = "fsl,fman-v2-port 67 compatible = "fsl,fman-v2-port-oh"; 68 reg = <0x83000 0x1000>; 68 reg = <0x83000 0x1000>; 69 }; 69 }; 70 70 71 fman0_oh_0x4: port@84000 { 71 fman0_oh_0x4: port@84000 { 72 cell-index = <0x4>; 72 cell-index = <0x4>; 73 compatible = "fsl,fman-v2-port 73 compatible = "fsl,fman-v2-port-oh"; 74 reg = <0x84000 0x1000>; 74 reg = <0x84000 0x1000>; 75 }; 75 }; 76 76 77 fman0_oh_0x5: port@85000 { 77 fman0_oh_0x5: port@85000 { 78 cell-index = <0x5>; 78 cell-index = <0x5>; 79 compatible = "fsl,fman-v2-port 79 compatible = "fsl,fman-v2-port-oh"; 80 reg = <0x85000 0x1000>; 80 reg = <0x85000 0x1000>; 81 status = "disabled"; 81 status = "disabled"; 82 }; 82 }; 83 83 84 fman0_oh_0x6: port@86000 { 84 fman0_oh_0x6: port@86000 { 85 cell-index = <0x6>; 85 cell-index = <0x6>; 86 compatible = "fsl,fman-v2-port 86 compatible = "fsl,fman-v2-port-oh"; 87 reg = <0x86000 0x1000>; 87 reg = <0x86000 0x1000>; 88 status = "disabled"; 88 status = "disabled"; 89 }; 89 }; 90 90 91 fman0_oh_0x7: port@87000 { 91 fman0_oh_0x7: port@87000 { 92 cell-index = <0x7>; 92 cell-index = <0x7>; 93 compatible = "fsl,fman-v2-port 93 compatible = "fsl,fman-v2-port-oh"; 94 reg = <0x87000 0x1000>; 94 reg = <0x87000 0x1000>; 95 status = "disabled"; 95 status = "disabled"; 96 }; 96 }; 97 }; 97 }; 98 98 99 ptp_timer0: ptp-timer@4fe000 { 99 ptp_timer0: ptp-timer@4fe000 { 100 compatible = "fsl,fman-ptp-timer"; 100 compatible = "fsl,fman-ptp-timer"; 101 reg = <0x4fe000 0x1000>; 101 reg = <0x4fe000 0x1000>; 102 interrupts = <96 2 0 0>; 102 interrupts = <96 2 0 0>; 103 clocks = <&clockgen 3 0>; 103 clocks = <&clockgen 3 0>; 104 }; 104 };
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