1 // SPDX-License-Identifier: BSD-3-Clause OR GP 1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later 2 /* 2 /* 3 * QorIQ FMan v3 10g port #2 device tree stub 3 * QorIQ FMan v3 10g port #2 device tree stub [ controller @ offset 0x400000 ] 4 * 4 * 5 * Copyright 2022 Sean Anderson <sean.anderson@ 5 * Copyright 2022 Sean Anderson <sean.anderson@seco.com> 6 * Copyright 2012 - 2015 Freescale Semiconduct 6 * Copyright 2012 - 2015 Freescale Semiconductor Inc. 7 */ 7 */ 8 8 9 fman@400000 { 9 fman@400000 { 10 fman0_rx_0x08: port@88000 { 10 fman0_rx_0x08: port@88000 { 11 cell-index = <0x8>; 11 cell-index = <0x8>; 12 compatible = "fsl,fman-v3-port 12 compatible = "fsl,fman-v3-port-rx"; 13 reg = <0x88000 0x1000>; 13 reg = <0x88000 0x1000>; 14 fsl,fman-10g-port; 14 fsl,fman-10g-port; 15 }; 15 }; 16 16 17 fman0_tx_0x28: port@a8000 { 17 fman0_tx_0x28: port@a8000 { 18 cell-index = <0x28>; 18 cell-index = <0x28>; 19 compatible = "fsl,fman-v3-port 19 compatible = "fsl,fman-v3-port-tx"; 20 reg = <0xa8000 0x1000>; 20 reg = <0xa8000 0x1000>; 21 fsl,fman-10g-port; 21 fsl,fman-10g-port; 22 }; 22 }; 23 23 24 ethernet@e0000 { 24 ethernet@e0000 { 25 cell-index = <0>; 25 cell-index = <0>; 26 compatible = "fsl,fman-memac"; 26 compatible = "fsl,fman-memac"; 27 reg = <0xe0000 0x1000>; 27 reg = <0xe0000 0x1000>; 28 fsl,fman-ports = <&fman0_rx_0x 28 fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>; 29 ptp-timer = <&ptp_timer0>; 29 ptp-timer = <&ptp_timer0>; 30 pcsphy-handle = <&pcsphy0>, <& 30 pcsphy-handle = <&pcsphy0>, <&pcsphy0>; 31 pcs-handle-names = "sgmii", "x 31 pcs-handle-names = "sgmii", "xfi"; 32 }; 32 }; 33 33 34 mdio@e1000 { 34 mdio@e1000 { 35 #address-cells = <1>; 35 #address-cells = <1>; 36 #size-cells = <0>; 36 #size-cells = <0>; 37 compatible = "fsl,fman-memac-m 37 compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; 38 reg = <0xe1000 0x1000>; 38 reg = <0xe1000 0x1000>; 39 fsl,erratum-a011043; /* must i 39 fsl,erratum-a011043; /* must ignore read errors */ 40 40 41 pcsphy0: ethernet-phy@0 { 41 pcsphy0: ethernet-phy@0 { 42 reg = <0x0>; 42 reg = <0x0>; 43 }; 43 }; 44 }; 44 }; 45 }; 45 };
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