1 /* 1 /*
2 * T1040D4RDB/T1042D4RDB Device Tree Source 2 * T1040D4RDB/T1042D4RDB Device Tree Source
3 * 3 *
4 * Copyright 2015 Freescale Semiconductor Inc. 4 * Copyright 2015 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that t 7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must r 8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and t 9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must r 10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and t 11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials 12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semicon 13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used 14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without sp 15 * derived from this software without specific prior written permission.
16 * 16 *
17 * 17 *
18 * ALTERNATIVELY, this software may be distrib 18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as publi 19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that Licens 20 * Foundation, either version 2 of that License or (at your option) any
21 * later version. 21 * later version.
22 * 22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35 / { 35 / {
36 reserved-memory { 36 reserved-memory {
37 #address-cells = <2>; 37 #address-cells = <2>;
38 #size-cells = <2>; 38 #size-cells = <2>;
39 ranges; 39 ranges;
40 40
41 bman_fbpr: bman-fbpr { 41 bman_fbpr: bman-fbpr {
42 size = <0 0x1000000>; 42 size = <0 0x1000000>;
43 alignment = <0 0x10000 43 alignment = <0 0x1000000>;
44 }; 44 };
45 qman_fqd: qman-fqd { 45 qman_fqd: qman-fqd {
46 size = <0 0x400000>; 46 size = <0 0x400000>;
47 alignment = <0 0x40000 47 alignment = <0 0x400000>;
48 }; 48 };
49 qman_pfdr: qman-pfdr { 49 qman_pfdr: qman-pfdr {
50 size = <0 0x2000000>; 50 size = <0 0x2000000>;
51 alignment = <0 0x20000 51 alignment = <0 0x2000000>;
52 }; 52 };
53 }; 53 };
54 54
55 ifc: localbus@ffe124000 { 55 ifc: localbus@ffe124000 {
56 reg = <0xf 0xfe124000 0 0x2000 56 reg = <0xf 0xfe124000 0 0x2000>;
57 ranges = <0 0 0xf 0xe8000000 0 57 ranges = <0 0 0xf 0xe8000000 0x08000000
58 2 0 0xf 0xff800000 0 58 2 0 0xf 0xff800000 0x00010000
59 3 0 0xf 0xffdf0000 0 59 3 0 0xf 0xffdf0000 0x00008000>;
60 60
61 nor@0,0 { 61 nor@0,0 {
62 #address-cells = <1>; 62 #address-cells = <1>;
63 #size-cells = <1>; 63 #size-cells = <1>;
64 compatible = "cfi-flas 64 compatible = "cfi-flash";
65 reg = <0x0 0x0 0x80000 65 reg = <0x0 0x0 0x8000000>;
66 bank-width = <2>; 66 bank-width = <2>;
67 device-width = <1>; 67 device-width = <1>;
68 }; 68 };
69 69
70 nand@2,0 { 70 nand@2,0 {
71 #address-cells = <1>; 71 #address-cells = <1>;
72 #size-cells = <1>; 72 #size-cells = <1>;
73 compatible = "fsl,ifc- 73 compatible = "fsl,ifc-nand";
74 reg = <0x2 0x0 0x10000 74 reg = <0x2 0x0 0x10000>;
75 }; 75 };
76 76
77 cpld@3,0 { 77 cpld@3,0 {
78 compatible = "fsl,t104 78 compatible = "fsl,t1040d4rdb-cpld";
79 reg = <3 0 0x300>; 79 reg = <3 0 0x300>;
80 }; 80 };
81 }; 81 };
82 82
83 memory { 83 memory {
84 device_type = "memory"; 84 device_type = "memory";
85 }; 85 };
86 86
87 dcsr: dcsr@f00000000 { 87 dcsr: dcsr@f00000000 {
88 ranges = <0x00000000 0xf 0x000 88 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
89 }; 89 };
90 90
91 bportals: bman-portals@ff4000000 { 91 bportals: bman-portals@ff4000000 {
92 ranges = <0x0 0xf 0xf4000000 0 92 ranges = <0x0 0xf 0xf4000000 0x2000000>;
93 }; 93 };
94 94
95 qportals: qman-portals@ff6000000 { 95 qportals: qman-portals@ff6000000 {
96 ranges = <0x0 0xf 0xf6000000 0 96 ranges = <0x0 0xf 0xf6000000 0x2000000>;
97 }; 97 };
98 98
99 soc: soc@ffe000000 { 99 soc: soc@ffe000000 {
100 ranges = <0x00000000 0xf 0xfe0 100 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
101 reg = <0xf 0xfe000000 0 0x0000 101 reg = <0xf 0xfe000000 0 0x00001000>;
102 102
103 spi@110000 { 103 spi@110000 {
104 flash@0 { 104 flash@0 {
105 #address-cells 105 #address-cells = <1>;
106 #size-cells = 106 #size-cells = <1>;
107 compatible = " 107 compatible = "micron,n25q512ax3", "jedec,spi-nor";
108 reg = <0>; 108 reg = <0>;
109 /* input clock 109 /* input clock */
110 spi-max-freque 110 spi-max-frequency = <10000000>;
111 }; 111 };
112 slic@1 { 112 slic@1 {
113 compatible = " 113 compatible = "maxim,ds26522";
114 reg = <1>; 114 reg = <1>;
115 spi-max-freque 115 spi-max-frequency = <2000000>; /* input clock */
116 }; 116 };
117 slic@2 { 117 slic@2 {
118 compatible = " 118 compatible = "maxim,ds26522";
119 reg = <2>; 119 reg = <2>;
120 spi-max-freque 120 spi-max-frequency = <2000000>; /* input clock */
121 }; 121 };
122 }; 122 };
123 i2c@118000 { 123 i2c@118000 {
124 hwmon@4c { 124 hwmon@4c {
125 compatible = " 125 compatible = "adi,adt7461";
126 reg = <0x4c>; 126 reg = <0x4c>;
127 }; 127 };
128 128
129 rtc@68 { 129 rtc@68 {
130 compatible = " 130 compatible = "dallas,ds1337";
131 reg = <0x68>; 131 reg = <0x68>;
132 interrupts = < 132 interrupts = <0x2 0x1 0 0>;
133 }; 133 };
134 }; 134 };
135 135
136 i2c@118100 { 136 i2c@118100 {
137 mux@77 { 137 mux@77 {
138 /* 138 /*
139 * Child nodes 139 * Child nodes of mux depend on which i2c
140 * devices are 140 * devices are connected via the mini PCI
141 * connector s 141 * connector slot1, the mini PCI connector
142 * slot2, the 142 * slot2, the HDMI connector, and the PEX
143 * slot. Syste 143 * slot. Systems with such devices attached
144 * should prov 144 * should provide a wrapper .dts file that
145 * includes th 145 * includes this one, and adds those nodes
146 */ 146 */
147 compatible = " 147 compatible = "nxp,pca9546";
148 reg = <0x77>; 148 reg = <0x77>;
149 #address-cells 149 #address-cells = <1>;
150 #size-cells = 150 #size-cells = <0>;
151 }; 151 };
152 }; 152 };
153 153
154 }; 154 };
155 155
156 pci0: pcie@ffe240000 { 156 pci0: pcie@ffe240000 {
157 reg = <0xf 0xfe240000 0 0x1000 157 reg = <0xf 0xfe240000 0 0x10000>;
158 ranges = <0x02000000 0 0xe0000 158 ranges = <0x02000000 0 0xe0000000 0xc 0x0 0x0 0x10000000
159 0x01000000 0 0x0 0xf 159 0x01000000 0 0x0 0xf 0xf8000000 0x0 0x00010000>;
160 pcie@0 { 160 pcie@0 {
161 ranges = <0x02000000 0 161 ranges = <0x02000000 0 0xe0000000
162 0x02000000 0 162 0x02000000 0 0xe0000000
163 0 0x10000000 163 0 0x10000000
164 164
165 0x01000000 0 165 0x01000000 0 0x00000000
166 0x01000000 0 166 0x01000000 0 0x00000000
167 0 0x00010000 167 0 0x00010000>;
168 }; 168 };
169 }; 169 };
170 170
171 pci1: pcie@ffe250000 { 171 pci1: pcie@ffe250000 {
172 reg = <0xf 0xfe250000 0 0x1000 172 reg = <0xf 0xfe250000 0 0x10000>;
173 ranges = <0x02000000 0 0xe0000 173 ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000
174 0x01000000 0 0 0xf 0 174 0x01000000 0 0 0xf 0xf8010000 0 0x00010000>;
175 pcie@0 { 175 pcie@0 {
176 ranges = <0x02000000 0 176 ranges = <0x02000000 0 0xe0000000
177 0x02000000 0 177 0x02000000 0 0xe0000000
178 0 0x10000000 178 0 0x10000000
179 179
180 0x01000000 0 180 0x01000000 0 0x00000000
181 0x01000000 0 181 0x01000000 0 0x00000000
182 0 0x00010000 182 0 0x00010000>;
183 }; 183 };
184 }; 184 };
185 185
186 pci2: pcie@ffe260000 { 186 pci2: pcie@ffe260000 {
187 reg = <0xf 0xfe260000 0 0x1000 187 reg = <0xf 0xfe260000 0 0x10000>;
188 ranges = <0x02000000 0 0xe0000 188 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
189 0x01000000 0 0x00000 189 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
190 pcie@0 { 190 pcie@0 {
191 ranges = <0x02000000 0 191 ranges = <0x02000000 0 0xe0000000
192 0x02000000 0 192 0x02000000 0 0xe0000000
193 0 0x10000000 193 0 0x10000000
194 194
195 0x01000000 0 195 0x01000000 0 0x00000000
196 0x01000000 0 196 0x01000000 0 0x00000000
197 0 0x00010000 197 0 0x00010000>;
198 }; 198 };
199 }; 199 };
200 200
201 pci3: pcie@ffe270000 { 201 pci3: pcie@ffe270000 {
202 reg = <0xf 0xfe270000 0 0x1000 202 reg = <0xf 0xfe270000 0 0x10000>;
203 ranges = <0x02000000 0 0xe0000 203 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
204 0x01000000 0 0x00000 204 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
205 pcie@0 { 205 pcie@0 {
206 ranges = <0x02000000 0 206 ranges = <0x02000000 0 0xe0000000
207 0x02000000 0 207 0x02000000 0 0xe0000000
208 0 0x10000000 208 0 0x10000000
209 209
210 0x01000000 0 210 0x01000000 0 0x00000000
211 0x01000000 0 211 0x01000000 0 0x00000000
212 0 0x00010000 212 0 0x00010000>;
213 }; 213 };
214 }; 214 };
215 215
216 qe: qe@ffe140000 { 216 qe: qe@ffe140000 {
217 ranges = <0x0 0xf 0xfe140000 0 217 ranges = <0x0 0xf 0xfe140000 0x40000>;
218 reg = <0xf 0xfe140000 0 0x480> 218 reg = <0xf 0xfe140000 0 0x480>;
219 brg-frequency = <0>; 219 brg-frequency = <0>;
220 bus-frequency = <0>; 220 bus-frequency = <0>;
221 221
222 si1: si@700 { 222 si1: si@700 {
223 compatible = "fsl,t104 223 compatible = "fsl,t1040-qe-si";
224 reg = <0x700 0x80>; 224 reg = <0x700 0x80>;
225 }; 225 };
226 226
227 siram1: siram@1000 { 227 siram1: siram@1000 {
228 compatible = "fsl,t104 228 compatible = "fsl,t1040-qe-siram";
229 reg = <0x1000 0x800>; 229 reg = <0x1000 0x800>;
230 }; 230 };
231 231
232 ucc_hdlc: ucc@2000 { 232 ucc_hdlc: ucc@2000 {
233 compatible = "fsl,ucc- 233 compatible = "fsl,ucc-hdlc";
234 rx-clock-name = "clk8" 234 rx-clock-name = "clk8";
235 tx-clock-name = "clk9" 235 tx-clock-name = "clk9";
236 fsl,rx-sync-clock = "r 236 fsl,rx-sync-clock = "rsync_pin";
237 fsl,tx-sync-clock = "t 237 fsl,tx-sync-clock = "tsync_pin";
238 fsl,tx-timeslot-mask = 238 fsl,tx-timeslot-mask = <0xfffffffe>;
239 fsl,rx-timeslot-mask = 239 fsl,rx-timeslot-mask = <0xfffffffe>;
240 fsl,tdm-framer-type = 240 fsl,tdm-framer-type = "e1";
241 fsl,tdm-id = <0>; 241 fsl,tdm-id = <0>;
242 fsl,siram-entry-id = < 242 fsl,siram-entry-id = <0>;
243 fsl,tdm-interface; 243 fsl,tdm-interface;
244 }; 244 };
245 245
246 ucc_serial: ucc@2200 { 246 ucc_serial: ucc@2200 {
247 compatible = "fsl,t104 247 compatible = "fsl,t1040-ucc-uart";
248 port-number = <0>; 248 port-number = <0>;
249 rx-clock-name = "brg2" 249 rx-clock-name = "brg2";
250 tx-clock-name = "brg2" 250 tx-clock-name = "brg2";
251 }; 251 };
252 }; 252 };
253 }; 253 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.