1 /*
2 * T1040/T1042 Silicon/SoC Device Tree Source
3 *
4 * Copyright 2013-2014 Freescale Semiconductor
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT
33 */
34
35 /dts-v1/;
36
37 /include/ "e5500_power_isa.dtsi"
38
39 / {
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 aliases {
45 ccsr = &soc;
46 dcsr = &dcsr;
47
48 serial0 = &serial0;
49 serial1 = &serial1;
50 serial2 = &serial2;
51 serial3 = &serial3;
52 pci0 = &pci0;
53 pci1 = &pci1;
54 pci2 = &pci2;
55 pci3 = &pci3;
56 usb0 = &usb0;
57 usb1 = &usb1;
58 sdhc = &sdhc;
59
60 crypto = &crypto;
61
62 fman0 = &fman0;
63 ethernet0 = &enet0;
64 ethernet1 = &enet1;
65 ethernet2 = &enet2;
66 ethernet3 = &enet3;
67 ethernet4 = &enet4;
68 };
69
70 cpus {
71 #address-cells = <1>;
72 #size-cells = <0>;
73
74 cpu0: PowerPC,e5500@0 {
75 device_type = "cpu";
76 reg = <0>;
77 clocks = <&clockgen 1
78 next-level-cache = <&L
79 #cooling-cells = <2>;
80 L2_1: l2-cache {
81 next-level-cac
82 };
83 };
84 cpu1: PowerPC,e5500@1 {
85 device_type = "cpu";
86 reg = <1>;
87 clocks = <&clockgen 1
88 next-level-cache = <&L
89 #cooling-cells = <2>;
90 L2_2: l2-cache {
91 next-level-cac
92 };
93 };
94 cpu2: PowerPC,e5500@2 {
95 device_type = "cpu";
96 reg = <2>;
97 clocks = <&clockgen 1
98 next-level-cache = <&L
99 #cooling-cells = <2>;
100 L2_3: l2-cache {
101 next-level-cac
102 };
103 };
104 cpu3: PowerPC,e5500@3 {
105 device_type = "cpu";
106 reg = <3>;
107 clocks = <&clockgen 1
108 next-level-cache = <&L
109 #cooling-cells = <2>;
110 L2_4: l2-cache {
111 next-level-cac
112 };
113 };
114 };
115 };
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