1 /* 1 /*
2 * T1040/T1042 Silicon/SoC Device Tree Source 2 * T1040/T1042 Silicon/SoC Device Tree Source (pre include)
3 * 3 *
4 * Copyright 2013-2014 Freescale Semiconductor 4 * Copyright 2013-2014 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that t 7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must r 8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and t 9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must r 10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and t 11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials 12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semicon 13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used 14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without sp 15 * derived from this software without specific prior written permission.
16 * 16 *
17 * 17 *
18 * ALTERNATIVELY, this software may be distrib 18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as publi 19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that Licens 20 * Foundation, either version 2 of that License or (at your option) any
21 * later version. 21 * later version.
22 * 22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35 /dts-v1/; 35 /dts-v1/;
36 36
37 /include/ "e5500_power_isa.dtsi" 37 /include/ "e5500_power_isa.dtsi"
38 38
39 / { 39 / {
40 #address-cells = <2>; 40 #address-cells = <2>;
41 #size-cells = <2>; 41 #size-cells = <2>;
42 interrupt-parent = <&mpic>; 42 interrupt-parent = <&mpic>;
43 43
44 aliases { 44 aliases {
45 ccsr = &soc; 45 ccsr = &soc;
46 dcsr = &dcsr; 46 dcsr = &dcsr;
47 47
48 serial0 = &serial0; 48 serial0 = &serial0;
49 serial1 = &serial1; 49 serial1 = &serial1;
50 serial2 = &serial2; 50 serial2 = &serial2;
51 serial3 = &serial3; 51 serial3 = &serial3;
52 pci0 = &pci0; 52 pci0 = &pci0;
53 pci1 = &pci1; 53 pci1 = &pci1;
54 pci2 = &pci2; 54 pci2 = &pci2;
55 pci3 = &pci3; 55 pci3 = &pci3;
56 usb0 = &usb0; 56 usb0 = &usb0;
57 usb1 = &usb1; 57 usb1 = &usb1;
58 sdhc = &sdhc; 58 sdhc = &sdhc;
59 59
60 crypto = &crypto; 60 crypto = &crypto;
61 61
62 fman0 = &fman0; 62 fman0 = &fman0;
63 ethernet0 = &enet0; 63 ethernet0 = &enet0;
64 ethernet1 = &enet1; 64 ethernet1 = &enet1;
65 ethernet2 = &enet2; 65 ethernet2 = &enet2;
66 ethernet3 = &enet3; 66 ethernet3 = &enet3;
67 ethernet4 = &enet4; 67 ethernet4 = &enet4;
68 }; 68 };
69 69
70 cpus { 70 cpus {
71 #address-cells = <1>; 71 #address-cells = <1>;
72 #size-cells = <0>; 72 #size-cells = <0>;
73 73
74 cpu0: PowerPC,e5500@0 { 74 cpu0: PowerPC,e5500@0 {
75 device_type = "cpu"; 75 device_type = "cpu";
76 reg = <0>; 76 reg = <0>;
77 clocks = <&clockgen 1 77 clocks = <&clockgen 1 0>;
78 next-level-cache = <&L 78 next-level-cache = <&L2_1>;
79 #cooling-cells = <2>; 79 #cooling-cells = <2>;
80 L2_1: l2-cache { 80 L2_1: l2-cache {
81 next-level-cac 81 next-level-cache = <&cpc>;
82 }; 82 };
83 }; 83 };
84 cpu1: PowerPC,e5500@1 { 84 cpu1: PowerPC,e5500@1 {
85 device_type = "cpu"; 85 device_type = "cpu";
86 reg = <1>; 86 reg = <1>;
87 clocks = <&clockgen 1 87 clocks = <&clockgen 1 1>;
88 next-level-cache = <&L 88 next-level-cache = <&L2_2>;
89 #cooling-cells = <2>; 89 #cooling-cells = <2>;
90 L2_2: l2-cache { 90 L2_2: l2-cache {
91 next-level-cac 91 next-level-cache = <&cpc>;
92 }; 92 };
93 }; 93 };
94 cpu2: PowerPC,e5500@2 { 94 cpu2: PowerPC,e5500@2 {
95 device_type = "cpu"; 95 device_type = "cpu";
96 reg = <2>; 96 reg = <2>;
97 clocks = <&clockgen 1 97 clocks = <&clockgen 1 2>;
98 next-level-cache = <&L 98 next-level-cache = <&L2_3>;
99 #cooling-cells = <2>; 99 #cooling-cells = <2>;
100 L2_3: l2-cache { 100 L2_3: l2-cache {
101 next-level-cac 101 next-level-cache = <&cpc>;
102 }; 102 };
103 }; 103 };
104 cpu3: PowerPC,e5500@3 { 104 cpu3: PowerPC,e5500@3 {
105 device_type = "cpu"; 105 device_type = "cpu";
106 reg = <3>; 106 reg = <3>;
107 clocks = <&clockgen 1 107 clocks = <&clockgen 1 3>;
108 next-level-cache = <&L 108 next-level-cache = <&L2_4>;
109 #cooling-cells = <2>; 109 #cooling-cells = <2>;
110 L2_4: l2-cache { 110 L2_4: l2-cache {
111 next-level-cac 111 next-level-cache = <&cpc>;
112 }; 112 };
113 }; 113 };
114 }; 114 };
115 }; 115 };
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