1 /* 1 /*
2 * T2081QDS Device Tree Source 2 * T2081QDS Device Tree Source
3 * 3 *
4 * Copyright 2013 - 2015 Freescale Semiconduct 4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that t 7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must r 8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and t 9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must r 10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and t 11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials 12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semicon 13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used 14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without sp 15 * derived from this software without specific prior written permission.
16 * 16 *
17 * 17 *
18 * ALTERNATIVELY, this software may be distrib 18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as publi 19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that Licens 20 * Foundation, either version 2 of that License or (at your option) any
21 * later version. 21 * later version.
22 * 22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35 /include/ "t208xsi-pre.dtsi" 35 /include/ "t208xsi-pre.dtsi"
36 /include/ "t208xqds.dtsi" 36 /include/ "t208xqds.dtsi"
37 37
38 / { 38 / {
39 model = "fsl,T2081QDS"; 39 model = "fsl,T2081QDS";
40 compatible = "fsl,T2081QDS"; 40 compatible = "fsl,T2081QDS";
41 #address-cells = <2>; 41 #address-cells = <2>;
42 #size-cells = <2>; 42 #size-cells = <2>;
43 interrupt-parent = <&mpic>; 43 interrupt-parent = <&mpic>;
44 44
45 aliases { 45 aliases {
46 emi1_slot1 = &t2081mdio2; 46 emi1_slot1 = &t2081mdio2;
47 emi1_slot2 = &t2081mdio3; 47 emi1_slot2 = &t2081mdio3;
48 emi1_slot3 = &t2081mdio4; 48 emi1_slot3 = &t2081mdio4;
49 emi1_slot5 = &t2081mdio5; 49 emi1_slot5 = &t2081mdio5;
50 emi1_slot6 = &t2081mdio6; 50 emi1_slot6 = &t2081mdio6;
51 emi1_slot7 = &t2081mdio7; 51 emi1_slot7 = &t2081mdio7;
52 }; 52 };
53 }; 53 };
54 54
55 &soc { 55 &soc {
56 fman@400000 { 56 fman@400000 {
57 ethernet@e0000 { 57 ethernet@e0000 {
58 phy-handle = <&phy_sgm 58 phy-handle = <&phy_sgmii_s7_1c>;
59 phy-connection-type = 59 phy-connection-type = "sgmii";
60 }; 60 };
61 61
62 ethernet@e2000 { 62 ethernet@e2000 {
63 phy-handle = <&phy_sgm 63 phy-handle = <&phy_sgmii_s7_1d>;
64 phy-connection-type = 64 phy-connection-type = "sgmii";
65 }; 65 };
66 66
67 ethernet@e4000 { 67 ethernet@e4000 {
68 phy-handle = <&rgmii_p 68 phy-handle = <&rgmii_phy1>;
69 phy-connection-type = 69 phy-connection-type = "rgmii";
70 }; 70 };
71 71
72 ethernet@e6000 { 72 ethernet@e6000 {
73 phy-handle = <&rgmii_p 73 phy-handle = <&rgmii_phy2>;
74 phy-connection-type = 74 phy-connection-type = "rgmii";
75 }; 75 };
76 76
77 ethernet@e8000 { 77 ethernet@e8000 {
78 phy-handle = <&phy_sgm 78 phy-handle = <&phy_sgmii_s3_1c>;
79 phy-connection-type = 79 phy-connection-type = "sgmii";
80 }; 80 };
81 81
82 ethernet@ea000 { 82 ethernet@ea000 {
83 phy-handle = <&phy_sgm 83 phy-handle = <&phy_sgmii_s7_1f>;
84 phy-connection-type = 84 phy-connection-type = "sgmii";
85 }; 85 };
86 86
87 ethernet@f0000 { 87 ethernet@f0000 {
88 phy-handle = <&phy_sgm 88 phy-handle = <&phy_sgmii_s2_1c>;
89 phy-connection-type = 89 phy-connection-type = "xgmii";
90 }; 90 };
91 91
92 ethernet@f2000 { 92 ethernet@f2000 {
93 phy-handle = <&phy_sgm 93 phy-handle = <&phy_sgmii_s7_1e>;
94 phy-connection-type = 94 phy-connection-type = "xgmii";
95 }; 95 };
96 }; 96 };
97 }; 97 };
98 98
99 &boardctrl { 99 &boardctrl {
100 mdio-mux-emi1 { 100 mdio-mux-emi1 {
101 compatible = "mdio-mux-mmioreg 101 compatible = "mdio-mux-mmioreg", "mdio-mux";
102 mdio-parent-bus = <&mdio0>; 102 mdio-parent-bus = <&mdio0>;
103 #address-cells = <1>; 103 #address-cells = <1>;
104 #size-cells = <0>; 104 #size-cells = <0>;
105 reg = <0x54 1>; 105 reg = <0x54 1>;
106 mux-mask = <0xe0>; 106 mux-mask = <0xe0>;
107 107
108 t2081mdio0: mdio@0 { 108 t2081mdio0: mdio@0 {
109 #address-cells = <1>; 109 #address-cells = <1>;
110 #size-cells = <0>; 110 #size-cells = <0>;
111 reg = <0>; 111 reg = <0>;
112 112
113 rgmii_phy1: ethernet-p 113 rgmii_phy1: ethernet-phy@1 {
114 reg = <0x1>; 114 reg = <0x1>;
115 }; 115 };
116 }; 116 };
117 117
118 t2081mdio1: mdio@20 { 118 t2081mdio1: mdio@20 {
119 #address-cells = <1>; 119 #address-cells = <1>;
120 #size-cells = <0>; 120 #size-cells = <0>;
121 reg = <0x20>; 121 reg = <0x20>;
122 122
123 rgmii_phy2: ethernet-p 123 rgmii_phy2: ethernet-phy@2 {
124 reg = <0x2>; 124 reg = <0x2>;
125 }; 125 };
126 }; 126 };
127 127
128 t2081mdio2: mdio@40 { 128 t2081mdio2: mdio@40 {
129 #address-cells = <1>; 129 #address-cells = <1>;
130 #size-cells = <0>; 130 #size-cells = <0>;
131 reg = <0x40>; 131 reg = <0x40>;
132 132
133 phy_sgmii_s1_1c: ether 133 phy_sgmii_s1_1c: ethernet-phy@1c {
134 reg = <0x1c>; 134 reg = <0x1c>;
135 }; 135 };
136 136
137 phy_sgmii_s1_1d: ether 137 phy_sgmii_s1_1d: ethernet-phy@1d {
138 reg = <0x1d>; 138 reg = <0x1d>;
139 }; 139 };
140 140
141 phy_sgmii_s1_1e: ether 141 phy_sgmii_s1_1e: ethernet-phy@1e {
142 reg = <0x1e>; 142 reg = <0x1e>;
143 }; 143 };
144 144
145 phy_sgmii_s1_1f: ether 145 phy_sgmii_s1_1f: ethernet-phy@1f {
146 reg = <0x1f>; 146 reg = <0x1f>;
147 }; 147 };
148 }; 148 };
149 149
150 t2081mdio3: mdio@60 { 150 t2081mdio3: mdio@60 {
151 #address-cells = <1>; 151 #address-cells = <1>;
152 #size-cells = <0>; 152 #size-cells = <0>;
153 reg = <0x60>; 153 reg = <0x60>;
154 154
155 phy_sgmii_s2_1c: ether 155 phy_sgmii_s2_1c: ethernet-phy@1c {
156 reg = <0x1c>; 156 reg = <0x1c>;
157 }; 157 };
158 158
159 phy_sgmii_s2_1d: ether 159 phy_sgmii_s2_1d: ethernet-phy@1d {
160 reg = <0x1d>; 160 reg = <0x1d>;
161 }; 161 };
162 162
163 phy_sgmii_s2_1e: ether 163 phy_sgmii_s2_1e: ethernet-phy@1e {
164 reg = <0x1e>; 164 reg = <0x1e>;
165 }; 165 };
166 166
167 phy_sgmii_s2_1f: ether 167 phy_sgmii_s2_1f: ethernet-phy@1f {
168 reg = <0x1f>; 168 reg = <0x1f>;
169 }; 169 };
170 }; 170 };
171 171
172 t2081mdio4: mdio@80 { 172 t2081mdio4: mdio@80 {
173 #address-cells = <1>; 173 #address-cells = <1>;
174 #size-cells = <0>; 174 #size-cells = <0>;
175 reg = <0x80>; 175 reg = <0x80>;
176 status = "disabled"; 176 status = "disabled";
177 177
178 phy_sgmii_s3_1c: ether 178 phy_sgmii_s3_1c: ethernet-phy@1c {
179 reg = <0x1c>; 179 reg = <0x1c>;
180 }; 180 };
181 181
182 phy_sgmii_s3_1d: ether 182 phy_sgmii_s3_1d: ethernet-phy@1d {
183 reg = <0x1d>; 183 reg = <0x1d>;
184 }; 184 };
185 185
186 phy_sgmii_s3_1e: ether 186 phy_sgmii_s3_1e: ethernet-phy@1e {
187 reg = <0x1e>; 187 reg = <0x1e>;
188 }; 188 };
189 189
190 phy_sgmii_s3_1f: ether 190 phy_sgmii_s3_1f: ethernet-phy@1f {
191 reg = <0x1f>; 191 reg = <0x1f>;
192 }; 192 };
193 }; 193 };
194 194
195 t2081mdio5: mdio@a0 { 195 t2081mdio5: mdio@a0 {
196 #address-cells = <1>; 196 #address-cells = <1>;
197 #size-cells = <0>; 197 #size-cells = <0>;
198 reg = <0xa0>; 198 reg = <0xa0>;
199 status = "disabled"; 199 status = "disabled";
200 200
201 phy_sgmii_s5_1c: ether 201 phy_sgmii_s5_1c: ethernet-phy@1c {
202 reg = <0x1c>; 202 reg = <0x1c>;
203 }; 203 };
204 204
205 phy_sgmii_s5_1d: ether 205 phy_sgmii_s5_1d: ethernet-phy@1d {
206 reg = <0x1d>; 206 reg = <0x1d>;
207 }; 207 };
208 208
209 phy_sgmii_s5_1e: ether 209 phy_sgmii_s5_1e: ethernet-phy@1e {
210 reg = <0x1e>; 210 reg = <0x1e>;
211 }; 211 };
212 212
213 phy_sgmii_s5_1f: ether 213 phy_sgmii_s5_1f: ethernet-phy@1f {
214 reg = <0x1f>; 214 reg = <0x1f>;
215 }; 215 };
216 }; 216 };
217 217
218 t2081mdio6: mdio@c0 { 218 t2081mdio6: mdio@c0 {
219 #address-cells = <1>; 219 #address-cells = <1>;
220 #size-cells = <0>; 220 #size-cells = <0>;
221 reg = <0xc0>; 221 reg = <0xc0>;
222 status = "disabled"; 222 status = "disabled";
223 223
224 phy_sgmii_s6_1c: ether 224 phy_sgmii_s6_1c: ethernet-phy@1c {
225 reg = <0x1c>; 225 reg = <0x1c>;
226 }; 226 };
227 227
228 phy_sgmii_s6_1d: ether 228 phy_sgmii_s6_1d: ethernet-phy@1d {
229 reg = <0x1d>; 229 reg = <0x1d>;
230 }; 230 };
231 231
232 phy_sgmii_s6_1e: ether 232 phy_sgmii_s6_1e: ethernet-phy@1e {
233 reg = <0x1e>; 233 reg = <0x1e>;
234 }; 234 };
235 235
236 phy_sgmii_s6_1f: ether 236 phy_sgmii_s6_1f: ethernet-phy@1f {
237 reg = <0x1f>; 237 reg = <0x1f>;
238 }; 238 };
239 }; 239 };
240 240
241 t2081mdio7: mdio@e0 { 241 t2081mdio7: mdio@e0 {
242 #address-cells = <1>; 242 #address-cells = <1>;
243 #size-cells = <0>; 243 #size-cells = <0>;
244 reg = <0xe0>; 244 reg = <0xe0>;
245 245
246 phy_sgmii_s7_1c: ether 246 phy_sgmii_s7_1c: ethernet-phy@1c {
247 reg = <0x1c>; 247 reg = <0x1c>;
248 }; 248 };
249 249
250 phy_sgmii_s7_1d: ether 250 phy_sgmii_s7_1d: ethernet-phy@1d {
251 reg = <0x1d>; 251 reg = <0x1d>;
252 }; 252 };
253 253
254 phy_sgmii_s7_1e: ether 254 phy_sgmii_s7_1e: ethernet-phy@1e {
255 reg = <0x1e>; 255 reg = <0x1e>;
256 }; 256 };
257 257
258 phy_sgmii_s7_1f: ether 258 phy_sgmii_s7_1f: ethernet-phy@1f {
259 reg = <0x1f>; 259 reg = <0x1f>;
260 }; 260 };
261 }; 261 };
262 }; 262 };
263 }; 263 };
264 264
265 /include/ "t2081si-post.dtsi" 265 /include/ "t2081si-post.dtsi"
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