1 /*
2 * T2080/T2081 QDS Device Tree Source
3 *
4 * Copyright 2013 - 2014 Freescale Semiconduct
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT
33 */
34
35 / {
36 model = "fsl,T2080QDS";
37 compatible = "fsl,T2080QDS";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 reserved-memory {
43 #address-cells = <2>;
44 #size-cells = <2>;
45 ranges;
46
47 bman_fbpr: bman-fbpr {
48 size = <0 0x1000000>;
49 alignment = <0 0x10000
50 };
51 qman_fqd: qman-fqd {
52 size = <0 0x400000>;
53 alignment = <0 0x40000
54 };
55 qman_pfdr: qman-pfdr {
56 size = <0 0x2000000>;
57 alignment = <0 0x20000
58 };
59 };
60
61 ifc: localbus@ffe124000 {
62 reg = <0xf 0xfe124000 0 0x2000
63 ranges = <0 0 0xf 0xe8000000 0
64 2 0 0xf 0xff800000 0
65 3 0 0xf 0xffdf0000 0
66
67 nor@0,0 {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "cfi-flas
71 reg = <0x0 0x0 0x80000
72 bank-width = <2>;
73 device-width = <1>;
74 };
75
76 nand@2,0 {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 compatible = "fsl,ifc-
80 reg = <0x2 0x0 0x10000
81 };
82
83 boardctrl: board-control@3,0 {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "fsl,fpga
87 reg = <3 0 0x300>;
88 ranges = <0 3 0 0x300>
89 };
90 };
91
92 memory {
93 device_type = "memory";
94 };
95
96 dcsr: dcsr@f00000000 {
97 ranges = <0x00000000 0xf 0x000
98 };
99
100 bportals: bman-portals@ff4000000 {
101 ranges = <0x0 0xf 0xf4000000 0
102 };
103
104 qportals: qman-portals@ff6000000 {
105 ranges = <0x0 0xf 0xf6000000 0
106 };
107
108 soc: soc@ffe000000 {
109 ranges = <0x00000000 0xf 0xfe0
110 reg = <0xf 0xfe000000 0 0x0000
111 spi@110000 {
112 flash@0 {
113 #address-cells
114 #size-cells =
115 compatible = "
116 reg = <0>;
117 spi-max-freque
118 };
119
120 flash@1 {
121 #address-cells
122 #size-cells =
123 compatible = "
124 reg = <1>;
125 spi-max-freque
126 };
127
128 flash@2 {
129 #address-cells
130 #size-cells =
131 compatible = "
132 reg = <2>;
133 spi-max-freque
134 };
135 };
136
137 i2c@118000 {
138 i2c-mux@77 {
139 compatible = "
140 reg = <0x77>;
141 #address-cells
142 #size-cells =
143
144 i2c@0 {
145 #addre
146 #size-
147 reg =
148
149 eeprom
150
151
152 };
153
154 eeprom
155
156
157 };
158
159 eeprom
160
161
162 };
163
164 rtc@68
165
166
167
168 };
169 };
170
171 i2c@1 {
172 #addre
173 #size-
174 reg =
175
176 eeprom
177
178
179 };
180 };
181
182 i2c@2 {
183 #addre
184 #size-
185 reg =
186
187 ina220
188
189
190
191 };
192
193 ina220
194
195
196
197 };
198 };
199
200 i2c@3 {
201 #addre
202 #size-
203 reg =
204
205 adt746
206
207
208 };
209 };
210 };
211 };
212
213 sdhc@114000 {
214 voltage-ranges = <1800
215 };
216 };
217
218 pci0: pcie@ffe240000 {
219 reg = <0xf 0xfe240000 0 0x1000
220 ranges = <0x02000000 0 0xe0000
221 0x01000000 0 0x00000
222 pcie@0 {
223 ranges = <0x02000000 0
224 0x02000000 0
225 0 0x20000000
226
227 0x01000000 0
228 0x01000000 0
229 0 0x00010000
230 };
231 };
232
233 pci1: pcie@ffe250000 {
234 reg = <0xf 0xfe250000 0 0x1000
235 ranges = <0x02000000 0x0 0xe00
236 0x01000000 0x0 0x000
237 pcie@0 {
238 ranges = <0x02000000 0
239 0x02000000 0
240 0 0x20000000
241
242 0x01000000 0
243 0x01000000 0
244 0 0x00010000
245 };
246 };
247
248 pci2: pcie@ffe260000 {
249 reg = <0xf 0xfe260000 0 0x1000
250 ranges = <0x02000000 0 0xe0000
251 0x01000000 0 0x00000
252 pcie@0 {
253 ranges = <0x02000000 0
254 0x02000000 0
255 0 0x20000000
256
257 0x01000000 0
258 0x01000000 0
259 0 0x00010000
260 };
261 };
262
263 pci3: pcie@ffe270000 {
264 reg = <0xf 0xfe270000 0 0x1000
265 ranges = <0x02000000 0 0xe0000
266 0x01000000 0 0x00000
267 pcie@0 {
268 ranges = <0x02000000 0
269 0x02000000 0
270 0 0x20000000
271
272 0x01000000 0
273 0x01000000 0
274 0 0x00010000
275 };
276 };
277 };
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