1 /* 1 /*
2 * T2080/T2081 QDS Device Tree Source 2 * T2080/T2081 QDS Device Tree Source
3 * 3 *
4 * Copyright 2013 - 2014 Freescale Semiconduct 4 * Copyright 2013 - 2014 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that t 7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must r 8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and t 9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must r 10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and t 11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials 12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semicon 13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used 14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without sp 15 * derived from this software without specific prior written permission.
16 * 16 *
17 * 17 *
18 * ALTERNATIVELY, this software may be distrib 18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as publi 19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that Licens 20 * Foundation, either version 2 of that License or (at your option) any
21 * later version. 21 * later version.
22 * 22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35 / { 35 / {
36 model = "fsl,T2080QDS"; 36 model = "fsl,T2080QDS";
37 compatible = "fsl,T2080QDS"; 37 compatible = "fsl,T2080QDS";
38 #address-cells = <2>; 38 #address-cells = <2>;
39 #size-cells = <2>; 39 #size-cells = <2>;
40 interrupt-parent = <&mpic>; 40 interrupt-parent = <&mpic>;
41 41
42 reserved-memory { 42 reserved-memory {
43 #address-cells = <2>; 43 #address-cells = <2>;
44 #size-cells = <2>; 44 #size-cells = <2>;
45 ranges; 45 ranges;
46 46
47 bman_fbpr: bman-fbpr { 47 bman_fbpr: bman-fbpr {
48 size = <0 0x1000000>; 48 size = <0 0x1000000>;
49 alignment = <0 0x10000 49 alignment = <0 0x1000000>;
50 }; 50 };
51 qman_fqd: qman-fqd { 51 qman_fqd: qman-fqd {
52 size = <0 0x400000>; 52 size = <0 0x400000>;
53 alignment = <0 0x40000 53 alignment = <0 0x400000>;
54 }; 54 };
55 qman_pfdr: qman-pfdr { 55 qman_pfdr: qman-pfdr {
56 size = <0 0x2000000>; 56 size = <0 0x2000000>;
57 alignment = <0 0x20000 57 alignment = <0 0x2000000>;
58 }; 58 };
59 }; 59 };
60 60
61 ifc: localbus@ffe124000 { 61 ifc: localbus@ffe124000 {
62 reg = <0xf 0xfe124000 0 0x2000 62 reg = <0xf 0xfe124000 0 0x2000>;
63 ranges = <0 0 0xf 0xe8000000 0 63 ranges = <0 0 0xf 0xe8000000 0x08000000
64 2 0 0xf 0xff800000 0 64 2 0 0xf 0xff800000 0x00010000
65 3 0 0xf 0xffdf0000 0 65 3 0 0xf 0xffdf0000 0x00008000>;
66 66
67 nor@0,0 { 67 nor@0,0 {
68 #address-cells = <1>; 68 #address-cells = <1>;
69 #size-cells = <1>; 69 #size-cells = <1>;
70 compatible = "cfi-flas 70 compatible = "cfi-flash";
71 reg = <0x0 0x0 0x80000 71 reg = <0x0 0x0 0x8000000>;
72 bank-width = <2>; 72 bank-width = <2>;
73 device-width = <1>; 73 device-width = <1>;
74 }; 74 };
75 75
76 nand@2,0 { 76 nand@2,0 {
77 #address-cells = <1>; 77 #address-cells = <1>;
78 #size-cells = <1>; 78 #size-cells = <1>;
79 compatible = "fsl,ifc- 79 compatible = "fsl,ifc-nand";
80 reg = <0x2 0x0 0x10000 80 reg = <0x2 0x0 0x10000>;
81 }; 81 };
82 82
83 boardctrl: board-control@3,0 { 83 boardctrl: board-control@3,0 {
84 #address-cells = <1>; 84 #address-cells = <1>;
85 #size-cells = <1>; 85 #size-cells = <1>;
86 compatible = "fsl,fpga 86 compatible = "fsl,fpga-qixis";
87 reg = <3 0 0x300>; 87 reg = <3 0 0x300>;
88 ranges = <0 3 0 0x300> 88 ranges = <0 3 0 0x300>;
89 }; 89 };
90 }; 90 };
91 91
92 memory { 92 memory {
93 device_type = "memory"; 93 device_type = "memory";
94 }; 94 };
95 95
96 dcsr: dcsr@f00000000 { 96 dcsr: dcsr@f00000000 {
97 ranges = <0x00000000 0xf 0x000 97 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
98 }; 98 };
99 99
100 bportals: bman-portals@ff4000000 { 100 bportals: bman-portals@ff4000000 {
101 ranges = <0x0 0xf 0xf4000000 0 101 ranges = <0x0 0xf 0xf4000000 0x2000000>;
102 }; 102 };
103 103
104 qportals: qman-portals@ff6000000 { 104 qportals: qman-portals@ff6000000 {
105 ranges = <0x0 0xf 0xf6000000 0 105 ranges = <0x0 0xf 0xf6000000 0x2000000>;
106 }; 106 };
107 107
108 soc: soc@ffe000000 { 108 soc: soc@ffe000000 {
109 ranges = <0x00000000 0xf 0xfe0 109 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
110 reg = <0xf 0xfe000000 0 0x0000 110 reg = <0xf 0xfe000000 0 0x00001000>;
111 spi@110000 { 111 spi@110000 {
112 flash@0 { 112 flash@0 {
113 #address-cells 113 #address-cells = <1>;
114 #size-cells = 114 #size-cells = <1>;
115 compatible = " 115 compatible = "micron,n25q128a11", "jedec,spi-nor"; /* 16MB */
116 reg = <0>; 116 reg = <0>;
117 spi-max-freque 117 spi-max-frequency = <40000000>; /* input clock */
118 }; 118 };
119 119
120 flash@1 { 120 flash@1 {
121 #address-cells 121 #address-cells = <1>;
122 #size-cells = 122 #size-cells = <1>;
123 compatible = " 123 compatible = "sst,sst25wf040", "jedec,spi-nor";
124 reg = <1>; 124 reg = <1>;
125 spi-max-freque 125 spi-max-frequency = <35000000>;
126 }; 126 };
127 127
128 flash@2 { 128 flash@2 {
129 #address-cells 129 #address-cells = <1>;
130 #size-cells = 130 #size-cells = <1>;
131 compatible = " 131 compatible = "eon,en25s64", "jedec,spi-nor";
132 reg = <2>; 132 reg = <2>;
133 spi-max-freque 133 spi-max-frequency = <35000000>;
134 }; 134 };
135 }; 135 };
136 136
137 i2c@118000 { 137 i2c@118000 {
138 i2c-mux@77 { 138 i2c-mux@77 {
139 compatible = " 139 compatible = "nxp,pca9547";
140 reg = <0x77>; 140 reg = <0x77>;
141 #address-cells 141 #address-cells = <1>;
142 #size-cells = 142 #size-cells = <0>;
143 143
144 i2c@0 { 144 i2c@0 {
145 #addre 145 #address-cells = <1>;
146 #size- 146 #size-cells = <0>;
147 reg = 147 reg = <0x0>;
148 148
149 eeprom 149 eeprom@50 {
150 150 compatible = "atmel,24c512";
151 151 reg = <0x50>;
152 }; 152 };
153 153
154 eeprom 154 eeprom@51 {
155 155 compatible = "atmel,24c02";
156 156 reg = <0x51>;
157 }; 157 };
158 158
159 eeprom 159 eeprom@57 {
160 160 compatible = "atmel,24c02";
161 161 reg = <0x57>;
162 }; 162 };
163 163
164 rtc@68 164 rtc@68 {
165 165 compatible = "dallas,ds3232";
166 166 reg = <0x68>;
167 167 interrupts = <0xb 0x1 0 0>;
168 }; 168 };
169 }; 169 };
170 170
171 i2c@1 { 171 i2c@1 {
172 #addre 172 #address-cells = <1>;
173 #size- 173 #size-cells = <0>;
174 reg = 174 reg = <0x1>;
175 175
176 eeprom 176 eeprom@55 {
177 177 compatible = "atmel,24c02";
178 178 reg = <0x55>;
179 }; 179 };
180 }; 180 };
181 181
182 i2c@2 { 182 i2c@2 {
183 #addre 183 #address-cells = <1>;
184 #size- 184 #size-cells = <0>;
185 reg = 185 reg = <0x2>;
186 186
187 ina220 187 ina220@40 {
188 188 compatible = "ti,ina220";
189 189 reg = <0x40>;
190 190 shunt-resistor = <1000>;
191 }; 191 };
192 192
193 ina220 193 ina220@41 {
194 194 compatible = "ti,ina220";
195 195 reg = <0x41>;
196 196 shunt-resistor = <1000>;
197 }; 197 };
198 }; 198 };
199 199
200 i2c@3 { 200 i2c@3 {
201 #addre 201 #address-cells = <1>;
202 #size- 202 #size-cells = <0>;
203 reg = 203 reg = <0x3>;
204 204
205 adt746 205 adt7461@4c {
206 206 compatible = "adi,adt7461";
207 207 reg = <0x4c>;
208 }; 208 };
209 }; 209 };
210 }; 210 };
211 }; 211 };
212 212
213 sdhc@114000 { 213 sdhc@114000 {
214 voltage-ranges = <1800 214 voltage-ranges = <1800 1800 3300 3300>;
215 }; 215 };
216 }; 216 };
217 217
218 pci0: pcie@ffe240000 { 218 pci0: pcie@ffe240000 {
219 reg = <0xf 0xfe240000 0 0x1000 219 reg = <0xf 0xfe240000 0 0x10000>;
220 ranges = <0x02000000 0 0xe0000 220 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
221 0x01000000 0 0x00000 221 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
222 pcie@0 { 222 pcie@0 {
223 ranges = <0x02000000 0 223 ranges = <0x02000000 0 0xe0000000
224 0x02000000 0 224 0x02000000 0 0xe0000000
225 0 0x20000000 225 0 0x20000000
226 226
227 0x01000000 0 227 0x01000000 0 0x00000000
228 0x01000000 0 228 0x01000000 0 0x00000000
229 0 0x00010000 229 0 0x00010000>;
230 }; 230 };
231 }; 231 };
232 232
233 pci1: pcie@ffe250000 { 233 pci1: pcie@ffe250000 {
234 reg = <0xf 0xfe250000 0 0x1000 234 reg = <0xf 0xfe250000 0 0x10000>;
235 ranges = <0x02000000 0x0 0xe00 235 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000
236 0x01000000 0x0 0x000 236 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
237 pcie@0 { 237 pcie@0 {
238 ranges = <0x02000000 0 238 ranges = <0x02000000 0 0xe0000000
239 0x02000000 0 239 0x02000000 0 0xe0000000
240 0 0x20000000 240 0 0x20000000
241 241
242 0x01000000 0 242 0x01000000 0 0x00000000
243 0x01000000 0 243 0x01000000 0 0x00000000
244 0 0x00010000 244 0 0x00010000>;
245 }; 245 };
246 }; 246 };
247 247
248 pci2: pcie@ffe260000 { 248 pci2: pcie@ffe260000 {
249 reg = <0xf 0xfe260000 0 0x1000 249 reg = <0xf 0xfe260000 0 0x1000>;
250 ranges = <0x02000000 0 0xe0000 250 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
251 0x01000000 0 0x00000 251 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
252 pcie@0 { 252 pcie@0 {
253 ranges = <0x02000000 0 253 ranges = <0x02000000 0 0xe0000000
254 0x02000000 0 254 0x02000000 0 0xe0000000
255 0 0x20000000 255 0 0x20000000
256 256
257 0x01000000 0 257 0x01000000 0 0x00000000
258 0x01000000 0 258 0x01000000 0 0x00000000
259 0 0x00010000 259 0 0x00010000>;
260 }; 260 };
261 }; 261 };
262 262
263 pci3: pcie@ffe270000 { 263 pci3: pcie@ffe270000 {
264 reg = <0xf 0xfe270000 0 0x1000 264 reg = <0xf 0xfe270000 0 0x10000>;
265 ranges = <0x02000000 0 0xe0000 265 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x10000000
266 0x01000000 0 0x00000 266 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
267 pcie@0 { 267 pcie@0 {
268 ranges = <0x02000000 0 268 ranges = <0x02000000 0 0xe0000000
269 0x02000000 0 269 0x02000000 0 0xe0000000
270 0 0x20000000 270 0 0x20000000
271 271
272 0x01000000 0 272 0x01000000 0 0x00000000
273 0x01000000 0 273 0x01000000 0 0x00000000
274 0 0x00010000 274 0 0x00010000>;
275 }; 275 };
276 }; 276 };
277 }; 277 };
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