1 /* 1 /*
2 * T4240RDB Device Tree Source 2 * T4240RDB Device Tree Source
3 * 3 *
4 * Copyright 2014 - 2015 Freescale Semiconduct 4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that t 7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must r 8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and t 9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must r 10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and t 11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials 12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semicon 13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used 14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without sp 15 * derived from this software without specific prior written permission.
16 * 16 *
17 * 17 *
18 * ALTERNATIVELY, this software may be distrib 18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as publi 19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that Licens 20 * Foundation, either version 2 of that License or (at your option) any
21 * later version. 21 * later version.
22 * 22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35 /include/ "t4240si-pre.dtsi" 35 /include/ "t4240si-pre.dtsi"
36 36
37 / { 37 / {
38 model = "fsl,T4240RDB"; 38 model = "fsl,T4240RDB";
39 compatible = "fsl,T4240RDB"; 39 compatible = "fsl,T4240RDB";
40 #address-cells = <2>; 40 #address-cells = <2>;
41 #size-cells = <2>; 41 #size-cells = <2>;
42 interrupt-parent = <&mpic>; 42 interrupt-parent = <&mpic>;
43 43
44 aliases { 44 aliases {
45 sgmii_phy21 = &sgmiiphy21; 45 sgmii_phy21 = &sgmiiphy21;
46 sgmii_phy22 = &sgmiiphy22; 46 sgmii_phy22 = &sgmiiphy22;
47 sgmii_phy23 = &sgmiiphy23; 47 sgmii_phy23 = &sgmiiphy23;
48 sgmii_phy24 = &sgmiiphy24; 48 sgmii_phy24 = &sgmiiphy24;
49 sgmii_phy41 = &sgmiiphy41; 49 sgmii_phy41 = &sgmiiphy41;
50 sgmii_phy42 = &sgmiiphy42; 50 sgmii_phy42 = &sgmiiphy42;
51 sgmii_phy43 = &sgmiiphy43; 51 sgmii_phy43 = &sgmiiphy43;
52 sgmii_phy44 = &sgmiiphy44; 52 sgmii_phy44 = &sgmiiphy44;
53 }; 53 };
54 54
55 ifc: localbus@ffe124000 { 55 ifc: localbus@ffe124000 {
56 reg = <0xf 0xfe124000 0 0x2000 56 reg = <0xf 0xfe124000 0 0x2000>;
57 ranges = <0 0 0xf 0xe8000000 0 57 ranges = <0 0 0xf 0xe8000000 0x08000000
58 2 0 0xf 0xff800000 0 58 2 0 0xf 0xff800000 0x00010000
59 3 0 0xf 0xffdf0000 0 59 3 0 0xf 0xffdf0000 0x00008000>;
60 60
61 nor@0,0 { 61 nor@0,0 {
62 #address-cells = <1>; 62 #address-cells = <1>;
63 #size-cells = <1>; 63 #size-cells = <1>;
64 compatible = "cfi-flas 64 compatible = "cfi-flash";
65 reg = <0x0 0x0 0x80000 65 reg = <0x0 0x0 0x8000000>;
66 66
67 bank-width = <2>; 67 bank-width = <2>;
68 device-width = <1>; 68 device-width = <1>;
69 }; 69 };
70 70
71 nand@2,0 { 71 nand@2,0 {
72 #address-cells = <1>; 72 #address-cells = <1>;
73 #size-cells = <1>; 73 #size-cells = <1>;
74 compatible = "fsl,ifc- 74 compatible = "fsl,ifc-nand";
75 reg = <0x2 0x0 0x10000 75 reg = <0x2 0x0 0x10000>;
76 }; 76 };
77 }; 77 };
78 78
79 memory { 79 memory {
80 device_type = "memory"; 80 device_type = "memory";
81 }; 81 };
82 82
83 reserved-memory { 83 reserved-memory {
84 #address-cells = <2>; 84 #address-cells = <2>;
85 #size-cells = <2>; 85 #size-cells = <2>;
86 ranges; 86 ranges;
87 87
88 bman_fbpr: bman-fbpr { 88 bman_fbpr: bman-fbpr {
89 size = <0 0x1000000>; 89 size = <0 0x1000000>;
90 alignment = <0 0x10000 90 alignment = <0 0x1000000>;
91 }; 91 };
92 qman_fqd: qman-fqd { 92 qman_fqd: qman-fqd {
93 size = <0 0x400000>; 93 size = <0 0x400000>;
94 alignment = <0 0x40000 94 alignment = <0 0x400000>;
95 }; 95 };
96 qman_pfdr: qman-pfdr { 96 qman_pfdr: qman-pfdr {
97 size = <0 0x2000000>; 97 size = <0 0x2000000>;
98 alignment = <0 0x20000 98 alignment = <0 0x2000000>;
99 }; 99 };
100 }; 100 };
101 101
102 dcsr: dcsr@f00000000 { 102 dcsr: dcsr@f00000000 {
103 ranges = <0x00000000 0xf 0x000 103 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
104 }; 104 };
105 105
106 bportals: bman-portals@ff4000000 { 106 bportals: bman-portals@ff4000000 {
107 ranges = <0x0 0xf 0xf4000000 0 107 ranges = <0x0 0xf 0xf4000000 0x2000000>;
108 }; 108 };
109 109
110 qportals: qman-portals@ff6000000 { 110 qportals: qman-portals@ff6000000 {
111 ranges = <0x0 0xf 0xf6000000 0 111 ranges = <0x0 0xf 0xf6000000 0x2000000>;
112 }; 112 };
113 113
114 soc: soc@ffe000000 { 114 soc: soc@ffe000000 {
115 ranges = <0x00000000 0xf 0xfe0 115 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
116 reg = <0xf 0xfe000000 0 0x0000 116 reg = <0xf 0xfe000000 0 0x00001000>;
117 spi@110000 { 117 spi@110000 {
118 flash@0 { 118 flash@0 {
119 #address-cells 119 #address-cells = <1>;
120 #size-cells = 120 #size-cells = <1>;
121 compatible = " 121 compatible = "sst,sst25wf040", "jedec,spi-nor";
122 reg = <0>; 122 reg = <0>;
123 spi-max-freque 123 spi-max-frequency = <40000000>; /* input clock */
124 }; 124 };
125 }; 125 };
126 126
127 i2c@118000 { 127 i2c@118000 {
128 hwmon@2f { 128 hwmon@2f {
129 compatible = " 129 compatible = "winbond,w83793";
130 reg = <0x2f>; 130 reg = <0x2f>;
131 }; 131 };
132 eeprom@52 { 132 eeprom@52 {
133 compatible = " 133 compatible = "atmel,24c256";
134 reg = <0x52>; 134 reg = <0x52>;
135 }; 135 };
136 eeprom@54 { 136 eeprom@54 {
137 compatible = " 137 compatible = "atmel,24c256";
138 reg = <0x54>; 138 reg = <0x54>;
139 }; 139 };
140 eeprom@56 { 140 eeprom@56 {
141 compatible = " 141 compatible = "atmel,24c256";
142 reg = <0x56>; 142 reg = <0x56>;
143 }; 143 };
144 rtc@68 { 144 rtc@68 {
145 compatible = " 145 compatible = "dallas,ds1374";
146 reg = <0x68>; 146 reg = <0x68>;
147 }; 147 };
148 }; 148 };
149 149
150 sdhc@114000 { 150 sdhc@114000 {
151 voltage-ranges = <1800 151 voltage-ranges = <1800 1800 3300 3300>;
152 }; 152 };
153 153
154 fman@400000 { 154 fman@400000 {
155 ethernet@e0000 { 155 ethernet@e0000 {
156 phy-handle = < 156 phy-handle = <&sgmiiphy21>;
157 phy-connection 157 phy-connection-type = "sgmii";
158 }; 158 };
159 159
160 ethernet@e2000 { 160 ethernet@e2000 {
161 phy-handle = < 161 phy-handle = <&sgmiiphy22>;
162 phy-connection 162 phy-connection-type = "sgmii";
163 }; 163 };
164 164
165 ethernet@e4000 { 165 ethernet@e4000 {
166 phy-handle = < 166 phy-handle = <&sgmiiphy23>;
167 phy-connection 167 phy-connection-type = "sgmii";
168 }; 168 };
169 169
170 ethernet@e6000 { 170 ethernet@e6000 {
171 phy-handle = < 171 phy-handle = <&sgmiiphy24>;
172 phy-connection 172 phy-connection-type = "sgmii";
173 }; 173 };
174 174
175 ethernet@e8000 { 175 ethernet@e8000 {
176 status = "disa 176 status = "disabled";
177 }; 177 };
178 178
179 ethernet@ea000 { 179 ethernet@ea000 {
180 status = "disa 180 status = "disabled";
181 }; 181 };
182 182
183 ethernet@f0000 { 183 ethernet@f0000 {
184 phy-handle = < 184 phy-handle = <&xfiphy1>;
185 phy-connection 185 phy-connection-type = "xgmii";
186 }; 186 };
187 187
188 ethernet@f2000 { 188 ethernet@f2000 {
189 phy-handle = < 189 phy-handle = <&xfiphy2>;
190 phy-connection 190 phy-connection-type = "xgmii";
191 }; 191 };
192 }; 192 };
193 193
194 fman@500000 { 194 fman@500000 {
195 ethernet@e0000 { 195 ethernet@e0000 {
196 phy-handle = < 196 phy-handle = <&sgmiiphy41>;
197 phy-connection 197 phy-connection-type = "sgmii";
198 }; 198 };
199 199
200 ethernet@e2000 { 200 ethernet@e2000 {
201 phy-handle = < 201 phy-handle = <&sgmiiphy42>;
202 phy-connection 202 phy-connection-type = "sgmii";
203 }; 203 };
204 204
205 ethernet@e4000 { 205 ethernet@e4000 {
206 phy-handle = < 206 phy-handle = <&sgmiiphy43>;
207 phy-connection 207 phy-connection-type = "sgmii";
208 }; 208 };
209 209
210 ethernet@e6000 { 210 ethernet@e6000 {
211 phy-handle = < 211 phy-handle = <&sgmiiphy44>;
212 phy-connection 212 phy-connection-type = "sgmii";
213 }; 213 };
214 214
215 ethernet@e8000 { 215 ethernet@e8000 {
216 status = "disa 216 status = "disabled";
217 }; 217 };
218 218
219 ethernet@ea000 { 219 ethernet@ea000 {
220 status = "disa 220 status = "disabled";
221 }; 221 };
222 222
223 ethernet@f0000 { 223 ethernet@f0000 {
224 phy-handle = < 224 phy-handle = <&xfiphy3>;
225 phy-connection 225 phy-connection-type = "xgmii";
226 }; 226 };
227 227
228 ethernet@f2000 { 228 ethernet@f2000 {
229 phy-handle = < 229 phy-handle = <&xfiphy4>;
230 phy-connection 230 phy-connection-type = "xgmii";
231 }; 231 };
232 232
233 mdio@fc000 { 233 mdio@fc000 {
234 sgmiiphy21: et 234 sgmiiphy21: ethernet-phy@0 {
235 reg = 235 reg = <0x0>;
236 }; 236 };
237 237
238 sgmiiphy22: et 238 sgmiiphy22: ethernet-phy@1 {
239 reg = 239 reg = <0x1>;
240 }; 240 };
241 241
242 sgmiiphy23: et 242 sgmiiphy23: ethernet-phy@2 {
243 reg = 243 reg = <0x2>;
244 }; 244 };
245 245
246 sgmiiphy24: et 246 sgmiiphy24: ethernet-phy@3 {
247 reg = 247 reg = <0x3>;
248 }; 248 };
249 249
250 sgmiiphy41: et 250 sgmiiphy41: ethernet-phy@4 {
251 reg = 251 reg = <0x4>;
252 }; 252 };
253 253
254 sgmiiphy42: et 254 sgmiiphy42: ethernet-phy@5 {
255 reg = 255 reg = <0x5>;
256 }; 256 };
257 257
258 sgmiiphy43: et 258 sgmiiphy43: ethernet-phy@6 {
259 reg = 259 reg = <0x6>;
260 }; 260 };
261 261
262 sgmiiphy44: et 262 sgmiiphy44: ethernet-phy@7 {
263 reg = 263 reg = <0x7>;
264 }; 264 };
265 }; 265 };
266 266
267 mdio@fd000 { 267 mdio@fd000 {
268 xfiphy1: ether 268 xfiphy1: ethernet-phy@10 {
269 compat 269 compatible = "ethernet-phy-id13e5.1002";
270 reg = 270 reg = <0x10>;
271 }; 271 };
272 272
273 xfiphy2: ether 273 xfiphy2: ethernet-phy@11 {
274 compat 274 compatible = "ethernet-phy-id13e5.1002";
275 reg = 275 reg = <0x11>;
276 }; 276 };
277 277
278 xfiphy3: ether 278 xfiphy3: ethernet-phy@13 {
279 compat 279 compatible = "ethernet-phy-id13e5.1002";
280 reg = 280 reg = <0x13>;
281 }; 281 };
282 282
283 xfiphy4: ether 283 xfiphy4: ethernet-phy@12 {
284 compat 284 compatible = "ethernet-phy-id13e5.1002";
285 reg = 285 reg = <0x12>;
286 }; 286 };
287 }; 287 };
288 }; 288 };
289 }; 289 };
290 290
291 pci0: pcie@ffe240000 { 291 pci0: pcie@ffe240000 {
292 reg = <0xf 0xfe240000 0 0x1000 292 reg = <0xf 0xfe240000 0 0x10000>;
293 ranges = <0x02000000 0 0xe0000 293 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
294 0x01000000 0 0x00000 294 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
295 pcie@0 { 295 pcie@0 {
296 ranges = <0x02000000 0 296 ranges = <0x02000000 0 0xe0000000
297 0x02000000 0 297 0x02000000 0 0xe0000000
298 0 0x20000000 298 0 0x20000000
299 299
300 0x01000000 0 300 0x01000000 0 0x00000000
301 0x01000000 0 301 0x01000000 0 0x00000000
302 0 0x00010000 302 0 0x00010000>;
303 }; 303 };
304 }; 304 };
305 305
306 pci1: pcie@ffe250000 { 306 pci1: pcie@ffe250000 {
307 reg = <0xf 0xfe250000 0 0x1000 307 reg = <0xf 0xfe250000 0 0x10000>;
308 ranges = <0x02000000 0x0 0xe00 308 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
309 0x01000000 0x0 0x000 309 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
310 pcie@0 { 310 pcie@0 {
311 ranges = <0x02000000 0 311 ranges = <0x02000000 0 0xe0000000
312 0x02000000 0 312 0x02000000 0 0xe0000000
313 0 0x20000000 313 0 0x20000000
314 314
315 0x01000000 0 315 0x01000000 0 0x00000000
316 0x01000000 0 316 0x01000000 0 0x00000000
317 0 0x00010000 317 0 0x00010000>;
318 }; 318 };
319 }; 319 };
320 320
321 pci2: pcie@ffe260000 { 321 pci2: pcie@ffe260000 {
322 reg = <0xf 0xfe260000 0 0x1000 322 reg = <0xf 0xfe260000 0 0x1000>;
323 ranges = <0x02000000 0 0xe0000 323 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
324 0x01000000 0 0x00000 324 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
325 pcie@0 { 325 pcie@0 {
326 ranges = <0x02000000 0 326 ranges = <0x02000000 0 0xe0000000
327 0x02000000 0 327 0x02000000 0 0xe0000000
328 0 0x20000000 328 0 0x20000000
329 329
330 0x01000000 0 330 0x01000000 0 0x00000000
331 0x01000000 0 331 0x01000000 0 0x00000000
332 0 0x00010000 332 0 0x00010000>;
333 }; 333 };
334 }; 334 };
335 335
336 pci3: pcie@ffe270000 { 336 pci3: pcie@ffe270000 {
337 reg = <0xf 0xfe270000 0 0x1000 337 reg = <0xf 0xfe270000 0 0x10000>;
338 ranges = <0x02000000 0 0xe0000 338 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
339 0x01000000 0 0x00000 339 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
340 pcie@0 { 340 pcie@0 {
341 ranges = <0x02000000 0 341 ranges = <0x02000000 0 0xe0000000
342 0x02000000 0 342 0x02000000 0 0xe0000000
343 0 0x20000000 343 0 0x20000000
344 344
345 0x01000000 0 345 0x01000000 0 0x00000000
346 0x01000000 0 346 0x01000000 0 0x00000000
347 0 0x00010000 347 0 0x00010000>;
348 }; 348 };
349 }; 349 };
350 350
351 rio: rapidio@ffe0c0000 { 351 rio: rapidio@ffe0c0000 {
352 reg = <0xf 0xfe0c0000 0 0x1100 352 reg = <0xf 0xfe0c0000 0 0x11000>;
353 353
354 port1 { 354 port1 {
355 ranges = <0 0 0xc 0x20 355 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
356 }; 356 };
357 port2 { 357 port2 {
358 ranges = <0 0 0xc 0x30 358 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
359 }; 359 };
360 }; 360 };
361 }; 361 };
362 362
363 /include/ "t4240si-post.dtsi" 363 /include/ "t4240si-post.dtsi"
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