1 /*
2 * T4240RDB Device Tree Source
3 *
4 * Copyright 2014 - 2015 Freescale Semiconduct
5 *
6 * Redistribution and use in source and binary
7 * modification, are permitted provided that t
8 * * Redistributions of source code must r
9 * notice, this list of conditions and t
10 * * Redistributions in binary form must r
11 * notice, this list of conditions and t
12 * documentation and/or other materials
13 * * Neither the name of Freescale Semicon
14 * names of its contributors may be used
15 * derived from this software without sp
16 *
17 *
18 * ALTERNATIVELY, this software may be distrib
19 * GNU General Public License ("GPL") as publi
20 * Foundation, either version 2 of that Licens
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT
33 */
34
35 /include/ "t4240si-pre.dtsi"
36
37 / {
38 model = "fsl,T4240RDB";
39 compatible = "fsl,T4240RDB";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 aliases {
45 sgmii_phy21 = &sgmiiphy21;
46 sgmii_phy22 = &sgmiiphy22;
47 sgmii_phy23 = &sgmiiphy23;
48 sgmii_phy24 = &sgmiiphy24;
49 sgmii_phy41 = &sgmiiphy41;
50 sgmii_phy42 = &sgmiiphy42;
51 sgmii_phy43 = &sgmiiphy43;
52 sgmii_phy44 = &sgmiiphy44;
53 };
54
55 ifc: localbus@ffe124000 {
56 reg = <0xf 0xfe124000 0 0x2000
57 ranges = <0 0 0xf 0xe8000000 0
58 2 0 0xf 0xff800000 0
59 3 0 0xf 0xffdf0000 0
60
61 nor@0,0 {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flas
65 reg = <0x0 0x0 0x80000
66
67 bank-width = <2>;
68 device-width = <1>;
69 };
70
71 nand@2,0 {
72 #address-cells = <1>;
73 #size-cells = <1>;
74 compatible = "fsl,ifc-
75 reg = <0x2 0x0 0x10000
76 };
77 };
78
79 memory {
80 device_type = "memory";
81 };
82
83 reserved-memory {
84 #address-cells = <2>;
85 #size-cells = <2>;
86 ranges;
87
88 bman_fbpr: bman-fbpr {
89 size = <0 0x1000000>;
90 alignment = <0 0x10000
91 };
92 qman_fqd: qman-fqd {
93 size = <0 0x400000>;
94 alignment = <0 0x40000
95 };
96 qman_pfdr: qman-pfdr {
97 size = <0 0x2000000>;
98 alignment = <0 0x20000
99 };
100 };
101
102 dcsr: dcsr@f00000000 {
103 ranges = <0x00000000 0xf 0x000
104 };
105
106 bportals: bman-portals@ff4000000 {
107 ranges = <0x0 0xf 0xf4000000 0
108 };
109
110 qportals: qman-portals@ff6000000 {
111 ranges = <0x0 0xf 0xf6000000 0
112 };
113
114 soc: soc@ffe000000 {
115 ranges = <0x00000000 0xf 0xfe0
116 reg = <0xf 0xfe000000 0 0x0000
117 spi@110000 {
118 flash@0 {
119 #address-cells
120 #size-cells =
121 compatible = "
122 reg = <0>;
123 spi-max-freque
124 };
125 };
126
127 i2c@118000 {
128 hwmon@2f {
129 compatible = "
130 reg = <0x2f>;
131 };
132 eeprom@52 {
133 compatible = "
134 reg = <0x52>;
135 };
136 eeprom@54 {
137 compatible = "
138 reg = <0x54>;
139 };
140 eeprom@56 {
141 compatible = "
142 reg = <0x56>;
143 };
144 rtc@68 {
145 compatible = "
146 reg = <0x68>;
147 };
148 };
149
150 sdhc@114000 {
151 voltage-ranges = <1800
152 };
153
154 fman@400000 {
155 ethernet@e0000 {
156 phy-handle = <
157 phy-connection
158 };
159
160 ethernet@e2000 {
161 phy-handle = <
162 phy-connection
163 };
164
165 ethernet@e4000 {
166 phy-handle = <
167 phy-connection
168 };
169
170 ethernet@e6000 {
171 phy-handle = <
172 phy-connection
173 };
174
175 ethernet@e8000 {
176 status = "disa
177 };
178
179 ethernet@ea000 {
180 status = "disa
181 };
182
183 ethernet@f0000 {
184 phy-handle = <
185 phy-connection
186 };
187
188 ethernet@f2000 {
189 phy-handle = <
190 phy-connection
191 };
192 };
193
194 fman@500000 {
195 ethernet@e0000 {
196 phy-handle = <
197 phy-connection
198 };
199
200 ethernet@e2000 {
201 phy-handle = <
202 phy-connection
203 };
204
205 ethernet@e4000 {
206 phy-handle = <
207 phy-connection
208 };
209
210 ethernet@e6000 {
211 phy-handle = <
212 phy-connection
213 };
214
215 ethernet@e8000 {
216 status = "disa
217 };
218
219 ethernet@ea000 {
220 status = "disa
221 };
222
223 ethernet@f0000 {
224 phy-handle = <
225 phy-connection
226 };
227
228 ethernet@f2000 {
229 phy-handle = <
230 phy-connection
231 };
232
233 mdio@fc000 {
234 sgmiiphy21: et
235 reg =
236 };
237
238 sgmiiphy22: et
239 reg =
240 };
241
242 sgmiiphy23: et
243 reg =
244 };
245
246 sgmiiphy24: et
247 reg =
248 };
249
250 sgmiiphy41: et
251 reg =
252 };
253
254 sgmiiphy42: et
255 reg =
256 };
257
258 sgmiiphy43: et
259 reg =
260 };
261
262 sgmiiphy44: et
263 reg =
264 };
265 };
266
267 mdio@fd000 {
268 xfiphy1: ether
269 compat
270 reg =
271 };
272
273 xfiphy2: ether
274 compat
275 reg =
276 };
277
278 xfiphy3: ether
279 compat
280 reg =
281 };
282
283 xfiphy4: ether
284 compat
285 reg =
286 };
287 };
288 };
289 };
290
291 pci0: pcie@ffe240000 {
292 reg = <0xf 0xfe240000 0 0x1000
293 ranges = <0x02000000 0 0xe0000
294 0x01000000 0 0x00000
295 pcie@0 {
296 ranges = <0x02000000 0
297 0x02000000 0
298 0 0x20000000
299
300 0x01000000 0
301 0x01000000 0
302 0 0x00010000
303 };
304 };
305
306 pci1: pcie@ffe250000 {
307 reg = <0xf 0xfe250000 0 0x1000
308 ranges = <0x02000000 0x0 0xe00
309 0x01000000 0x0 0x000
310 pcie@0 {
311 ranges = <0x02000000 0
312 0x02000000 0
313 0 0x20000000
314
315 0x01000000 0
316 0x01000000 0
317 0 0x00010000
318 };
319 };
320
321 pci2: pcie@ffe260000 {
322 reg = <0xf 0xfe260000 0 0x1000
323 ranges = <0x02000000 0 0xe0000
324 0x01000000 0 0x00000
325 pcie@0 {
326 ranges = <0x02000000 0
327 0x02000000 0
328 0 0x20000000
329
330 0x01000000 0
331 0x01000000 0
332 0 0x00010000
333 };
334 };
335
336 pci3: pcie@ffe270000 {
337 reg = <0xf 0xfe270000 0 0x1000
338 ranges = <0x02000000 0 0xe0000
339 0x01000000 0 0x00000
340 pcie@0 {
341 ranges = <0x02000000 0
342 0x02000000 0
343 0 0x20000000
344
345 0x01000000 0
346 0x01000000 0
347 0 0x00010000
348 };
349 };
350
351 rio: rapidio@ffe0c0000 {
352 reg = <0xf 0xfe0c0000 0 0x1100
353
354 port1 {
355 ranges = <0 0 0xc 0x20
356 };
357 port2 {
358 ranges = <0 0 0xc 0x30
359 };
360 };
361 };
362
363 /include/ "t4240si-post.dtsi"
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