1 /* 1 /*
2 * T4240 Silicon/SoC Device Tree Source (post 2 * T4240 Silicon/SoC Device Tree Source (post include)
3 * 3 *
4 * Copyright 2012 - 2015 Freescale Semiconduct 4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that t 7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must r 8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and t 9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must r 10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and t 11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials 12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semicon 13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used 14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without sp 15 * derived from this software without specific prior written permission.
16 * 16 *
17 * 17 *
18 * ALTERNATIVELY, this software may be distrib 18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as publi 19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that Licens 20 * Foundation, either version 2 of that License or (at your option) any
21 * later version. 21 * later version.
22 * 22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semi 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, B 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS F 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Sem 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEM 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONT 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILIT 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35 &bman_fbpr { 35 &bman_fbpr {
36 compatible = "fsl,bman-fbpr"; 36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>; 37 alloc-ranges = <0 0 0x10000 0>;
38 }; 38 };
39 39
40 &qman_fqd { 40 &qman_fqd {
41 compatible = "fsl,qman-fqd"; 41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>; 42 alloc-ranges = <0 0 0x10000 0>;
43 }; 43 };
44 44
45 &qman_pfdr { 45 &qman_pfdr {
46 compatible = "fsl,qman-pfdr"; 46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>; 47 alloc-ranges = <0 0 0x10000 0>;
48 }; 48 };
49 49
50 &ifc { 50 &ifc {
51 #address-cells = <2>; 51 #address-cells = <2>;
52 #size-cells = <1>; 52 #size-cells = <1>;
53 compatible = "fsl,ifc"; !! 53 compatible = "fsl,ifc", "simple-bus";
54 interrupts = <25 2 0 0>; 54 interrupts = <25 2 0 0>;
55 }; 55 };
56 56
57 /* controller at 0x240000 */ 57 /* controller at 0x240000 */
58 &pci0 { 58 &pci0 {
59 compatible = "fsl,t4240-pcie", "fsl,qo 59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
60 device_type = "pci"; 60 device_type = "pci";
61 #size-cells = <2>; 61 #size-cells = <2>;
62 #address-cells = <3>; 62 #address-cells = <3>;
63 bus-range = <0x0 0xff>; 63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>; 64 interrupts = <20 2 0 0>;
65 pcie@0 { 65 pcie@0 {
66 #interrupt-cells = <1>; 66 #interrupt-cells = <1>;
67 #size-cells = <2>; 67 #size-cells = <2>;
68 #address-cells = <3>; 68 #address-cells = <3>;
69 device_type = "pci"; 69 device_type = "pci";
70 reg = <0 0 0 0 0>; 70 reg = <0 0 0 0 0>;
71 interrupts = <20 2 0 0>; 71 interrupts = <20 2 0 0>;
72 interrupt-map-mask = <0xf800 0 72 interrupt-map-mask = <0xf800 0 0 7>;
73 interrupt-map = < 73 interrupt-map = <
74 /* IDSEL 0x0 */ 74 /* IDSEL 0x0 */
75 0000 0 0 1 &mpic 40 1 75 0000 0 0 1 &mpic 40 1 0 0
76 0000 0 0 2 &mpic 1 1 0 76 0000 0 0 2 &mpic 1 1 0 0
77 0000 0 0 3 &mpic 2 1 0 77 0000 0 0 3 &mpic 2 1 0 0
78 0000 0 0 4 &mpic 3 1 0 78 0000 0 0 4 &mpic 3 1 0 0
79 >; 79 >;
80 }; 80 };
81 }; 81 };
82 82
83 /* controller at 0x250000 */ 83 /* controller at 0x250000 */
84 &pci1 { 84 &pci1 {
85 compatible = "fsl,t4240-pcie", "fsl,qo 85 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
86 device_type = "pci"; 86 device_type = "pci";
87 #size-cells = <2>; 87 #size-cells = <2>;
88 #address-cells = <3>; 88 #address-cells = <3>;
89 bus-range = <0 0xff>; 89 bus-range = <0 0xff>;
90 interrupts = <21 2 0 0>; 90 interrupts = <21 2 0 0>;
91 pcie@0 { 91 pcie@0 {
92 #interrupt-cells = <1>; 92 #interrupt-cells = <1>;
93 #size-cells = <2>; 93 #size-cells = <2>;
94 #address-cells = <3>; 94 #address-cells = <3>;
95 device_type = "pci"; 95 device_type = "pci";
96 reg = <0 0 0 0 0>; 96 reg = <0 0 0 0 0>;
97 interrupts = <21 2 0 0>; 97 interrupts = <21 2 0 0>;
98 interrupt-map-mask = <0xf800 0 98 interrupt-map-mask = <0xf800 0 0 7>;
99 interrupt-map = < 99 interrupt-map = <
100 /* IDSEL 0x0 */ 100 /* IDSEL 0x0 */
101 0000 0 0 1 &mpic 41 1 101 0000 0 0 1 &mpic 41 1 0 0
102 0000 0 0 2 &mpic 5 1 0 102 0000 0 0 2 &mpic 5 1 0 0
103 0000 0 0 3 &mpic 6 1 0 103 0000 0 0 3 &mpic 6 1 0 0
104 0000 0 0 4 &mpic 7 1 0 104 0000 0 0 4 &mpic 7 1 0 0
105 >; 105 >;
106 }; 106 };
107 }; 107 };
108 108
109 /* controller at 0x260000 */ 109 /* controller at 0x260000 */
110 &pci2 { 110 &pci2 {
111 compatible = "fsl,t4240-pcie", "fsl,qo 111 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
112 device_type = "pci"; 112 device_type = "pci";
113 #size-cells = <2>; 113 #size-cells = <2>;
114 #address-cells = <3>; 114 #address-cells = <3>;
115 bus-range = <0x0 0xff>; 115 bus-range = <0x0 0xff>;
116 interrupts = <22 2 0 0>; 116 interrupts = <22 2 0 0>;
117 pcie@0 { 117 pcie@0 {
118 #interrupt-cells = <1>; 118 #interrupt-cells = <1>;
119 #size-cells = <2>; 119 #size-cells = <2>;
120 #address-cells = <3>; 120 #address-cells = <3>;
121 device_type = "pci"; 121 device_type = "pci";
122 reg = <0 0 0 0 0>; 122 reg = <0 0 0 0 0>;
123 interrupts = <22 2 0 0>; 123 interrupts = <22 2 0 0>;
124 interrupt-map-mask = <0xf800 0 124 interrupt-map-mask = <0xf800 0 0 7>;
125 interrupt-map = < 125 interrupt-map = <
126 /* IDSEL 0x0 */ 126 /* IDSEL 0x0 */
127 0000 0 0 1 &mpic 42 1 127 0000 0 0 1 &mpic 42 1 0 0
128 0000 0 0 2 &mpic 9 1 0 128 0000 0 0 2 &mpic 9 1 0 0
129 0000 0 0 3 &mpic 10 1 129 0000 0 0 3 &mpic 10 1 0 0
130 0000 0 0 4 &mpic 11 1 130 0000 0 0 4 &mpic 11 1 0 0
131 >; 131 >;
132 }; 132 };
133 }; 133 };
134 134
135 /* controller at 0x270000 */ 135 /* controller at 0x270000 */
136 &pci3 { 136 &pci3 {
137 compatible = "fsl,t4240-pcie", "fsl,qo 137 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
138 device_type = "pci"; 138 device_type = "pci";
139 #size-cells = <2>; 139 #size-cells = <2>;
140 #address-cells = <3>; 140 #address-cells = <3>;
141 bus-range = <0x0 0xff>; 141 bus-range = <0x0 0xff>;
142 interrupts = <23 2 0 0>; 142 interrupts = <23 2 0 0>;
143 pcie@0 { 143 pcie@0 {
144 #interrupt-cells = <1>; 144 #interrupt-cells = <1>;
145 #size-cells = <2>; 145 #size-cells = <2>;
146 #address-cells = <3>; 146 #address-cells = <3>;
147 device_type = "pci"; 147 device_type = "pci";
148 reg = <0 0 0 0 0>; 148 reg = <0 0 0 0 0>;
149 interrupts = <23 2 0 0>; 149 interrupts = <23 2 0 0>;
150 interrupt-map-mask = <0xf800 0 150 interrupt-map-mask = <0xf800 0 0 7>;
151 interrupt-map = < 151 interrupt-map = <
152 /* IDSEL 0x0 */ 152 /* IDSEL 0x0 */
153 0000 0 0 1 &mpic 43 1 153 0000 0 0 1 &mpic 43 1 0 0
154 0000 0 0 2 &mpic 0 1 0 154 0000 0 0 2 &mpic 0 1 0 0
155 0000 0 0 3 &mpic 4 1 0 155 0000 0 0 3 &mpic 4 1 0 0
156 0000 0 0 4 &mpic 8 1 0 156 0000 0 0 4 &mpic 8 1 0 0
157 >; 157 >;
158 }; 158 };
159 }; 159 };
160 160
161 &rio { 161 &rio {
162 compatible = "fsl,srio"; 162 compatible = "fsl,srio";
163 interrupts = <16 2 1 11>; 163 interrupts = <16 2 1 11>;
164 #address-cells = <2>; 164 #address-cells = <2>;
165 #size-cells = <2>; 165 #size-cells = <2>;
166 ranges; 166 ranges;
167 167
168 port1 { 168 port1 {
169 #address-cells = <2>; 169 #address-cells = <2>;
170 #size-cells = <2>; 170 #size-cells = <2>;
171 cell-index = <1>; 171 cell-index = <1>;
172 }; 172 };
173 173
174 port2 { 174 port2 {
175 #address-cells = <2>; 175 #address-cells = <2>;
176 #size-cells = <2>; 176 #size-cells = <2>;
177 cell-index = <2>; 177 cell-index = <2>;
178 }; 178 };
179 }; 179 };
180 180
181 &dcsr { 181 &dcsr {
182 #address-cells = <1>; 182 #address-cells = <1>;
183 #size-cells = <1>; 183 #size-cells = <1>;
184 compatible = "fsl,dcsr", "simple-bus"; 184 compatible = "fsl,dcsr", "simple-bus";
185 185
186 dcsr-epu@0 { 186 dcsr-epu@0 {
187 compatible = "fsl,t4240-dcsr-e 187 compatible = "fsl,t4240-dcsr-epu", "fsl,dcsr-epu";
188 interrupts = <52 2 0 0 188 interrupts = <52 2 0 0
189 84 2 0 0 189 84 2 0 0
190 85 2 0 0 190 85 2 0 0
191 94 2 0 0 191 94 2 0 0
192 95 2 0 0>; 192 95 2 0 0>;
193 reg = <0x0 0x1000>; 193 reg = <0x0 0x1000>;
194 }; 194 };
195 dcsr-npc { 195 dcsr-npc {
196 compatible = "fsl,t4240-dcsr-c 196 compatible = "fsl,t4240-dcsr-cnpc", "fsl,dcsr-cnpc";
197 reg = <0x1000 0x1000 0x1002000 197 reg = <0x1000 0x1000 0x1002000 0x10000>;
198 }; 198 };
199 dcsr-nxc@2000 { 199 dcsr-nxc@2000 {
200 compatible = "fsl,dcsr-nxc"; 200 compatible = "fsl,dcsr-nxc";
201 reg = <0x2000 0x1000>; 201 reg = <0x2000 0x1000>;
202 }; 202 };
203 dcsr-corenet { 203 dcsr-corenet {
204 compatible = "fsl,dcsr-corenet 204 compatible = "fsl,dcsr-corenet";
205 reg = <0x8000 0x1000 0x1A000 0 205 reg = <0x8000 0x1000 0x1A000 0x1000>;
206 }; 206 };
207 dcsr-dpaa@9000 { 207 dcsr-dpaa@9000 {
208 compatible = "fsl,t4240-dcsr-d 208 compatible = "fsl,t4240-dcsr-dpaa", "fsl,dcsr-dpaa";
209 reg = <0x9000 0x1000>; 209 reg = <0x9000 0x1000>;
210 }; 210 };
211 dcsr-ocn@11000 { 211 dcsr-ocn@11000 {
212 compatible = "fsl,t4240-dcsr-o 212 compatible = "fsl,t4240-dcsr-ocn", "fsl,dcsr-ocn";
213 reg = <0x11000 0x1000>; 213 reg = <0x11000 0x1000>;
214 }; 214 };
215 dcsr-ddr@12000 { 215 dcsr-ddr@12000 {
216 compatible = "fsl,dcsr-ddr"; 216 compatible = "fsl,dcsr-ddr";
217 dev-handle = <&ddr1>; 217 dev-handle = <&ddr1>;
218 reg = <0x12000 0x1000>; 218 reg = <0x12000 0x1000>;
219 }; 219 };
220 dcsr-ddr@13000 { 220 dcsr-ddr@13000 {
221 compatible = "fsl,dcsr-ddr"; 221 compatible = "fsl,dcsr-ddr";
222 dev-handle = <&ddr2>; 222 dev-handle = <&ddr2>;
223 reg = <0x13000 0x1000>; 223 reg = <0x13000 0x1000>;
224 }; 224 };
225 dcsr-ddr@14000 { 225 dcsr-ddr@14000 {
226 compatible = "fsl,dcsr-ddr"; 226 compatible = "fsl,dcsr-ddr";
227 dev-handle = <&ddr3>; 227 dev-handle = <&ddr3>;
228 reg = <0x14000 0x1000>; 228 reg = <0x14000 0x1000>;
229 }; 229 };
230 dcsr-nal@18000 { 230 dcsr-nal@18000 {
231 compatible = "fsl,t4240-dcsr-n 231 compatible = "fsl,t4240-dcsr-nal", "fsl,dcsr-nal";
232 reg = <0x18000 0x1000>; 232 reg = <0x18000 0x1000>;
233 }; 233 };
234 dcsr-rcpm@22000 { 234 dcsr-rcpm@22000 {
235 compatible = "fsl,t4240-dcsr-r 235 compatible = "fsl,t4240-dcsr-rcpm", "fsl,dcsr-rcpm";
236 reg = <0x22000 0x1000>; 236 reg = <0x22000 0x1000>;
237 }; 237 };
238 dcsr-snpc@30000 { 238 dcsr-snpc@30000 {
239 compatible = "fsl,t4240-dcsr-s 239 compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc";
240 reg = <0x30000 0x1000 0x102200 240 reg = <0x30000 0x1000 0x1022000 0x10000>;
241 }; 241 };
242 dcsr-snpc@31000 { 242 dcsr-snpc@31000 {
243 compatible = "fsl,t4240-dcsr-s 243 compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc";
244 reg = <0x31000 0x1000 0x104200 244 reg = <0x31000 0x1000 0x1042000 0x10000>;
245 }; 245 };
246 dcsr-snpc@32000 { 246 dcsr-snpc@32000 {
247 compatible = "fsl,t4240-dcsr-s 247 compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc";
248 reg = <0x32000 0x1000 0x106200 248 reg = <0x32000 0x1000 0x1062000 0x10000>;
249 }; 249 };
250 dcsr-cpu-sb-proxy@100000 { 250 dcsr-cpu-sb-proxy@100000 {
251 compatible = "fsl,dcsr-e6500-s 251 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
252 cpu-handle = <&cpu0>; 252 cpu-handle = <&cpu0>;
253 reg = <0x100000 0x1000 0x10100 253 reg = <0x100000 0x1000 0x101000 0x1000>;
254 }; 254 };
255 dcsr-cpu-sb-proxy@108000 { 255 dcsr-cpu-sb-proxy@108000 {
256 compatible = "fsl,dcsr-e6500-s 256 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
257 cpu-handle = <&cpu1>; 257 cpu-handle = <&cpu1>;
258 reg = <0x108000 0x1000 0x10900 258 reg = <0x108000 0x1000 0x109000 0x1000>;
259 }; 259 };
260 dcsr-cpu-sb-proxy@110000 { 260 dcsr-cpu-sb-proxy@110000 {
261 compatible = "fsl,dcsr-e6500-s 261 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
262 cpu-handle = <&cpu2>; 262 cpu-handle = <&cpu2>;
263 reg = <0x110000 0x1000 0x11100 263 reg = <0x110000 0x1000 0x111000 0x1000>;
264 }; 264 };
265 dcsr-cpu-sb-proxy@118000 { 265 dcsr-cpu-sb-proxy@118000 {
266 compatible = "fsl,dcsr-e6500-s 266 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
267 cpu-handle = <&cpu3>; 267 cpu-handle = <&cpu3>;
268 reg = <0x118000 0x1000 0x11900 268 reg = <0x118000 0x1000 0x119000 0x1000>;
269 }; 269 };
270 dcsr-cpu-sb-proxy@120000 { 270 dcsr-cpu-sb-proxy@120000 {
271 compatible = "fsl,dcsr-e6500-s 271 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
272 cpu-handle = <&cpu4>; 272 cpu-handle = <&cpu4>;
273 reg = <0x120000 0x1000 0x12100 273 reg = <0x120000 0x1000 0x121000 0x1000>;
274 }; 274 };
275 dcsr-cpu-sb-proxy@128000 { 275 dcsr-cpu-sb-proxy@128000 {
276 compatible = "fsl,dcsr-e6500-s 276 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
277 cpu-handle = <&cpu5>; 277 cpu-handle = <&cpu5>;
278 reg = <0x128000 0x1000 0x12900 278 reg = <0x128000 0x1000 0x129000 0x1000>;
279 }; 279 };
280 dcsr-cpu-sb-proxy@130000 { 280 dcsr-cpu-sb-proxy@130000 {
281 compatible = "fsl,dcsr-e6500-s 281 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
282 cpu-handle = <&cpu6>; 282 cpu-handle = <&cpu6>;
283 reg = <0x130000 0x1000 0x13100 283 reg = <0x130000 0x1000 0x131000 0x1000>;
284 }; 284 };
285 dcsr-cpu-sb-proxy@138000 { 285 dcsr-cpu-sb-proxy@138000 {
286 compatible = "fsl,dcsr-e6500-s 286 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
287 cpu-handle = <&cpu7>; 287 cpu-handle = <&cpu7>;
288 reg = <0x138000 0x1000 0x13900 288 reg = <0x138000 0x1000 0x139000 0x1000>;
289 }; 289 };
290 dcsr-cpu-sb-proxy@140000 { 290 dcsr-cpu-sb-proxy@140000 {
291 compatible = "fsl,dcsr-e6500-s 291 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
292 cpu-handle = <&cpu8>; 292 cpu-handle = <&cpu8>;
293 reg = <0x140000 0x1000 0x14100 293 reg = <0x140000 0x1000 0x141000 0x1000>;
294 }; 294 };
295 dcsr-cpu-sb-proxy@148000 { 295 dcsr-cpu-sb-proxy@148000 {
296 compatible = "fsl,dcsr-e6500-s 296 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
297 cpu-handle = <&cpu9>; 297 cpu-handle = <&cpu9>;
298 reg = <0x148000 0x1000 0x14900 298 reg = <0x148000 0x1000 0x149000 0x1000>;
299 }; 299 };
300 dcsr-cpu-sb-proxy@150000 { 300 dcsr-cpu-sb-proxy@150000 {
301 compatible = "fsl,dcsr-e6500-s 301 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
302 cpu-handle = <&cpu10>; 302 cpu-handle = <&cpu10>;
303 reg = <0x150000 0x1000 0x15100 303 reg = <0x150000 0x1000 0x151000 0x1000>;
304 }; 304 };
305 dcsr-cpu-sb-proxy@158000 { 305 dcsr-cpu-sb-proxy@158000 {
306 compatible = "fsl,dcsr-e6500-s 306 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
307 cpu-handle = <&cpu11>; 307 cpu-handle = <&cpu11>;
308 reg = <0x158000 0x1000 0x15900 308 reg = <0x158000 0x1000 0x159000 0x1000>;
309 }; 309 };
310 }; 310 };
311 311
312 &bportals { 312 &bportals {
313 #address-cells = <0x1>; 313 #address-cells = <0x1>;
314 #size-cells = <0x1>; 314 #size-cells = <0x1>;
315 compatible = "simple-bus"; 315 compatible = "simple-bus";
316 316
317 bman-portal@0 { 317 bman-portal@0 {
318 compatible = "fsl,bman-portal" 318 compatible = "fsl,bman-portal";
319 reg = <0x0 0x4000>, <0x1000000 319 reg = <0x0 0x4000>, <0x1000000 0x1000>;
320 interrupts = <105 2 0 0>; 320 interrupts = <105 2 0 0>;
321 }; 321 };
322 bman-portal@4000 { 322 bman-portal@4000 {
323 compatible = "fsl,bman-portal" 323 compatible = "fsl,bman-portal";
324 reg = <0x4000 0x4000>, <0x1001 324 reg = <0x4000 0x4000>, <0x1001000 0x1000>;
325 interrupts = <107 2 0 0>; 325 interrupts = <107 2 0 0>;
326 }; 326 };
327 bman-portal@8000 { 327 bman-portal@8000 {
328 compatible = "fsl,bman-portal" 328 compatible = "fsl,bman-portal";
329 reg = <0x8000 0x4000>, <0x1002 329 reg = <0x8000 0x4000>, <0x1002000 0x1000>;
330 interrupts = <109 2 0 0>; 330 interrupts = <109 2 0 0>;
331 }; 331 };
332 bman-portal@c000 { 332 bman-portal@c000 {
333 compatible = "fsl,bman-portal" 333 compatible = "fsl,bman-portal";
334 reg = <0xc000 0x4000>, <0x1003 334 reg = <0xc000 0x4000>, <0x1003000 0x1000>;
335 interrupts = <111 2 0 0>; 335 interrupts = <111 2 0 0>;
336 }; 336 };
337 bman-portal@10000 { 337 bman-portal@10000 {
338 compatible = "fsl,bman-portal" 338 compatible = "fsl,bman-portal";
339 reg = <0x10000 0x4000>, <0x100 339 reg = <0x10000 0x4000>, <0x1004000 0x1000>;
340 interrupts = <113 2 0 0>; 340 interrupts = <113 2 0 0>;
341 }; 341 };
342 bman-portal@14000 { 342 bman-portal@14000 {
343 compatible = "fsl,bman-portal" 343 compatible = "fsl,bman-portal";
344 reg = <0x14000 0x4000>, <0x100 344 reg = <0x14000 0x4000>, <0x1005000 0x1000>;
345 interrupts = <115 2 0 0>; 345 interrupts = <115 2 0 0>;
346 }; 346 };
347 bman-portal@18000 { 347 bman-portal@18000 {
348 compatible = "fsl,bman-portal" 348 compatible = "fsl,bman-portal";
349 reg = <0x18000 0x4000>, <0x100 349 reg = <0x18000 0x4000>, <0x1006000 0x1000>;
350 interrupts = <117 2 0 0>; 350 interrupts = <117 2 0 0>;
351 }; 351 };
352 bman-portal@1c000 { 352 bman-portal@1c000 {
353 compatible = "fsl,bman-portal" 353 compatible = "fsl,bman-portal";
354 reg = <0x1c000 0x4000>, <0x100 354 reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
355 interrupts = <119 2 0 0>; 355 interrupts = <119 2 0 0>;
356 }; 356 };
357 bman-portal@20000 { 357 bman-portal@20000 {
358 compatible = "fsl,bman-portal" 358 compatible = "fsl,bman-portal";
359 reg = <0x20000 0x4000>, <0x100 359 reg = <0x20000 0x4000>, <0x1008000 0x1000>;
360 interrupts = <121 2 0 0>; 360 interrupts = <121 2 0 0>;
361 }; 361 };
362 bman-portal@24000 { 362 bman-portal@24000 {
363 compatible = "fsl,bman-portal" 363 compatible = "fsl,bman-portal";
364 reg = <0x24000 0x4000>, <0x100 364 reg = <0x24000 0x4000>, <0x1009000 0x1000>;
365 interrupts = <123 2 0 0>; 365 interrupts = <123 2 0 0>;
366 }; 366 };
367 bman-portal@28000 { 367 bman-portal@28000 {
368 compatible = "fsl,bman-portal" 368 compatible = "fsl,bman-portal";
369 reg = <0x28000 0x4000>, <0x100 369 reg = <0x28000 0x4000>, <0x100a000 0x1000>;
370 interrupts = <125 2 0 0>; 370 interrupts = <125 2 0 0>;
371 }; 371 };
372 bman-portal@2c000 { 372 bman-portal@2c000 {
373 compatible = "fsl,bman-portal" 373 compatible = "fsl,bman-portal";
374 reg = <0x2c000 0x4000>, <0x100 374 reg = <0x2c000 0x4000>, <0x100b000 0x1000>;
375 interrupts = <127 2 0 0>; 375 interrupts = <127 2 0 0>;
376 }; 376 };
377 bman-portal@30000 { 377 bman-portal@30000 {
378 compatible = "fsl,bman-portal" 378 compatible = "fsl,bman-portal";
379 reg = <0x30000 0x4000>, <0x100 379 reg = <0x30000 0x4000>, <0x100c000 0x1000>;
380 interrupts = <129 2 0 0>; 380 interrupts = <129 2 0 0>;
381 }; 381 };
382 bman-portal@34000 { 382 bman-portal@34000 {
383 compatible = "fsl,bman-portal" 383 compatible = "fsl,bman-portal";
384 reg = <0x34000 0x4000>, <0x100 384 reg = <0x34000 0x4000>, <0x100d000 0x1000>;
385 interrupts = <131 2 0 0>; 385 interrupts = <131 2 0 0>;
386 }; 386 };
387 bman-portal@38000 { 387 bman-portal@38000 {
388 compatible = "fsl,bman-portal" 388 compatible = "fsl,bman-portal";
389 reg = <0x38000 0x4000>, <0x100 389 reg = <0x38000 0x4000>, <0x100e000 0x1000>;
390 interrupts = <133 2 0 0>; 390 interrupts = <133 2 0 0>;
391 }; 391 };
392 bman-portal@3c000 { 392 bman-portal@3c000 {
393 compatible = "fsl,bman-portal" 393 compatible = "fsl,bman-portal";
394 reg = <0x3c000 0x4000>, <0x100 394 reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
395 interrupts = <135 2 0 0>; 395 interrupts = <135 2 0 0>;
396 }; 396 };
397 bman-portal@40000 { 397 bman-portal@40000 {
398 compatible = "fsl,bman-portal" 398 compatible = "fsl,bman-portal";
399 reg = <0x40000 0x4000>, <0x101 399 reg = <0x40000 0x4000>, <0x1010000 0x1000>;
400 interrupts = <137 2 0 0>; 400 interrupts = <137 2 0 0>;
401 }; 401 };
402 bman-portal@44000 { 402 bman-portal@44000 {
403 compatible = "fsl,bman-portal" 403 compatible = "fsl,bman-portal";
404 reg = <0x44000 0x4000>, <0x101 404 reg = <0x44000 0x4000>, <0x1011000 0x1000>;
405 interrupts = <139 2 0 0>; 405 interrupts = <139 2 0 0>;
406 }; 406 };
407 bman-portal@48000 { 407 bman-portal@48000 {
408 compatible = "fsl,bman-portal" 408 compatible = "fsl,bman-portal";
409 reg = <0x48000 0x4000>, <0x101 409 reg = <0x48000 0x4000>, <0x1012000 0x1000>;
410 interrupts = <141 2 0 0>; 410 interrupts = <141 2 0 0>;
411 }; 411 };
412 bman-portal@4c000 { 412 bman-portal@4c000 {
413 compatible = "fsl,bman-portal" 413 compatible = "fsl,bman-portal";
414 reg = <0x4c000 0x4000>, <0x101 414 reg = <0x4c000 0x4000>, <0x1013000 0x1000>;
415 interrupts = <143 2 0 0>; 415 interrupts = <143 2 0 0>;
416 }; 416 };
417 bman-portal@50000 { 417 bman-portal@50000 {
418 compatible = "fsl,bman-portal" 418 compatible = "fsl,bman-portal";
419 reg = <0x50000 0x4000>, <0x101 419 reg = <0x50000 0x4000>, <0x1014000 0x1000>;
420 interrupts = <145 2 0 0>; 420 interrupts = <145 2 0 0>;
421 }; 421 };
422 bman-portal@54000 { 422 bman-portal@54000 {
423 compatible = "fsl,bman-portal" 423 compatible = "fsl,bman-portal";
424 reg = <0x54000 0x4000>, <0x101 424 reg = <0x54000 0x4000>, <0x1015000 0x1000>;
425 interrupts = <147 2 0 0>; 425 interrupts = <147 2 0 0>;
426 }; 426 };
427 bman-portal@58000 { 427 bman-portal@58000 {
428 compatible = "fsl,bman-portal" 428 compatible = "fsl,bman-portal";
429 reg = <0x58000 0x4000>, <0x101 429 reg = <0x58000 0x4000>, <0x1016000 0x1000>;
430 interrupts = <149 2 0 0>; 430 interrupts = <149 2 0 0>;
431 }; 431 };
432 bman-portal@5c000 { 432 bman-portal@5c000 {
433 compatible = "fsl,bman-portal" 433 compatible = "fsl,bman-portal";
434 reg = <0x5c000 0x4000>, <0x101 434 reg = <0x5c000 0x4000>, <0x1017000 0x1000>;
435 interrupts = <151 2 0 0>; 435 interrupts = <151 2 0 0>;
436 }; 436 };
437 bman-portal@60000 { 437 bman-portal@60000 {
438 compatible = "fsl,bman-portal" 438 compatible = "fsl,bman-portal";
439 reg = <0x60000 0x4000>, <0x101 439 reg = <0x60000 0x4000>, <0x1018000 0x1000>;
440 interrupts = <153 2 0 0>; 440 interrupts = <153 2 0 0>;
441 }; 441 };
442 bman-portal@64000 { 442 bman-portal@64000 {
443 compatible = "fsl,bman-portal" 443 compatible = "fsl,bman-portal";
444 reg = <0x64000 0x4000>, <0x101 444 reg = <0x64000 0x4000>, <0x1019000 0x1000>;
445 interrupts = <155 2 0 0>; 445 interrupts = <155 2 0 0>;
446 }; 446 };
447 bman-portal@68000 { 447 bman-portal@68000 {
448 compatible = "fsl,bman-portal" 448 compatible = "fsl,bman-portal";
449 reg = <0x68000 0x4000>, <0x101 449 reg = <0x68000 0x4000>, <0x101a000 0x1000>;
450 interrupts = <157 2 0 0>; 450 interrupts = <157 2 0 0>;
451 }; 451 };
452 bman-portal@6c000 { 452 bman-portal@6c000 {
453 compatible = "fsl,bman-portal" 453 compatible = "fsl,bman-portal";
454 reg = <0x6c000 0x4000>, <0x101 454 reg = <0x6c000 0x4000>, <0x101b000 0x1000>;
455 interrupts = <159 2 0 0>; 455 interrupts = <159 2 0 0>;
456 }; 456 };
457 bman-portal@70000 { 457 bman-portal@70000 {
458 compatible = "fsl,bman-portal" 458 compatible = "fsl,bman-portal";
459 reg = <0x70000 0x4000>, <0x101 459 reg = <0x70000 0x4000>, <0x101c000 0x1000>;
460 interrupts = <161 2 0 0>; 460 interrupts = <161 2 0 0>;
461 }; 461 };
462 bman-portal@74000 { 462 bman-portal@74000 {
463 compatible = "fsl,bman-portal" 463 compatible = "fsl,bman-portal";
464 reg = <0x74000 0x4000>, <0x101 464 reg = <0x74000 0x4000>, <0x101d000 0x1000>;
465 interrupts = <163 2 0 0>; 465 interrupts = <163 2 0 0>;
466 }; 466 };
467 bman-portal@78000 { 467 bman-portal@78000 {
468 compatible = "fsl,bman-portal" 468 compatible = "fsl,bman-portal";
469 reg = <0x78000 0x4000>, <0x101 469 reg = <0x78000 0x4000>, <0x101e000 0x1000>;
470 interrupts = <165 2 0 0>; 470 interrupts = <165 2 0 0>;
471 }; 471 };
472 bman-portal@7c000 { 472 bman-portal@7c000 {
473 compatible = "fsl,bman-portal" 473 compatible = "fsl,bman-portal";
474 reg = <0x7c000 0x4000>, <0x101 474 reg = <0x7c000 0x4000>, <0x101f000 0x1000>;
475 interrupts = <167 2 0 0>; 475 interrupts = <167 2 0 0>;
476 }; 476 };
477 bman-portal@80000 { 477 bman-portal@80000 {
478 compatible = "fsl,bman-portal" 478 compatible = "fsl,bman-portal";
479 reg = <0x80000 0x4000>, <0x102 479 reg = <0x80000 0x4000>, <0x1020000 0x1000>;
480 interrupts = <169 2 0 0>; 480 interrupts = <169 2 0 0>;
481 }; 481 };
482 bman-portal@84000 { 482 bman-portal@84000 {
483 compatible = "fsl,bman-portal" 483 compatible = "fsl,bman-portal";
484 reg = <0x84000 0x4000>, <0x102 484 reg = <0x84000 0x4000>, <0x1021000 0x1000>;
485 interrupts = <171 2 0 0>; 485 interrupts = <171 2 0 0>;
486 }; 486 };
487 bman-portal@88000 { 487 bman-portal@88000 {
488 compatible = "fsl,bman-portal" 488 compatible = "fsl,bman-portal";
489 reg = <0x88000 0x4000>, <0x102 489 reg = <0x88000 0x4000>, <0x1022000 0x1000>;
490 interrupts = <173 2 0 0>; 490 interrupts = <173 2 0 0>;
491 }; 491 };
492 bman-portal@8c000 { 492 bman-portal@8c000 {
493 compatible = "fsl,bman-portal" 493 compatible = "fsl,bman-portal";
494 reg = <0x8c000 0x4000>, <0x102 494 reg = <0x8c000 0x4000>, <0x1023000 0x1000>;
495 interrupts = <175 2 0 0>; 495 interrupts = <175 2 0 0>;
496 }; 496 };
497 bman-portal@90000 { 497 bman-portal@90000 {
498 compatible = "fsl,bman-portal" 498 compatible = "fsl,bman-portal";
499 reg = <0x90000 0x4000>, <0x102 499 reg = <0x90000 0x4000>, <0x1024000 0x1000>;
500 interrupts = <385 2 0 0>; 500 interrupts = <385 2 0 0>;
501 }; 501 };
502 bman-portal@94000 { 502 bman-portal@94000 {
503 compatible = "fsl,bman-portal" 503 compatible = "fsl,bman-portal";
504 reg = <0x94000 0x4000>, <0x102 504 reg = <0x94000 0x4000>, <0x1025000 0x1000>;
505 interrupts = <387 2 0 0>; 505 interrupts = <387 2 0 0>;
506 }; 506 };
507 bman-portal@98000 { 507 bman-portal@98000 {
508 compatible = "fsl,bman-portal" 508 compatible = "fsl,bman-portal";
509 reg = <0x98000 0x4000>, <0x102 509 reg = <0x98000 0x4000>, <0x1026000 0x1000>;
510 interrupts = <389 2 0 0>; 510 interrupts = <389 2 0 0>;
511 }; 511 };
512 bman-portal@9c000 { 512 bman-portal@9c000 {
513 compatible = "fsl,bman-portal" 513 compatible = "fsl,bman-portal";
514 reg = <0x9c000 0x4000>, <0x102 514 reg = <0x9c000 0x4000>, <0x1027000 0x1000>;
515 interrupts = <391 2 0 0>; 515 interrupts = <391 2 0 0>;
516 }; 516 };
517 bman-portal@a0000 { 517 bman-portal@a0000 {
518 compatible = "fsl,bman-portal" 518 compatible = "fsl,bman-portal";
519 reg = <0xa0000 0x4000>, <0x102 519 reg = <0xa0000 0x4000>, <0x1028000 0x1000>;
520 interrupts = <393 2 0 0>; 520 interrupts = <393 2 0 0>;
521 }; 521 };
522 bman-portal@a4000 { 522 bman-portal@a4000 {
523 compatible = "fsl,bman-portal" 523 compatible = "fsl,bman-portal";
524 reg = <0xa4000 0x4000>, <0x102 524 reg = <0xa4000 0x4000>, <0x1029000 0x1000>;
525 interrupts = <395 2 0 0>; 525 interrupts = <395 2 0 0>;
526 }; 526 };
527 bman-portal@a8000 { 527 bman-portal@a8000 {
528 compatible = "fsl,bman-portal" 528 compatible = "fsl,bman-portal";
529 reg = <0xa8000 0x4000>, <0x102 529 reg = <0xa8000 0x4000>, <0x102a000 0x1000>;
530 interrupts = <397 2 0 0>; 530 interrupts = <397 2 0 0>;
531 }; 531 };
532 bman-portal@ac000 { 532 bman-portal@ac000 {
533 compatible = "fsl,bman-portal" 533 compatible = "fsl,bman-portal";
534 reg = <0xac000 0x4000>, <0x102 534 reg = <0xac000 0x4000>, <0x102b000 0x1000>;
535 interrupts = <399 2 0 0>; 535 interrupts = <399 2 0 0>;
536 }; 536 };
537 bman-portal@b0000 { 537 bman-portal@b0000 {
538 compatible = "fsl,bman-portal" 538 compatible = "fsl,bman-portal";
539 reg = <0xb0000 0x4000>, <0x102 539 reg = <0xb0000 0x4000>, <0x102c000 0x1000>;
540 interrupts = <401 2 0 0>; 540 interrupts = <401 2 0 0>;
541 }; 541 };
542 bman-portal@b4000 { 542 bman-portal@b4000 {
543 compatible = "fsl,bman-portal" 543 compatible = "fsl,bman-portal";
544 reg = <0xb4000 0x4000>, <0x102 544 reg = <0xb4000 0x4000>, <0x102d000 0x1000>;
545 interrupts = <403 2 0 0>; 545 interrupts = <403 2 0 0>;
546 }; 546 };
547 bman-portal@b8000 { 547 bman-portal@b8000 {
548 compatible = "fsl,bman-portal" 548 compatible = "fsl,bman-portal";
549 reg = <0xb8000 0x4000>, <0x102 549 reg = <0xb8000 0x4000>, <0x102e000 0x1000>;
550 interrupts = <405 2 0 0>; 550 interrupts = <405 2 0 0>;
551 }; 551 };
552 bman-portal@bc000 { 552 bman-portal@bc000 {
553 compatible = "fsl,bman-portal" 553 compatible = "fsl,bman-portal";
554 reg = <0xbc000 0x4000>, <0x102 554 reg = <0xbc000 0x4000>, <0x102f000 0x1000>;
555 interrupts = <407 2 0 0>; 555 interrupts = <407 2 0 0>;
556 }; 556 };
557 bman-portal@c0000 { 557 bman-portal@c0000 {
558 compatible = "fsl,bman-portal" 558 compatible = "fsl,bman-portal";
559 reg = <0xc0000 0x4000>, <0x103 559 reg = <0xc0000 0x4000>, <0x1030000 0x1000>;
560 interrupts = <409 2 0 0>; 560 interrupts = <409 2 0 0>;
561 }; 561 };
562 bman-portal@c4000 { 562 bman-portal@c4000 {
563 compatible = "fsl,bman-portal" 563 compatible = "fsl,bman-portal";
564 reg = <0xc4000 0x4000>, <0x103 564 reg = <0xc4000 0x4000>, <0x1031000 0x1000>;
565 interrupts = <411 2 0 0>; 565 interrupts = <411 2 0 0>;
566 }; 566 };
567 }; 567 };
568 568
569 &qportals { 569 &qportals {
570 #address-cells = <0x1>; 570 #address-cells = <0x1>;
571 #size-cells = <0x1>; 571 #size-cells = <0x1>;
572 compatible = "simple-bus"; 572 compatible = "simple-bus";
573 573
574 qportal0: qman-portal@0 { 574 qportal0: qman-portal@0 {
575 compatible = "fsl,qman-portal" 575 compatible = "fsl,qman-portal";
576 reg = <0x0 0x4000>, <0x1000000 576 reg = <0x0 0x4000>, <0x1000000 0x1000>;
577 interrupts = <104 0x2 0 0>; 577 interrupts = <104 0x2 0 0>;
578 cell-index = <0x0>; 578 cell-index = <0x0>;
579 }; 579 };
580 qportal1: qman-portal@4000 { 580 qportal1: qman-portal@4000 {
581 compatible = "fsl,qman-portal" 581 compatible = "fsl,qman-portal";
582 reg = <0x4000 0x4000>, <0x1001 582 reg = <0x4000 0x4000>, <0x1001000 0x1000>;
583 interrupts = <106 0x2 0 0>; 583 interrupts = <106 0x2 0 0>;
584 cell-index = <0x1>; 584 cell-index = <0x1>;
585 }; 585 };
586 qportal2: qman-portal@8000 { 586 qportal2: qman-portal@8000 {
587 compatible = "fsl,qman-portal" 587 compatible = "fsl,qman-portal";
588 reg = <0x8000 0x4000>, <0x1002 588 reg = <0x8000 0x4000>, <0x1002000 0x1000>;
589 interrupts = <108 0x2 0 0>; 589 interrupts = <108 0x2 0 0>;
590 cell-index = <0x2>; 590 cell-index = <0x2>;
591 }; 591 };
592 qportal3: qman-portal@c000 { 592 qportal3: qman-portal@c000 {
593 compatible = "fsl,qman-portal" 593 compatible = "fsl,qman-portal";
594 reg = <0xc000 0x4000>, <0x1003 594 reg = <0xc000 0x4000>, <0x1003000 0x1000>;
595 interrupts = <110 0x2 0 0>; 595 interrupts = <110 0x2 0 0>;
596 cell-index = <0x3>; 596 cell-index = <0x3>;
597 }; 597 };
598 qportal4: qman-portal@10000 { 598 qportal4: qman-portal@10000 {
599 compatible = "fsl,qman-portal" 599 compatible = "fsl,qman-portal";
600 reg = <0x10000 0x4000>, <0x100 600 reg = <0x10000 0x4000>, <0x1004000 0x1000>;
601 interrupts = <112 0x2 0 0>; 601 interrupts = <112 0x2 0 0>;
602 cell-index = <0x4>; 602 cell-index = <0x4>;
603 }; 603 };
604 qportal5: qman-portal@14000 { 604 qportal5: qman-portal@14000 {
605 compatible = "fsl,qman-portal" 605 compatible = "fsl,qman-portal";
606 reg = <0x14000 0x4000>, <0x100 606 reg = <0x14000 0x4000>, <0x1005000 0x1000>;
607 interrupts = <114 0x2 0 0>; 607 interrupts = <114 0x2 0 0>;
608 cell-index = <0x5>; 608 cell-index = <0x5>;
609 }; 609 };
610 qportal6: qman-portal@18000 { 610 qportal6: qman-portal@18000 {
611 compatible = "fsl,qman-portal" 611 compatible = "fsl,qman-portal";
612 reg = <0x18000 0x4000>, <0x100 612 reg = <0x18000 0x4000>, <0x1006000 0x1000>;
613 interrupts = <116 0x2 0 0>; 613 interrupts = <116 0x2 0 0>;
614 cell-index = <0x6>; 614 cell-index = <0x6>;
615 }; 615 };
616 qportal7: qman-portal@1c000 { 616 qportal7: qman-portal@1c000 {
617 compatible = "fsl,qman-portal" 617 compatible = "fsl,qman-portal";
618 reg = <0x1c000 0x4000>, <0x100 618 reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
619 interrupts = <118 0x2 0 0>; 619 interrupts = <118 0x2 0 0>;
620 cell-index = <0x7>; 620 cell-index = <0x7>;
621 }; 621 };
622 qportal8: qman-portal@20000 { 622 qportal8: qman-portal@20000 {
623 compatible = "fsl,qman-portal" 623 compatible = "fsl,qman-portal";
624 reg = <0x20000 0x4000>, <0x100 624 reg = <0x20000 0x4000>, <0x1008000 0x1000>;
625 interrupts = <120 0x2 0 0>; 625 interrupts = <120 0x2 0 0>;
626 cell-index = <0x8>; 626 cell-index = <0x8>;
627 }; 627 };
628 qportal9: qman-portal@24000 { 628 qportal9: qman-portal@24000 {
629 compatible = "fsl,qman-portal" 629 compatible = "fsl,qman-portal";
630 reg = <0x24000 0x4000>, <0x100 630 reg = <0x24000 0x4000>, <0x1009000 0x1000>;
631 interrupts = <122 0x2 0 0>; 631 interrupts = <122 0x2 0 0>;
632 cell-index = <0x9>; 632 cell-index = <0x9>;
633 }; 633 };
634 qportal10: qman-portal@28000 { 634 qportal10: qman-portal@28000 {
635 compatible = "fsl,qman-portal" 635 compatible = "fsl,qman-portal";
636 reg = <0x28000 0x4000>, <0x100 636 reg = <0x28000 0x4000>, <0x100a000 0x1000>;
637 interrupts = <124 0x2 0 0>; 637 interrupts = <124 0x2 0 0>;
638 cell-index = <0xa>; 638 cell-index = <0xa>;
639 }; 639 };
640 qportal11: qman-portal@2c000 { 640 qportal11: qman-portal@2c000 {
641 compatible = "fsl,qman-portal" 641 compatible = "fsl,qman-portal";
642 reg = <0x2c000 0x4000>, <0x100 642 reg = <0x2c000 0x4000>, <0x100b000 0x1000>;
643 interrupts = <126 0x2 0 0>; 643 interrupts = <126 0x2 0 0>;
644 cell-index = <0xb>; 644 cell-index = <0xb>;
645 }; 645 };
646 qportal12: qman-portal@30000 { 646 qportal12: qman-portal@30000 {
647 compatible = "fsl,qman-portal" 647 compatible = "fsl,qman-portal";
648 reg = <0x30000 0x4000>, <0x100 648 reg = <0x30000 0x4000>, <0x100c000 0x1000>;
649 interrupts = <128 0x2 0 0>; 649 interrupts = <128 0x2 0 0>;
650 cell-index = <0xc>; 650 cell-index = <0xc>;
651 }; 651 };
652 qportal13: qman-portal@34000 { 652 qportal13: qman-portal@34000 {
653 compatible = "fsl,qman-portal" 653 compatible = "fsl,qman-portal";
654 reg = <0x34000 0x4000>, <0x100 654 reg = <0x34000 0x4000>, <0x100d000 0x1000>;
655 interrupts = <130 0x2 0 0>; 655 interrupts = <130 0x2 0 0>;
656 cell-index = <0xd>; 656 cell-index = <0xd>;
657 }; 657 };
658 qportal14: qman-portal@38000 { 658 qportal14: qman-portal@38000 {
659 compatible = "fsl,qman-portal" 659 compatible = "fsl,qman-portal";
660 reg = <0x38000 0x4000>, <0x100 660 reg = <0x38000 0x4000>, <0x100e000 0x1000>;
661 interrupts = <132 0x2 0 0>; 661 interrupts = <132 0x2 0 0>;
662 cell-index = <0xe>; 662 cell-index = <0xe>;
663 }; 663 };
664 qportal15: qman-portal@3c000 { 664 qportal15: qman-portal@3c000 {
665 compatible = "fsl,qman-portal" 665 compatible = "fsl,qman-portal";
666 reg = <0x3c000 0x4000>, <0x100 666 reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
667 interrupts = <134 0x2 0 0>; 667 interrupts = <134 0x2 0 0>;
668 cell-index = <0xf>; 668 cell-index = <0xf>;
669 }; 669 };
670 qportal16: qman-portal@40000 { 670 qportal16: qman-portal@40000 {
671 compatible = "fsl,qman-portal" 671 compatible = "fsl,qman-portal";
672 reg = <0x40000 0x4000>, <0x101 672 reg = <0x40000 0x4000>, <0x1010000 0x1000>;
673 interrupts = <136 0x2 0 0>; 673 interrupts = <136 0x2 0 0>;
674 cell-index = <0x10>; 674 cell-index = <0x10>;
675 }; 675 };
676 qportal17: qman-portal@44000 { 676 qportal17: qman-portal@44000 {
677 compatible = "fsl,qman-portal" 677 compatible = "fsl,qman-portal";
678 reg = <0x44000 0x4000>, <0x101 678 reg = <0x44000 0x4000>, <0x1011000 0x1000>;
679 interrupts = <138 0x2 0 0>; 679 interrupts = <138 0x2 0 0>;
680 cell-index = <0x11>; 680 cell-index = <0x11>;
681 }; 681 };
682 qportal18: qman-portal@48000 { 682 qportal18: qman-portal@48000 {
683 compatible = "fsl,qman-portal" 683 compatible = "fsl,qman-portal";
684 reg = <0x48000 0x4000>, <0x101 684 reg = <0x48000 0x4000>, <0x1012000 0x1000>;
685 interrupts = <140 0x2 0 0>; 685 interrupts = <140 0x2 0 0>;
686 cell-index = <0x12>; 686 cell-index = <0x12>;
687 }; 687 };
688 qportal19: qman-portal@4c000 { 688 qportal19: qman-portal@4c000 {
689 compatible = "fsl,qman-portal" 689 compatible = "fsl,qman-portal";
690 reg = <0x4c000 0x4000>, <0x101 690 reg = <0x4c000 0x4000>, <0x1013000 0x1000>;
691 interrupts = <142 0x2 0 0>; 691 interrupts = <142 0x2 0 0>;
692 cell-index = <0x13>; 692 cell-index = <0x13>;
693 }; 693 };
694 qportal20: qman-portal@50000 { 694 qportal20: qman-portal@50000 {
695 compatible = "fsl,qman-portal" 695 compatible = "fsl,qman-portal";
696 reg = <0x50000 0x4000>, <0x101 696 reg = <0x50000 0x4000>, <0x1014000 0x1000>;
697 interrupts = <144 0x2 0 0>; 697 interrupts = <144 0x2 0 0>;
698 cell-index = <0x14>; 698 cell-index = <0x14>;
699 }; 699 };
700 qportal21: qman-portal@54000 { 700 qportal21: qman-portal@54000 {
701 compatible = "fsl,qman-portal" 701 compatible = "fsl,qman-portal";
702 reg = <0x54000 0x4000>, <0x101 702 reg = <0x54000 0x4000>, <0x1015000 0x1000>;
703 interrupts = <146 0x2 0 0>; 703 interrupts = <146 0x2 0 0>;
704 cell-index = <0x15>; 704 cell-index = <0x15>;
705 }; 705 };
706 qportal22: qman-portal@58000 { 706 qportal22: qman-portal@58000 {
707 compatible = "fsl,qman-portal" 707 compatible = "fsl,qman-portal";
708 reg = <0x58000 0x4000>, <0x101 708 reg = <0x58000 0x4000>, <0x1016000 0x1000>;
709 interrupts = <148 0x2 0 0>; 709 interrupts = <148 0x2 0 0>;
710 cell-index = <0x16>; 710 cell-index = <0x16>;
711 }; 711 };
712 qportal23: qman-portal@5c000 { 712 qportal23: qman-portal@5c000 {
713 compatible = "fsl,qman-portal" 713 compatible = "fsl,qman-portal";
714 reg = <0x5c000 0x4000>, <0x101 714 reg = <0x5c000 0x4000>, <0x1017000 0x1000>;
715 interrupts = <150 0x2 0 0>; 715 interrupts = <150 0x2 0 0>;
716 cell-index = <0x17>; 716 cell-index = <0x17>;
717 }; 717 };
718 qportal24: qman-portal@60000 { 718 qportal24: qman-portal@60000 {
719 compatible = "fsl,qman-portal" 719 compatible = "fsl,qman-portal";
720 reg = <0x60000 0x4000>, <0x101 720 reg = <0x60000 0x4000>, <0x1018000 0x1000>;
721 interrupts = <152 0x2 0 0>; 721 interrupts = <152 0x2 0 0>;
722 cell-index = <0x18>; 722 cell-index = <0x18>;
723 }; 723 };
724 qportal25: qman-portal@64000 { 724 qportal25: qman-portal@64000 {
725 compatible = "fsl,qman-portal" 725 compatible = "fsl,qman-portal";
726 reg = <0x64000 0x4000>, <0x101 726 reg = <0x64000 0x4000>, <0x1019000 0x1000>;
727 interrupts = <154 0x2 0 0>; 727 interrupts = <154 0x2 0 0>;
728 cell-index = <0x19>; 728 cell-index = <0x19>;
729 }; 729 };
730 qportal26: qman-portal@68000 { 730 qportal26: qman-portal@68000 {
731 compatible = "fsl,qman-portal" 731 compatible = "fsl,qman-portal";
732 reg = <0x68000 0x4000>, <0x101 732 reg = <0x68000 0x4000>, <0x101a000 0x1000>;
733 interrupts = <156 0x2 0 0>; 733 interrupts = <156 0x2 0 0>;
734 cell-index = <0x1a>; 734 cell-index = <0x1a>;
735 }; 735 };
736 qportal27: qman-portal@6c000 { 736 qportal27: qman-portal@6c000 {
737 compatible = "fsl,qman-portal" 737 compatible = "fsl,qman-portal";
738 reg = <0x6c000 0x4000>, <0x101 738 reg = <0x6c000 0x4000>, <0x101b000 0x1000>;
739 interrupts = <158 0x2 0 0>; 739 interrupts = <158 0x2 0 0>;
740 cell-index = <0x1b>; 740 cell-index = <0x1b>;
741 }; 741 };
742 qportal28: qman-portal@70000 { 742 qportal28: qman-portal@70000 {
743 compatible = "fsl,qman-portal" 743 compatible = "fsl,qman-portal";
744 reg = <0x70000 0x4000>, <0x101 744 reg = <0x70000 0x4000>, <0x101c000 0x1000>;
745 interrupts = <160 0x2 0 0>; 745 interrupts = <160 0x2 0 0>;
746 cell-index = <0x1c>; 746 cell-index = <0x1c>;
747 }; 747 };
748 qportal29: qman-portal@74000 { 748 qportal29: qman-portal@74000 {
749 compatible = "fsl,qman-portal" 749 compatible = "fsl,qman-portal";
750 reg = <0x74000 0x4000>, <0x101 750 reg = <0x74000 0x4000>, <0x101d000 0x1000>;
751 interrupts = <162 0x2 0 0>; 751 interrupts = <162 0x2 0 0>;
752 cell-index = <0x1d>; 752 cell-index = <0x1d>;
753 }; 753 };
754 qportal30: qman-portal@78000 { 754 qportal30: qman-portal@78000 {
755 compatible = "fsl,qman-portal" 755 compatible = "fsl,qman-portal";
756 reg = <0x78000 0x4000>, <0x101 756 reg = <0x78000 0x4000>, <0x101e000 0x1000>;
757 interrupts = <164 0x2 0 0>; 757 interrupts = <164 0x2 0 0>;
758 cell-index = <0x1e>; 758 cell-index = <0x1e>;
759 }; 759 };
760 qportal31: qman-portal@7c000 { 760 qportal31: qman-portal@7c000 {
761 compatible = "fsl,qman-portal" 761 compatible = "fsl,qman-portal";
762 reg = <0x7c000 0x4000>, <0x101 762 reg = <0x7c000 0x4000>, <0x101f000 0x1000>;
763 interrupts = <166 0x2 0 0>; 763 interrupts = <166 0x2 0 0>;
764 cell-index = <0x1f>; 764 cell-index = <0x1f>;
765 }; 765 };
766 qportal32: qman-portal@80000 { 766 qportal32: qman-portal@80000 {
767 compatible = "fsl,qman-portal" 767 compatible = "fsl,qman-portal";
768 reg = <0x80000 0x4000>, <0x102 768 reg = <0x80000 0x4000>, <0x1020000 0x1000>;
769 interrupts = <168 0x2 0 0>; 769 interrupts = <168 0x2 0 0>;
770 cell-index = <0x20>; 770 cell-index = <0x20>;
771 }; 771 };
772 qportal33: qman-portal@84000 { 772 qportal33: qman-portal@84000 {
773 compatible = "fsl,qman-portal" 773 compatible = "fsl,qman-portal";
774 reg = <0x84000 0x4000>, <0x102 774 reg = <0x84000 0x4000>, <0x1021000 0x1000>;
775 interrupts = <170 0x2 0 0>; 775 interrupts = <170 0x2 0 0>;
776 cell-index = <0x21>; 776 cell-index = <0x21>;
777 }; 777 };
778 qportal34: qman-portal@88000 { 778 qportal34: qman-portal@88000 {
779 compatible = "fsl,qman-portal" 779 compatible = "fsl,qman-portal";
780 reg = <0x88000 0x4000>, <0x102 780 reg = <0x88000 0x4000>, <0x1022000 0x1000>;
781 interrupts = <172 0x2 0 0>; 781 interrupts = <172 0x2 0 0>;
782 cell-index = <0x22>; 782 cell-index = <0x22>;
783 }; 783 };
784 qportal35: qman-portal@8c000 { 784 qportal35: qman-portal@8c000 {
785 compatible = "fsl,qman-portal" 785 compatible = "fsl,qman-portal";
786 reg = <0x8c000 0x4000>, <0x102 786 reg = <0x8c000 0x4000>, <0x1023000 0x1000>;
787 interrupts = <174 0x2 0 0>; 787 interrupts = <174 0x2 0 0>;
788 cell-index = <0x23>; 788 cell-index = <0x23>;
789 }; 789 };
790 qportal36: qman-portal@90000 { 790 qportal36: qman-portal@90000 {
791 compatible = "fsl,qman-portal" 791 compatible = "fsl,qman-portal";
792 reg = <0x90000 0x4000>, <0x102 792 reg = <0x90000 0x4000>, <0x1024000 0x1000>;
793 interrupts = <384 0x2 0 0>; 793 interrupts = <384 0x2 0 0>;
794 cell-index = <0x24>; 794 cell-index = <0x24>;
795 }; 795 };
796 qportal37: qman-portal@94000 { 796 qportal37: qman-portal@94000 {
797 compatible = "fsl,qman-portal" 797 compatible = "fsl,qman-portal";
798 reg = <0x94000 0x4000>, <0x102 798 reg = <0x94000 0x4000>, <0x1025000 0x1000>;
799 interrupts = <386 0x2 0 0>; 799 interrupts = <386 0x2 0 0>;
800 cell-index = <0x25>; 800 cell-index = <0x25>;
801 }; 801 };
802 qportal38: qman-portal@98000 { 802 qportal38: qman-portal@98000 {
803 compatible = "fsl,qman-portal" 803 compatible = "fsl,qman-portal";
804 reg = <0x98000 0x4000>, <0x102 804 reg = <0x98000 0x4000>, <0x1026000 0x1000>;
805 interrupts = <388 0x2 0 0>; 805 interrupts = <388 0x2 0 0>;
806 cell-index = <0x26>; 806 cell-index = <0x26>;
807 }; 807 };
808 qportal39: qman-portal@9c000 { 808 qportal39: qman-portal@9c000 {
809 compatible = "fsl,qman-portal" 809 compatible = "fsl,qman-portal";
810 reg = <0x9c000 0x4000>, <0x102 810 reg = <0x9c000 0x4000>, <0x1027000 0x1000>;
811 interrupts = <390 0x2 0 0>; 811 interrupts = <390 0x2 0 0>;
812 cell-index = <0x27>; 812 cell-index = <0x27>;
813 }; 813 };
814 qportal40: qman-portal@a0000 { 814 qportal40: qman-portal@a0000 {
815 compatible = "fsl,qman-portal" 815 compatible = "fsl,qman-portal";
816 reg = <0xa0000 0x4000>, <0x102 816 reg = <0xa0000 0x4000>, <0x1028000 0x1000>;
817 interrupts = <392 0x2 0 0>; 817 interrupts = <392 0x2 0 0>;
818 cell-index = <0x28>; 818 cell-index = <0x28>;
819 }; 819 };
820 qportal41: qman-portal@a4000 { 820 qportal41: qman-portal@a4000 {
821 compatible = "fsl,qman-portal" 821 compatible = "fsl,qman-portal";
822 reg = <0xa4000 0x4000>, <0x102 822 reg = <0xa4000 0x4000>, <0x1029000 0x1000>;
823 interrupts = <394 0x2 0 0>; 823 interrupts = <394 0x2 0 0>;
824 cell-index = <0x29>; 824 cell-index = <0x29>;
825 }; 825 };
826 qportal42: qman-portal@a8000 { 826 qportal42: qman-portal@a8000 {
827 compatible = "fsl,qman-portal" 827 compatible = "fsl,qman-portal";
828 reg = <0xa8000 0x4000>, <0x102 828 reg = <0xa8000 0x4000>, <0x102a000 0x1000>;
829 interrupts = <396 0x2 0 0>; 829 interrupts = <396 0x2 0 0>;
830 cell-index = <0x2a>; 830 cell-index = <0x2a>;
831 }; 831 };
832 qportal43: qman-portal@ac000 { 832 qportal43: qman-portal@ac000 {
833 compatible = "fsl,qman-portal" 833 compatible = "fsl,qman-portal";
834 reg = <0xac000 0x4000>, <0x102 834 reg = <0xac000 0x4000>, <0x102b000 0x1000>;
835 interrupts = <398 0x2 0 0>; 835 interrupts = <398 0x2 0 0>;
836 cell-index = <0x2b>; 836 cell-index = <0x2b>;
837 }; 837 };
838 qportal44: qman-portal@b0000 { 838 qportal44: qman-portal@b0000 {
839 compatible = "fsl,qman-portal" 839 compatible = "fsl,qman-portal";
840 reg = <0xb0000 0x4000>, <0x102 840 reg = <0xb0000 0x4000>, <0x102c000 0x1000>;
841 interrupts = <400 0x2 0 0>; 841 interrupts = <400 0x2 0 0>;
842 cell-index = <0x2c>; 842 cell-index = <0x2c>;
843 }; 843 };
844 qportal45: qman-portal@b4000 { 844 qportal45: qman-portal@b4000 {
845 compatible = "fsl,qman-portal" 845 compatible = "fsl,qman-portal";
846 reg = <0xb4000 0x4000>, <0x102 846 reg = <0xb4000 0x4000>, <0x102d000 0x1000>;
847 interrupts = <402 0x2 0 0>; 847 interrupts = <402 0x2 0 0>;
848 cell-index = <0x2d>; 848 cell-index = <0x2d>;
849 }; 849 };
850 qportal46: qman-portal@b8000 { 850 qportal46: qman-portal@b8000 {
851 compatible = "fsl,qman-portal" 851 compatible = "fsl,qman-portal";
852 reg = <0xb8000 0x4000>, <0x102 852 reg = <0xb8000 0x4000>, <0x102e000 0x1000>;
853 interrupts = <404 0x2 0 0>; 853 interrupts = <404 0x2 0 0>;
854 cell-index = <0x2e>; 854 cell-index = <0x2e>;
855 }; 855 };
856 qportal47: qman-portal@bc000 { 856 qportal47: qman-portal@bc000 {
857 compatible = "fsl,qman-portal" 857 compatible = "fsl,qman-portal";
858 reg = <0xbc000 0x4000>, <0x102 858 reg = <0xbc000 0x4000>, <0x102f000 0x1000>;
859 interrupts = <406 0x2 0 0>; 859 interrupts = <406 0x2 0 0>;
860 cell-index = <0x2f>; 860 cell-index = <0x2f>;
861 }; 861 };
862 qportal48: qman-portal@c0000 { 862 qportal48: qman-portal@c0000 {
863 compatible = "fsl,qman-portal" 863 compatible = "fsl,qman-portal";
864 reg = <0xc0000 0x4000>, <0x103 864 reg = <0xc0000 0x4000>, <0x1030000 0x1000>;
865 interrupts = <408 0x2 0 0>; 865 interrupts = <408 0x2 0 0>;
866 cell-index = <0x30>; 866 cell-index = <0x30>;
867 }; 867 };
868 qportal49: qman-portal@c4000 { 868 qportal49: qman-portal@c4000 {
869 compatible = "fsl,qman-portal" 869 compatible = "fsl,qman-portal";
870 reg = <0xc4000 0x4000>, <0x103 870 reg = <0xc4000 0x4000>, <0x1031000 0x1000>;
871 interrupts = <410 0x2 0 0>; 871 interrupts = <410 0x2 0 0>;
872 cell-index = <0x31>; 872 cell-index = <0x31>;
873 }; 873 };
874 }; 874 };
875 875
876 &soc { 876 &soc {
877 #address-cells = <1>; 877 #address-cells = <1>;
878 #size-cells = <1>; 878 #size-cells = <1>;
879 device_type = "soc"; 879 device_type = "soc";
880 compatible = "simple-bus"; 880 compatible = "simple-bus";
881 881
882 soc-sram-error { 882 soc-sram-error {
883 compatible = "fsl,soc-sram-err 883 compatible = "fsl,soc-sram-error";
884 interrupts = <16 2 1 29>; 884 interrupts = <16 2 1 29>;
885 }; 885 };
886 886
887 corenet-law@0 { 887 corenet-law@0 {
888 compatible = "fsl,corenet-law" 888 compatible = "fsl,corenet-law";
889 reg = <0x0 0x1000>; 889 reg = <0x0 0x1000>;
890 fsl,num-laws = <32>; 890 fsl,num-laws = <32>;
891 }; 891 };
892 892
893 ddr1: memory-controller@8000 { 893 ddr1: memory-controller@8000 {
894 compatible = "fsl,qoriq-memory 894 compatible = "fsl,qoriq-memory-controller-v4.7",
895 "fsl,qoriq-mem 895 "fsl,qoriq-memory-controller";
896 reg = <0x8000 0x1000>; 896 reg = <0x8000 0x1000>;
897 interrupts = <16 2 1 23>; 897 interrupts = <16 2 1 23>;
898 }; 898 };
899 899
900 ddr2: memory-controller@9000 { 900 ddr2: memory-controller@9000 {
901 compatible = "fsl,qoriq-memory 901 compatible = "fsl,qoriq-memory-controller-v4.7",
902 "fsl,qoriq-mem 902 "fsl,qoriq-memory-controller";
903 reg = <0x9000 0x1000>; 903 reg = <0x9000 0x1000>;
904 interrupts = <16 2 1 22>; 904 interrupts = <16 2 1 22>;
905 }; 905 };
906 906
907 ddr3: memory-controller@a000 { 907 ddr3: memory-controller@a000 {
908 compatible = "fsl,qoriq-memory 908 compatible = "fsl,qoriq-memory-controller-v4.7",
909 "fsl,qoriq-mem 909 "fsl,qoriq-memory-controller";
910 reg = <0xa000 0x1000>; 910 reg = <0xa000 0x1000>;
911 interrupts = <16 2 1 21>; 911 interrupts = <16 2 1 21>;
912 }; 912 };
913 913
914 cpc: l3-cache-controller@10000 { 914 cpc: l3-cache-controller@10000 {
915 compatible = "fsl,t4240-l3-cac 915 compatible = "fsl,t4240-l3-cache-controller", "cache";
916 reg = <0x10000 0x1000 916 reg = <0x10000 0x1000
917 0x11000 0x1000 917 0x11000 0x1000
918 0x12000 0x1000>; 918 0x12000 0x1000>;
919 interrupts = <16 2 1 27 919 interrupts = <16 2 1 27
920 16 2 1 26 920 16 2 1 26
921 16 2 1 25>; 921 16 2 1 25>;
922 }; 922 };
923 923
924 corenet-cf@18000 { 924 corenet-cf@18000 {
925 compatible = "fsl,corenet2-cf" 925 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
926 reg = <0x18000 0x1000>; 926 reg = <0x18000 0x1000>;
927 interrupts = <16 2 1 31>; 927 interrupts = <16 2 1 31>;
928 fsl,ccf-num-csdids = <32>; 928 fsl,ccf-num-csdids = <32>;
929 fsl,ccf-num-snoopids = <32>; 929 fsl,ccf-num-snoopids = <32>;
930 }; 930 };
931 931
932 iommu@20000 { 932 iommu@20000 {
933 compatible = "fsl,pamu-v1.0", 933 compatible = "fsl,pamu-v1.0", "fsl,pamu";
934 reg = <0x20000 0x6000>; 934 reg = <0x20000 0x6000>;
935 fsl,portid-mapping = <0x8000>; 935 fsl,portid-mapping = <0x8000>;
936 interrupts = < 936 interrupts = <
937 24 2 0 0 937 24 2 0 0
938 16 2 1 30>; 938 16 2 1 30>;
939 }; 939 };
940 940
941 /include/ "qoriq-mpic4.3.dtsi" 941 /include/ "qoriq-mpic4.3.dtsi"
942 942
943 guts: global-utilities@e0000 { 943 guts: global-utilities@e0000 {
944 compatible = "fsl,t4240-device 944 compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0";
945 reg = <0xe0000 0xe00>; 945 reg = <0xe0000 0xe00>;
946 fsl,has-rstcr; 946 fsl,has-rstcr;
947 fsl,liodn-bits = <12>; 947 fsl,liodn-bits = <12>;
948 }; 948 };
949 949
950 /include/ "qoriq-clockgen2.dtsi" 950 /include/ "qoriq-clockgen2.dtsi"
951 global-utilities@e1000 { 951 global-utilities@e1000 {
952 compatible = "fsl,t4240-clockg 952 compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
>> 953
>> 954 pll2: pll2@840 {
>> 955 #clock-cells = <1>;
>> 956 reg = <0x840 0x4>;
>> 957 compatible = "fsl,qoriq-core-pll-2.0";
>> 958 clocks = <&sysclk>;
>> 959 clock-output-names = "pll2", "pll2-div2", "pll2-div4";
>> 960 };
>> 961
>> 962 pll3: pll3@860 {
>> 963 #clock-cells = <1>;
>> 964 reg = <0x860 0x4>;
>> 965 compatible = "fsl,qoriq-core-pll-2.0";
>> 966 clocks = <&sysclk>;
>> 967 clock-output-names = "pll3", "pll3-div2", "pll3-div4";
>> 968 };
>> 969
>> 970 pll4: pll4@880 {
>> 971 #clock-cells = <1>;
>> 972 reg = <0x880 0x4>;
>> 973 compatible = "fsl,qoriq-core-pll-2.0";
>> 974 clocks = <&sysclk>;
>> 975 clock-output-names = "pll4", "pll4-div2", "pll4-div4";
>> 976 };
>> 977
>> 978 mux0: mux0@0 {
>> 979 #clock-cells = <0>;
>> 980 reg = <0x0 0x4>;
>> 981 compatible = "fsl,qoriq-core-mux-2.0";
>> 982 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
>> 983 <&pll1 0>, <&pll1 1>, <&pll1 2>,
>> 984 <&pll2 0>, <&pll2 1>, <&pll2 2>;
>> 985 clock-names = "pll0", "pll0-div2", "pll0-div4",
>> 986 "pll1", "pll1-div2", "pll1-div4",
>> 987 "pll2", "pll2-div2", "pll2-div4";
>> 988 clock-output-names = "cmux0";
>> 989 };
>> 990
>> 991 mux1: mux1@20 {
>> 992 #clock-cells = <0>;
>> 993 reg = <0x20 0x4>;
>> 994 compatible = "fsl,qoriq-core-mux-2.0";
>> 995 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
>> 996 <&pll1 0>, <&pll1 1>, <&pll1 2>,
>> 997 <&pll2 0>, <&pll2 1>, <&pll2 2>;
>> 998 clock-names = "pll0", "pll0-div2", "pll0-div4",
>> 999 "pll1", "pll1-div2", "pll1-div4",
>> 1000 "pll2", "pll2-div2", "pll2-div4";
>> 1001 clock-output-names = "cmux1";
>> 1002 };
>> 1003
>> 1004 mux2: mux2@40 {
>> 1005 #clock-cells = <0>;
>> 1006 reg = <0x40 0x4>;
>> 1007 compatible = "fsl,qoriq-core-mux-2.0";
>> 1008 clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>,
>> 1009 <&pll4 0>, <&pll4 1>, <&pll4 2>;
>> 1010 clock-names = "pll3", "pll3-div2", "pll3-div4",
>> 1011 "pll4", "pll4-div2", "pll4-div4";
>> 1012 clock-output-names = "cmux2";
>> 1013 };
953 }; 1014 };
954 1015
955 rcpm: global-utilities@e2000 { 1016 rcpm: global-utilities@e2000 {
956 compatible = "fsl,t4240-rcpm", 1017 compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
957 reg = <0xe2000 0x1000>; 1018 reg = <0xe2000 0x1000>;
958 }; 1019 };
959 1020
960 sfp: sfp@e8000 { 1021 sfp: sfp@e8000 {
961 compatible = "fsl,t4240-sfp"; 1022 compatible = "fsl,t4240-sfp";
962 reg = <0xe8000 0x1000>; 1023 reg = <0xe8000 0x1000>;
963 }; 1024 };
964 1025
965 serdes: serdes@ea000 { 1026 serdes: serdes@ea000 {
966 compatible = "fsl,t4240-serdes 1027 compatible = "fsl,t4240-serdes";
967 reg = <0xea000 0x4000>; 1028 reg = <0xea000 0x4000>;
968 }; 1029 };
969 1030
970 /include/ "elo3-dma-0.dtsi" 1031 /include/ "elo3-dma-0.dtsi"
971 /include/ "elo3-dma-1.dtsi" 1032 /include/ "elo3-dma-1.dtsi"
972 /include/ "elo3-dma-2.dtsi" 1033 /include/ "elo3-dma-2.dtsi"
973 1034
974 /include/ "qoriq-espi-0.dtsi" 1035 /include/ "qoriq-espi-0.dtsi"
975 spi@110000 { 1036 spi@110000 {
976 fsl,espi-num-chipselects = <4> 1037 fsl,espi-num-chipselects = <4>;
977 }; 1038 };
978 1039
979 /include/ "qoriq-esdhc-0.dtsi" 1040 /include/ "qoriq-esdhc-0.dtsi"
980 sdhc@114000 { 1041 sdhc@114000 {
981 compatible = "fsl,t4240-esdhc" 1042 compatible = "fsl,t4240-esdhc", "fsl,esdhc";
982 sdhci,auto-cmd12; 1043 sdhci,auto-cmd12;
983 }; 1044 };
984 /include/ "qoriq-i2c-0.dtsi" 1045 /include/ "qoriq-i2c-0.dtsi"
985 /include/ "qoriq-i2c-1.dtsi" 1046 /include/ "qoriq-i2c-1.dtsi"
986 /include/ "qoriq-duart-0.dtsi" 1047 /include/ "qoriq-duart-0.dtsi"
987 /include/ "qoriq-duart-1.dtsi" 1048 /include/ "qoriq-duart-1.dtsi"
988 /include/ "qoriq-gpio-0.dtsi" 1049 /include/ "qoriq-gpio-0.dtsi"
989 /include/ "qoriq-gpio-1.dtsi" 1050 /include/ "qoriq-gpio-1.dtsi"
990 /include/ "qoriq-gpio-2.dtsi" 1051 /include/ "qoriq-gpio-2.dtsi"
991 /include/ "qoriq-gpio-3.dtsi" 1052 /include/ "qoriq-gpio-3.dtsi"
992 /include/ "qoriq-usb2-mph-0.dtsi" 1053 /include/ "qoriq-usb2-mph-0.dtsi"
993 usb0: usb@210000 { 1054 usb0: usb@210000 {
994 compatible = "fsl-usb2 1055 compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph";
995 phy_type = "utmi"; 1056 phy_type = "utmi";
996 port0; 1057 port0;
997 }; 1058 };
998 /include/ "qoriq-usb2-dr-0.dtsi" 1059 /include/ "qoriq-usb2-dr-0.dtsi"
999 usb1: usb@211000 { 1060 usb1: usb@211000 {
1000 compatible = "fsl-usb 1061 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
1001 dr_mode = "host"; 1062 dr_mode = "host";
1002 phy_type = "utmi"; 1063 phy_type = "utmi";
1003 }; 1064 };
1004 /include/ "qoriq-sata2-0.dtsi" 1065 /include/ "qoriq-sata2-0.dtsi"
1005 /include/ "qoriq-sata2-1.dtsi" 1066 /include/ "qoriq-sata2-1.dtsi"
1006 /include/ "qoriq-sec5.0-0.dtsi" 1067 /include/ "qoriq-sec5.0-0.dtsi"
1007 /include/ "qoriq-qman3.dtsi" 1068 /include/ "qoriq-qman3.dtsi"
1008 /include/ "qoriq-bman1.dtsi" 1069 /include/ "qoriq-bman1.dtsi"
1009 1070
1010 /include/ "qoriq-fman3-0.dtsi" 1071 /include/ "qoriq-fman3-0.dtsi"
1011 /include/ "qoriq-fman3-0-1g-0.dtsi" 1072 /include/ "qoriq-fman3-0-1g-0.dtsi"
1012 /include/ "qoriq-fman3-0-1g-1.dtsi" 1073 /include/ "qoriq-fman3-0-1g-1.dtsi"
1013 /include/ "qoriq-fman3-0-1g-2.dtsi" 1074 /include/ "qoriq-fman3-0-1g-2.dtsi"
1014 /include/ "qoriq-fman3-0-1g-3.dtsi" 1075 /include/ "qoriq-fman3-0-1g-3.dtsi"
1015 /include/ "qoriq-fman3-0-1g-4.dtsi" 1076 /include/ "qoriq-fman3-0-1g-4.dtsi"
1016 /include/ "qoriq-fman3-0-1g-5.dtsi" 1077 /include/ "qoriq-fman3-0-1g-5.dtsi"
1017 /include/ "qoriq-fman3-0-10g-0.dtsi" 1078 /include/ "qoriq-fman3-0-10g-0.dtsi"
1018 /include/ "qoriq-fman3-0-10g-1.dtsi" 1079 /include/ "qoriq-fman3-0-10g-1.dtsi"
1019 fman@400000 { 1080 fman@400000 {
1020 enet0: ethernet@e0000 { 1081 enet0: ethernet@e0000 {
1021 }; 1082 };
1022 1083
1023 enet1: ethernet@e2000 { 1084 enet1: ethernet@e2000 {
1024 }; 1085 };
1025 1086
1026 enet2: ethernet@e4000 { 1087 enet2: ethernet@e4000 {
1027 }; 1088 };
1028 1089
1029 enet3: ethernet@e6000 { 1090 enet3: ethernet@e6000 {
1030 }; 1091 };
1031 1092
1032 enet4: ethernet@e8000 { 1093 enet4: ethernet@e8000 {
1033 }; 1094 };
1034 1095
1035 enet5: ethernet@ea000 { 1096 enet5: ethernet@ea000 {
1036 }; 1097 };
1037 1098
1038 enet6: ethernet@f0000 { 1099 enet6: ethernet@f0000 {
1039 }; 1100 };
1040 1101
1041 enet7: ethernet@f2000 { 1102 enet7: ethernet@f2000 {
1042 }; 1103 };
1043 1104
1044 mdio@fc000 { 1105 mdio@fc000 {
1045 status = "disabled"; 1106 status = "disabled";
1046 }; 1107 };
1047 1108
1048 mdio@fd000 { 1109 mdio@fd000 {
1049 status = "disabled"; 1110 status = "disabled";
1050 }; 1111 };
1051 }; 1112 };
1052 1113
1053 /include/ "qoriq-fman3-1.dtsi" 1114 /include/ "qoriq-fman3-1.dtsi"
1054 /include/ "qoriq-fman3-1-1g-0.dtsi" 1115 /include/ "qoriq-fman3-1-1g-0.dtsi"
1055 /include/ "qoriq-fman3-1-1g-1.dtsi" 1116 /include/ "qoriq-fman3-1-1g-1.dtsi"
1056 /include/ "qoriq-fman3-1-1g-2.dtsi" 1117 /include/ "qoriq-fman3-1-1g-2.dtsi"
1057 /include/ "qoriq-fman3-1-1g-3.dtsi" 1118 /include/ "qoriq-fman3-1-1g-3.dtsi"
1058 /include/ "qoriq-fman3-1-1g-4.dtsi" 1119 /include/ "qoriq-fman3-1-1g-4.dtsi"
1059 /include/ "qoriq-fman3-1-1g-5.dtsi" 1120 /include/ "qoriq-fman3-1-1g-5.dtsi"
1060 /include/ "qoriq-fman3-1-10g-0.dtsi" 1121 /include/ "qoriq-fman3-1-10g-0.dtsi"
1061 /include/ "qoriq-fman3-1-10g-1.dtsi" 1122 /include/ "qoriq-fman3-1-10g-1.dtsi"
1062 fman@500000 { 1123 fman@500000 {
1063 enet8: ethernet@e0000 { 1124 enet8: ethernet@e0000 {
1064 }; 1125 };
1065 1126
1066 enet9: ethernet@e2000 { 1127 enet9: ethernet@e2000 {
1067 }; 1128 };
1068 1129
1069 enet10: ethernet@e4000 { 1130 enet10: ethernet@e4000 {
1070 }; 1131 };
1071 1132
1072 enet11: ethernet@e6000 { 1133 enet11: ethernet@e6000 {
1073 }; 1134 };
1074 1135
1075 enet12: ethernet@e8000 { 1136 enet12: ethernet@e8000 {
1076 }; 1137 };
1077 1138
1078 enet13: ethernet@ea000 { 1139 enet13: ethernet@ea000 {
1079 }; 1140 };
1080 1141
1081 enet14: ethernet@f0000 { 1142 enet14: ethernet@f0000 {
1082 }; 1143 };
1083 1144
1084 enet15: ethernet@f2000 { 1145 enet15: ethernet@f2000 {
1085 }; 1146 };
1086 1147
1087 mdio@fc000 { 1148 mdio@fc000 {
1088 interrupts = <100 1 0 1149 interrupts = <100 1 0 0>;
1089 }; 1150 };
1090 1151
1091 mdio@fd000 { 1152 mdio@fd000 {
1092 interrupts = <101 1 0 1153 interrupts = <101 1 0 0>;
1093 }; 1154 };
1094 }; 1155 };
1095 1156
1096 L2_1: l2-cache-controller@c20000 { 1157 L2_1: l2-cache-controller@c20000 {
1097 compatible = "fsl,t4240-l2-ca 1158 compatible = "fsl,t4240-l2-cache-controller";
1098 reg = <0xc20000 0x40000>; 1159 reg = <0xc20000 0x40000>;
1099 next-level-cache = <&cpc>; 1160 next-level-cache = <&cpc>;
1100 }; 1161 };
1101 L2_2: l2-cache-controller@c60000 { 1162 L2_2: l2-cache-controller@c60000 {
1102 compatible = "fsl,t4240-l2-ca 1163 compatible = "fsl,t4240-l2-cache-controller";
1103 reg = <0xc60000 0x40000>; 1164 reg = <0xc60000 0x40000>;
1104 next-level-cache = <&cpc>; 1165 next-level-cache = <&cpc>;
1105 }; 1166 };
1106 L2_3: l2-cache-controller@ca0000 { 1167 L2_3: l2-cache-controller@ca0000 {
1107 compatible = "fsl,t4240-l2-ca 1168 compatible = "fsl,t4240-l2-cache-controller";
1108 reg = <0xca0000 0x40000>; 1169 reg = <0xca0000 0x40000>;
1109 next-level-cache = <&cpc>; 1170 next-level-cache = <&cpc>;
1110 }; 1171 };
1111 }; 1172 };
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