1 /*
2 * Device Tree Source for Mosaix Technologies,
3 *
4 * Copyright 2010 DENX Software Engineering, S<
5 *
6 * This file is licensed under the terms of th
7 * License version 2. This program is license
8 * any warranty of any kind, whether express o
9 */
10
11 /dts-v1/;
12
13 / {
14 #address-cells = <2>;
15 #size-cells = <2>;
16 model = "mosaixtech,icon";
17 compatible = "mosaixtech,icon";
18 dcr-parent = <&{/cpus/cpu@0}>;
19
20 aliases {
21 ethernet0 = &EMAC0;
22 serial0 = &UART0;
23 serial1 = &UART1;
24 serial2 = &UART2;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 model = "PowerPC,440SP
34 reg = <0x00000000>;
35 clock-frequency = <0>;
36 timebase-frequency = <
37 i-cache-line-size = <3
38 d-cache-line-size = <3
39 i-cache-size = <32768>
40 d-cache-size = <32768>
41 dcr-controller;
42 dcr-access-method = "n
43 reset-type = <2>;
44 };
45 };
46
47 memory {
48 device_type = "memory";
49 reg = <0x0 0x00000000 0x0 0x00
50 };
51
52 UIC0: interrupt-controller0 {
53 compatible = "ibm,uic-440spe",
54 interrupt-controller;
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
58 #size-cells = <0>;
59 #interrupt-cells = <2>;
60 };
61
62 UIC1: interrupt-controller1 {
63 compatible = "ibm,uic-440spe",
64 interrupt-controller;
65 cell-index = <1>;
66 dcr-reg = <0x0d0 0x009>;
67 #address-cells = <0>;
68 #size-cells = <0>;
69 #interrupt-cells = <2>;
70 interrupts = <0x1e 0x4 0x1f 0x
71 interrupt-parent = <&UIC0>;
72 };
73
74 UIC2: interrupt-controller2 {
75 compatible = "ibm,uic-440spe",
76 interrupt-controller;
77 cell-index = <2>;
78 dcr-reg = <0x0e0 0x009>;
79 #address-cells = <0>;
80 #size-cells = <0>;
81 #interrupt-cells = <2>;
82 interrupts = <0xa 0x4 0xb 0x4>
83 interrupt-parent = <&UIC0>;
84 };
85
86 UIC3: interrupt-controller3 {
87 compatible = "ibm,uic-440spe",
88 interrupt-controller;
89 cell-index = <3>;
90 dcr-reg = <0x0f0 0x009>;
91 #address-cells = <0>;
92 #size-cells = <0>;
93 #interrupt-cells = <2>;
94 interrupts = <0x10 0x4 0x11 0x
95 interrupt-parent = <&UIC0>;
96 };
97
98 SDR0: sdr {
99 compatible = "ibm,sdr-440spe";
100 dcr-reg = <0x00e 0x002>;
101 };
102
103 CPR0: cpr {
104 compatible = "ibm,cpr-440spe";
105 dcr-reg = <0x00c 0x002>;
106 };
107
108 MQ0: mq {
109 compatible = "ibm,mq-440spe";
110 dcr-reg = <0x040 0x020>;
111 };
112
113 plb {
114 compatible = "ibm,plb-440spe",
115 #address-cells = <2>;
116 #size-cells = <1>;
117 /* addr-child addr-
118 ranges = <0x4 0x00100000 0x4 0
119 0x4 0x00200000 0x4 0
120 0x4 0xe0000000 0x4 0
121 0xc 0x00000000 0xc 0
122 0xd 0x00000000 0xd 0
123 0xd 0x80000000 0xd 0
124 0xe 0x00000000 0xe 0
125 0xe 0x80000000 0xe 0
126 0xf 0x00000000 0xf 0
127 0xf 0x80000000 0xf 0
128 clock-frequency = <0>; /* Fill
129
130 SDRAM0: sdram {
131 compatible = "ibm,sdra
132 dcr-reg = <0x010 0x002
133 };
134
135 MAL0: mcmal {
136 compatible = "ibm,mcma
137 dcr-reg = <0x180 0x062
138 num-tx-chans = <2>;
139 num-rx-chans = <1>;
140 interrupt-parent = <&M
141 interrupts = <0x0 0x1
142 #interrupt-cells = <1>
143 #address-cells = <0>;
144 #size-cells = <0>;
145 interrupt-map = </*TXE
146 /*RXE
147 /*SER
148 /*TXD
149 /*RXD
150 };
151
152 POB0: opb {
153 compatible = "ibm,opb-
154 #address-cells = <1>;
155 #size-cells = <1>;
156 ranges = <0xe0000000 0
157 clock-frequency = <0>;
158
159 EBC0: ebc {
160 compatible = "
161 dcr-reg = <0x0
162 #address-cells
163 #size-cells =
164 clock-frequenc
165 /* ranges prop
166 interrupts = <
167 interrupt-pare
168
169 nor_flash@0,0
170 compat
171 bank-w
172 reg =
173 #addre
174 #size-
175 partit
176
177
178 };
179 partit
180
181
182 };
183 partit
184
185
186 };
187 partit
188
189
190 };
191 partit
192
193
194 };
195 partit
196
197
198 };
199 };
200 };
201
202 UART0: serial@f0000200
203 device_type =
204 compatible = "
205 reg = <0xf0000
206 virtual-reg =
207 clock-frequenc
208 current-speed
209 interrupt-pare
210 interrupts = <
211 };
212
213 UART1: serial@f0000300
214 device_type =
215 compatible = "
216 reg = <0xf0000
217 virtual-reg =
218 clock-frequenc
219 current-speed
220 interrupt-pare
221 interrupts = <
222 };
223
224
225 UART2: serial@f0000600
226 device_type =
227 compatible = "
228 reg = <0xf0000
229 virtual-reg =
230 clock-frequenc
231 current-speed
232 interrupt-pare
233 interrupts = <
234 };
235
236 IIC0: i2c@f0000400 {
237 compatible = "
238 reg = <0xf0000
239 interrupt-pare
240 interrupts = <
241 };
242
243 IIC1: i2c@f0000500 {
244 compatible = "
245 reg = <0xf0000
246 interrupt-pare
247 interrupts = <
248 #address-cells
249 #size-cells =
250
251 rtc@68 {
252 compat
253 reg =
254 };
255 };
256
257 EMAC0: ethernet@f00008
258 linux,network-
259 device_type =
260 compatible = "
261 interrupt-pare
262 interrupts = <
263 reg = <0xf0000
264 local-mac-addr
265 mal-device = <
266 mal-tx-channel
267 mal-rx-channel
268 cell-index = <
269 max-frame-size
270 rx-fifo-size =
271 tx-fifo-size =
272 phy-mode = "gm
273 phy-map = <0x0
274 has-inverted-s
275 has-new-stacr-
276 };
277 };
278
279 PCIX0: pci@c0ec00000 {
280 device_type = "pci";
281 #interrupt-cells = <1>
282 #size-cells = <2>;
283 #address-cells = <3>;
284 compatible = "ibm,plb-
285 primary;
286 large-inbound-windows;
287 enable-msi-hole;
288 reg = <0x0000000c 0x0e
289 0x00000000 0x00
290 0x0000000c 0x0e
291 0x0000000c 0x0e
292 0x0000000c 0x0e
293
294 /* Outbound ranges, on
295 * later cannot be cha
296 */
297 ranges = <0x02000000 0
298 0x01000000 0
299
300 /* Inbound 4GB range s
301 dma-ranges = <0x420000
302
303 /* This drives busses
304 bus-range = <0x0 0xf>;
305
306 /* PCI-X interrupt (SM
307 interrupt-map-mask = <
308 interrupt-map = <0x0 0
309 };
310
311 PCIE0: pcie@d00000000 {
312 device_type = "pci";
313 #interrupt-cells = <1>
314 #size-cells = <2>;
315 #address-cells = <3>;
316 compatible = "ibm,plb-
317 primary;
318 port = <0x0>; /* port
319 reg = <0x0000000d 0x00
320 0x0000000c 0x10
321 dcr-reg = <0x100 0x020
322 sdr-base = <0x300>;
323
324 /* Outbound ranges, on
325 * later cannot be cha
326 */
327 ranges = <0x02000000 0
328 0x01000000 0
329
330 /* Inbound 4GB range s
331 dma-ranges = <0x420000
332
333 /* This drives busses
334 bus-range = <0x10 0x1f
335
336 /* Legacy interrupts (
337 * to invert PCIe lega
338 * We are de-swizzling
339 * port of the root co
340 * to avoid putting a
341 * below are basically
342 * The real slot is on
343 */
344 interrupt-map-mask = <
345 interrupt-map = <
346 0x0 0x0 0x0 0x
347 0x0 0x0 0x0 0x
348 0x0 0x0 0x0 0x
349 0x0 0x0 0x0 0x
350 };
351
352 PCIE1: pcie@d20000000 {
353 device_type = "pci";
354 #interrupt-cells = <1>
355 #size-cells = <2>;
356 #address-cells = <3>;
357 compatible = "ibm,plb-
358 primary;
359 port = <0x1>; /* port
360 reg = <0x0000000d 0x20
361 0x0000000c 0x10
362 dcr-reg = <0x120 0x020
363 sdr-base = <0x340>;
364
365 /* Outbound ranges, on
366 * later cannot be cha
367 */
368 ranges = <0x02000000 0
369 0x01000000 0
370
371 /* Inbound 4GB range s
372 dma-ranges = <0x420000
373
374 /* This drives busses
375 bus-range = <0x20 0x2f
376
377 /* Legacy interrupts (
378 * to invert PCIe lega
379 * We are de-swizzling
380 * port of the root co
381 * to avoid putting a
382 * below are basically
383 * The real slot is on
384 */
385 interrupt-map-mask = <
386 interrupt-map = <
387 0x0 0x0 0x0 0x
388 0x0 0x0 0x0 0x
389 0x0 0x0 0x0 0x
390 0x0 0x0 0x0 0x
391 };
392
393 I2O: i2o@400100000 {
394 compatible = "ibm,i2o-
395 reg = <0x00000004 0x00
396 dcr-reg = <0x060 0x020
397 };
398
399 DMA0: dma0@400100100 {
400 compatible = "ibm,dma-
401 cell-index = <0>;
402 reg = <0x00000004 0x00
403 dcr-reg = <0x060 0x020
404 interrupt-parent = <&D
405 interrupts = <0 1>;
406 #interrupt-cells = <1>
407 #address-cells = <0>;
408 #size-cells = <0>;
409 interrupt-map = <
410 0 &UIC0 0x14 4
411 1 &UIC1 0x16 4
412 };
413
414 DMA1: dma1@400100200 {
415 compatible = "ibm,dma-
416 cell-index = <1>;
417 reg = <0x00000004 0x00
418 dcr-reg = <0x060 0x020
419 interrupt-parent = <&D
420 interrupts = <0 1>;
421 #interrupt-cells = <1>
422 #address-cells = <0>;
423 #size-cells = <0>;
424 interrupt-map = <
425 0 &UIC0 0x16 4
426 1 &UIC1 0x16 4
427 };
428
429 xor-accel@400200000 {
430 compatible = "amcc,xor
431 reg = <0x00000004 0x00
432 interrupt-parent = <&U
433 interrupts = <0x1f 4>;
434 };
435 };
436
437 chosen {
438 stdout-path = "/plb/opb/serial
439 };
440 };
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