1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * Freescale Media5200 board Device Tree Sourc 3 * Freescale Media5200 board Device Tree Source
4 * 4 *
5 * Copyright 2009 Secret Lab Technologies Ltd. 5 * Copyright 2009 Secret Lab Technologies Ltd.
6 * Grant Likely <grant.likely@secretlab.ca> 6 * Grant Likely <grant.likely@secretlab.ca>
7 * Steven Cavanagh <scavanagh@secretlab.ca> 7 * Steven Cavanagh <scavanagh@secretlab.ca>
8 */ 8 */
9 9
10 /include/ "mpc5200b.dtsi" 10 /include/ "mpc5200b.dtsi"
11 11
12 &gpt0 { fsl,has-wdt; }; 12 &gpt0 { fsl,has-wdt; };
13 13
14 / { 14 / {
15 model = "fsl,media5200"; 15 model = "fsl,media5200";
16 compatible = "fsl,media5200"; 16 compatible = "fsl,media5200";
17 17
18 aliases { 18 aliases {
19 console = &console; 19 console = &console;
20 ethernet0 = ð0; 20 ethernet0 = ð0;
21 }; 21 };
22 22
23 chosen { 23 chosen {
24 stdout-path = &console; 24 stdout-path = &console;
25 }; 25 };
26 26
27 cpus { 27 cpus {
28 PowerPC,5200@0 { 28 PowerPC,5200@0 {
29 timebase-frequency = < 29 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
30 bus-frequency = <13200 30 bus-frequency = <132000000>; // 132 MHz
31 clock-frequency = <396 31 clock-frequency = <396000000>; // 396 MHz
32 }; 32 };
33 }; 33 };
34 34
35 memory@0 { 35 memory@0 {
36 reg = <0x00000000 0x08000000>; 36 reg = <0x00000000 0x08000000>; // 128MB RAM
37 }; 37 };
38 38
39 soc5200@f0000000 { 39 soc5200@f0000000 {
40 bus-frequency = <132000000>;// 40 bus-frequency = <132000000>;// 132 MHz
41 41
42 psc@2000 { // PSC1 42 psc@2000 { // PSC1
43 status = "disabled"; 43 status = "disabled";
44 }; 44 };
45 45
46 psc@2200 { // PSC2 46 psc@2200 { // PSC2
47 status = "disabled"; 47 status = "disabled";
48 }; 48 };
49 49
50 psc@2400 { // PSC3 50 psc@2400 { // PSC3
51 status = "disabled"; 51 status = "disabled";
52 }; 52 };
53 53
54 psc@2600 { // PSC4 54 psc@2600 { // PSC4
55 status = "disabled"; 55 status = "disabled";
56 }; 56 };
57 57
58 psc@2800 { // PSC5 58 psc@2800 { // PSC5
59 status = "disabled"; 59 status = "disabled";
60 }; 60 };
61 61
62 // PSC6 in uart mode 62 // PSC6 in uart mode
63 console: psc@2c00 { 63 console: psc@2c00 { // PSC6
64 compatible = "fsl,mpc5 64 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
65 }; 65 };
66 66
67 ethernet@3000 { 67 ethernet@3000 {
68 phy-handle = <&phy0>; 68 phy-handle = <&phy0>;
69 }; 69 };
70 70
71 mdio@3000 { 71 mdio@3000 {
72 phy0: ethernet-phy@0 { 72 phy0: ethernet-phy@0 {
73 reg = <0>; 73 reg = <0>;
74 }; 74 };
75 }; 75 };
76 76
77 usb@1000 { 77 usb@1000 {
78 reg = <0x1000 0x100>; 78 reg = <0x1000 0x100>;
79 }; 79 };
80 }; 80 };
81 81
82 pci@f0000d00 { 82 pci@f0000d00 {
83 interrupt-map-mask = <0xf800 0 83 interrupt-map-mask = <0xf800 0 0 7>;
84 interrupt-map = <0xc000 0 0 1 84 interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
85 0xc000 0 0 2 85 0xc000 0 0 2 &media5200_fpga 0 3
86 0xc000 0 0 3 86 0xc000 0 0 3 &media5200_fpga 0 4
87 0xc000 0 0 4 87 0xc000 0 0 4 &media5200_fpga 0 5
88 88
89 0xc800 0 0 1 89 0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot
90 0xc800 0 0 2 90 0xc800 0 0 2 &media5200_fpga 0 4
91 0xc800 0 0 3 91 0xc800 0 0 3 &media5200_fpga 0 5
92 0xc800 0 0 4 92 0xc800 0 0 4 &media5200_fpga 0 2
93 93
94 0xd000 0 0 1 94 0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI
95 0xd000 0 0 2 95 0xd000 0 0 2 &media5200_fpga 0 5
96 96
97 0xe000 0 0 1 97 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
98 >; 98 >;
99 ranges = <0x42000000 0 0x80000 99 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000>,
100 <0x02000000 0 0xa0000 100 <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000>,
101 <0x01000000 0 0x00000 101 <0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
102 interrupt-parent = <&mpc5200_p 102 interrupt-parent = <&mpc5200_pic>;
103 }; 103 };
104 104
105 localbus { 105 localbus {
106 ranges = < 0 0 0xfc000000 0x02 106 ranges = < 0 0 0xfc000000 0x02000000
107 1 0 0xfe000000 0x02 107 1 0 0xfe000000 0x02000000
108 2 0 0xf0010000 0x00 108 2 0 0xf0010000 0x00010000
109 3 0 0xf0020000 0x00 109 3 0 0xf0020000 0x00010000 >;
110 flash@0,0 { 110 flash@0,0 {
111 compatible = "amd,am29 111 compatible = "amd,am29lv28ml", "cfi-flash";
112 reg = <0 0x0 0x2000000 112 reg = <0 0x0 0x2000000>; // 32 MB
113 bank-width = <4>; 113 bank-width = <4>; // Width in bytes of the flash bank
114 device-width = <2>; 114 device-width = <2>; // Two devices on each bank
115 }; 115 };
116 116
117 flash@1,0 { 117 flash@1,0 {
118 compatible = "amd,am29 118 compatible = "amd,am29lv28ml", "cfi-flash";
119 reg = <1 0 0x2000000>; 119 reg = <1 0 0x2000000>; // 32 MB
120 bank-width = <4>; 120 bank-width = <4>; // Width in bytes of the flash bank
121 device-width = <2>; 121 device-width = <2>; // Two devices on each bank
122 }; 122 };
123 123
124 media5200_fpga: fpga@2,0 { 124 media5200_fpga: fpga@2,0 {
125 compatible = "fsl,medi 125 compatible = "fsl,media5200-fpga";
126 interrupt-controller; 126 interrupt-controller;
127 #interrupt-cells = <2> 127 #interrupt-cells = <2>; // 0:bank 1:id; no type field
128 reg = <2 0 0x10000>; 128 reg = <2 0 0x10000>;
129 129
130 interrupt-parent = <&m 130 interrupt-parent = <&mpc5200_pic>;
131 interrupts = <0 0 3 131 interrupts = <0 0 3 // IRQ bank 0
132 1 1 3>; 132 1 1 3>; // IRQ bank 1
133 }; 133 };
134 134
135 uart@3,0 { 135 uart@3,0 {
136 compatible = "ti,tl16c 136 compatible = "ti,tl16c752bpt";
137 reg = <3 0 0x10000>; 137 reg = <3 0 0x10000>;
138 interrupt-parent = <&m 138 interrupt-parent = <&media5200_fpga>;
139 interrupts = <0 0 0 1 139 interrupts = <0 0 0 1>; // 2 irqs
140 }; 140 };
141 }; 141 };
142 }; 142 };
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