1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * base MPC5121 Device Tree Source 3 * base MPC5121 Device Tree Source
4 * 4 *
5 * Copyright 2007-2008 Freescale Semiconductor 5 * Copyright 2007-2008 Freescale Semiconductor Inc.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/mpc512x-clock.h> 8 #include <dt-bindings/clock/mpc512x-clock.h>
9 9
10 /dts-v1/; 10 /dts-v1/;
11 11
12 / { 12 / {
13 model = "mpc5121"; 13 model = "mpc5121";
14 compatible = "fsl,mpc5121"; 14 compatible = "fsl,mpc5121";
15 #address-cells = <1>; 15 #address-cells = <1>;
16 #size-cells = <1>; 16 #size-cells = <1>;
17 interrupt-parent = <&ipic>; 17 interrupt-parent = <&ipic>;
18 18
19 aliases { 19 aliases {
20 ethernet0 = ð0; 20 ethernet0 = ð0;
21 pci = &pci; 21 pci = &pci;
22 }; 22 };
23 23
24 cpus { 24 cpus {
25 #address-cells = <1>; 25 #address-cells = <1>;
26 #size-cells = <0>; 26 #size-cells = <0>;
27 27
28 PowerPC,5121@0 { 28 PowerPC,5121@0 {
29 device_type = "cpu"; 29 device_type = "cpu";
30 reg = <0>; 30 reg = <0>;
31 d-cache-line-size = <0 31 d-cache-line-size = <0x20>; /* 32 bytes */
32 i-cache-line-size = <0 32 i-cache-line-size = <0x20>; /* 32 bytes */
33 d-cache-size = <0x8000 33 d-cache-size = <0x8000>; /* L1, 32K */
34 i-cache-size = <0x8000 34 i-cache-size = <0x8000>; /* L1, 32K */
35 timebase-frequency = < 35 timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */
36 bus-frequency = <19800 36 bus-frequency = <198000000>; /* 198 MHz csb bus */
37 clock-frequency = <396 37 clock-frequency = <396000000>; /* 396 MHz ppc core */
38 }; 38 };
39 }; 39 };
40 40
41 memory { 41 memory {
42 device_type = "memory"; 42 device_type = "memory";
43 reg = <0x00000000 0x10000000>; 43 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
44 }; 44 };
45 45
46 mbx@20000000 { 46 mbx@20000000 {
47 compatible = "fsl,mpc5121-mbx" 47 compatible = "fsl,mpc5121-mbx";
48 reg = <0x20000000 0x4000>; 48 reg = <0x20000000 0x4000>;
49 interrupts = <66 0x8>; 49 interrupts = <66 0x8>;
50 clocks = <&clks MPC512x_CLK_MB 50 clocks = <&clks MPC512x_CLK_MBX_BUS>,
51 <&clks MPC512x_CLK_MB 51 <&clks MPC512x_CLK_MBX_3D>,
52 <&clks MPC512x_CLK_MB 52 <&clks MPC512x_CLK_MBX>;
53 clock-names = "mbx-bus", "mbx- 53 clock-names = "mbx-bus", "mbx-3d", "mbx";
54 }; 54 };
55 55
56 sram@30000000 { 56 sram@30000000 {
57 compatible = "fsl,mpc5121-sram 57 compatible = "fsl,mpc5121-sram";
58 reg = <0x30000000 0x20000>; 58 reg = <0x30000000 0x20000>; /* 128K at 0x30000000 */
59 }; 59 };
60 60
61 nfc@40000000 { 61 nfc@40000000 {
62 compatible = "fsl,mpc5121-nfc" 62 compatible = "fsl,mpc5121-nfc";
63 reg = <0x40000000 0x100000>; 63 reg = <0x40000000 0x100000>; /* 1M at 0x40000000 */
64 interrupts = <6 8>; 64 interrupts = <6 8>;
65 #address-cells = <1>; 65 #address-cells = <1>;
66 #size-cells = <1>; 66 #size-cells = <1>;
67 clocks = <&clks MPC512x_CLK_NF 67 clocks = <&clks MPC512x_CLK_NFC>;
68 clock-names = "ipg"; 68 clock-names = "ipg";
69 }; 69 };
70 70
71 localbus@80000020 { 71 localbus@80000020 {
72 compatible = "fsl,mpc5121-loca 72 compatible = "fsl,mpc5121-localbus";
73 #address-cells = <2>; 73 #address-cells = <2>;
74 #size-cells = <1>; 74 #size-cells = <1>;
75 reg = <0x80000020 0x40>; 75 reg = <0x80000020 0x40>;
76 ranges = <0x0 0x0 0xfc000000 0 76 ranges = <0x0 0x0 0xfc000000 0x04000000>;
77 }; 77 };
78 78
79 clocks { 79 clocks {
80 #address-cells = <1>; 80 #address-cells = <1>;
81 #size-cells = <0>; 81 #size-cells = <0>;
82 82
83 osc: osc { 83 osc: osc {
84 compatible = "fixed-cl 84 compatible = "fixed-clock";
85 #clock-cells = <0>; 85 #clock-cells = <0>;
86 clock-frequency = <330 86 clock-frequency = <33000000>;
87 }; 87 };
88 }; 88 };
89 89
90 soc@80000000 { 90 soc@80000000 {
91 compatible = "fsl,mpc5121-immr 91 compatible = "fsl,mpc5121-immr";
92 #address-cells = <1>; 92 #address-cells = <1>;
93 #size-cells = <1>; 93 #size-cells = <1>;
94 ranges = <0x0 0x80000000 0x400 94 ranges = <0x0 0x80000000 0x400000>;
95 reg = <0x80000000 0x400000>; 95 reg = <0x80000000 0x400000>;
96 bus-frequency = <66000000>; 96 bus-frequency = <66000000>; /* 66 MHz ips bus */
97 97
98 98
99 /* 99 /*
100 * IPIC 100 * IPIC
101 * interrupts cell = <intr #, 101 * interrupts cell = <intr #, sense>
102 * sense values match linux IO 102 * sense values match linux IORESOURCE_IRQ_* defines:
103 * sense == 8: Level, low asse 103 * sense == 8: Level, low assertion
104 * sense == 2: Edge, high-to-l 104 * sense == 2: Edge, high-to-low change
105 */ 105 */
106 ipic: interrupt-controller@c00 106 ipic: interrupt-controller@c00 {
107 compatible = "fsl,mpc5 107 compatible = "fsl,mpc5121-ipic", "fsl,ipic";
108 interrupt-controller; 108 interrupt-controller;
109 #address-cells = <0>; 109 #address-cells = <0>;
110 #interrupt-cells = <2> 110 #interrupt-cells = <2>;
111 reg = <0xc00 0x100>; 111 reg = <0xc00 0x100>;
112 }; 112 };
113 113
114 /* Watchdog timer */ 114 /* Watchdog timer */
115 wdt@900 { 115 wdt@900 {
116 compatible = "fsl,mpc5 116 compatible = "fsl,mpc5121-wdt";
117 reg = <0x900 0x100>; 117 reg = <0x900 0x100>;
118 }; 118 };
119 119
120 /* Real time clock */ 120 /* Real time clock */
121 rtc@a00 { 121 rtc@a00 {
122 compatible = "fsl,mpc5 122 compatible = "fsl,mpc5121-rtc";
123 reg = <0xa00 0x100>; 123 reg = <0xa00 0x100>;
124 interrupts = <79 0x8 8 124 interrupts = <79 0x8 80 0x8>;
125 }; 125 };
126 126
127 /* Reset module */ 127 /* Reset module */
128 reset@e00 { 128 reset@e00 {
129 compatible = "fsl,mpc5 129 compatible = "fsl,mpc5121-reset";
130 reg = <0xe00 0x100>; 130 reg = <0xe00 0x100>;
131 }; 131 };
132 132
133 /* Clock control */ 133 /* Clock control */
134 clks: clock@f00 { 134 clks: clock@f00 {
135 compatible = "fsl,mpc5 135 compatible = "fsl,mpc5121-clock";
136 reg = <0xf00 0x100>; 136 reg = <0xf00 0x100>;
137 #clock-cells = <1>; 137 #clock-cells = <1>;
138 clocks = <&osc>; 138 clocks = <&osc>;
139 clock-names = "osc"; 139 clock-names = "osc";
140 }; 140 };
141 141
142 /* Power Management Controller 142 /* Power Management Controller */
143 pmc@1000 { 143 pmc@1000 {
144 compatible = "fsl,mpc5 144 compatible = "fsl,mpc5121-pmc";
145 reg = <0x1000 0x100>; 145 reg = <0x1000 0x100>;
146 interrupts = <83 0x8>; 146 interrupts = <83 0x8>;
147 }; 147 };
148 148
149 gpio@1100 { 149 gpio@1100 {
150 compatible = "fsl,mpc5 150 compatible = "fsl,mpc5121-gpio";
151 reg = <0x1100 0x100>; 151 reg = <0x1100 0x100>;
152 interrupts = <78 0x8>; 152 interrupts = <78 0x8>;
153 }; 153 };
154 154
155 can@1300 { 155 can@1300 {
156 compatible = "fsl,mpc5 156 compatible = "fsl,mpc5121-mscan";
157 reg = <0x1300 0x80>; 157 reg = <0x1300 0x80>;
158 interrupts = <12 0x8>; 158 interrupts = <12 0x8>;
159 clocks = <&clks MPC512 159 clocks = <&clks MPC512x_CLK_BDLC>,
160 <&clks MPC512 160 <&clks MPC512x_CLK_IPS>,
161 <&clks MPC512 161 <&clks MPC512x_CLK_SYS>,
162 <&clks MPC512 162 <&clks MPC512x_CLK_REF>,
163 <&clks MPC512 163 <&clks MPC512x_CLK_MSCAN0_MCLK>;
164 clock-names = "ipg", " 164 clock-names = "ipg", "ips", "sys", "ref", "mclk";
165 }; 165 };
166 166
167 can@1380 { 167 can@1380 {
168 compatible = "fsl,mpc5 168 compatible = "fsl,mpc5121-mscan";
169 reg = <0x1380 0x80>; 169 reg = <0x1380 0x80>;
170 interrupts = <13 0x8>; 170 interrupts = <13 0x8>;
171 clocks = <&clks MPC512 171 clocks = <&clks MPC512x_CLK_BDLC>,
172 <&clks MPC512 172 <&clks MPC512x_CLK_IPS>,
173 <&clks MPC512 173 <&clks MPC512x_CLK_SYS>,
174 <&clks MPC512 174 <&clks MPC512x_CLK_REF>,
175 <&clks MPC512 175 <&clks MPC512x_CLK_MSCAN1_MCLK>;
176 clock-names = "ipg", " 176 clock-names = "ipg", "ips", "sys", "ref", "mclk";
177 }; 177 };
178 178
179 sdhc@1500 { 179 sdhc@1500 {
180 compatible = "fsl,mpc5 180 compatible = "fsl,mpc5121-sdhc";
181 reg = <0x1500 0x100>; 181 reg = <0x1500 0x100>;
182 interrupts = <8 0x8>; 182 interrupts = <8 0x8>;
183 dmas = <&dma0 30>; 183 dmas = <&dma0 30>;
184 dma-names = "rx-tx"; 184 dma-names = "rx-tx";
185 clocks = <&clks MPC512 185 clocks = <&clks MPC512x_CLK_IPS>,
186 <&clks MPC512 186 <&clks MPC512x_CLK_SDHC>;
187 clock-names = "ipg", " 187 clock-names = "ipg", "per";
188 }; 188 };
189 189
190 i2c@1700 { 190 i2c@1700 {
191 #address-cells = <1>; 191 #address-cells = <1>;
192 #size-cells = <0>; 192 #size-cells = <0>;
193 compatible = "fsl,mpc5 193 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
194 reg = <0x1700 0x20>; 194 reg = <0x1700 0x20>;
195 interrupts = <9 0x8>; 195 interrupts = <9 0x8>;
196 clocks = <&clks MPC512 196 clocks = <&clks MPC512x_CLK_I2C>;
197 clock-names = "ipg"; 197 clock-names = "ipg";
198 }; 198 };
199 199
200 i2c@1720 { 200 i2c@1720 {
201 #address-cells = <1>; 201 #address-cells = <1>;
202 #size-cells = <0>; 202 #size-cells = <0>;
203 compatible = "fsl,mpc5 203 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
204 reg = <0x1720 0x20>; 204 reg = <0x1720 0x20>;
205 interrupts = <10 0x8>; 205 interrupts = <10 0x8>;
206 clocks = <&clks MPC512 206 clocks = <&clks MPC512x_CLK_I2C>;
207 clock-names = "ipg"; 207 clock-names = "ipg";
208 }; 208 };
209 209
210 i2c@1740 { 210 i2c@1740 {
211 #address-cells = <1>; 211 #address-cells = <1>;
212 #size-cells = <0>; 212 #size-cells = <0>;
213 compatible = "fsl,mpc5 213 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
214 reg = <0x1740 0x20>; 214 reg = <0x1740 0x20>;
215 interrupts = <11 0x8>; 215 interrupts = <11 0x8>;
216 clocks = <&clks MPC512 216 clocks = <&clks MPC512x_CLK_I2C>;
217 clock-names = "ipg"; 217 clock-names = "ipg";
218 }; 218 };
219 219
220 i2ccontrol@1760 { 220 i2ccontrol@1760 {
221 compatible = "fsl,mpc5 221 compatible = "fsl,mpc5121-i2c-ctrl";
222 reg = <0x1760 0x8>; 222 reg = <0x1760 0x8>;
223 }; 223 };
224 224
225 axe@2000 { 225 axe@2000 {
226 compatible = "fsl,mpc5 226 compatible = "fsl,mpc5121-axe";
227 reg = <0x2000 0x100>; 227 reg = <0x2000 0x100>;
228 interrupts = <42 0x8>; 228 interrupts = <42 0x8>;
229 clocks = <&clks MPC512 229 clocks = <&clks MPC512x_CLK_AXE>;
230 clock-names = "ipg"; 230 clock-names = "ipg";
231 }; 231 };
232 232
233 display@2100 { 233 display@2100 {
234 compatible = "fsl,mpc5 234 compatible = "fsl,mpc5121-diu";
235 reg = <0x2100 0x100>; 235 reg = <0x2100 0x100>;
236 interrupts = <64 0x8>; 236 interrupts = <64 0x8>;
237 clocks = <&clks MPC512 237 clocks = <&clks MPC512x_CLK_DIU>;
238 clock-names = "ipg"; 238 clock-names = "ipg";
239 }; 239 };
240 240
241 can@2300 { 241 can@2300 {
242 compatible = "fsl,mpc5 242 compatible = "fsl,mpc5121-mscan";
243 reg = <0x2300 0x80>; 243 reg = <0x2300 0x80>;
244 interrupts = <90 0x8>; 244 interrupts = <90 0x8>;
245 clocks = <&clks MPC512 245 clocks = <&clks MPC512x_CLK_BDLC>,
246 <&clks MPC512 246 <&clks MPC512x_CLK_IPS>,
247 <&clks MPC512 247 <&clks MPC512x_CLK_SYS>,
248 <&clks MPC512 248 <&clks MPC512x_CLK_REF>,
249 <&clks MPC512 249 <&clks MPC512x_CLK_MSCAN2_MCLK>;
250 clock-names = "ipg", " 250 clock-names = "ipg", "ips", "sys", "ref", "mclk";
251 }; 251 };
252 252
253 can@2380 { 253 can@2380 {
254 compatible = "fsl,mpc5 254 compatible = "fsl,mpc5121-mscan";
255 reg = <0x2380 0x80>; 255 reg = <0x2380 0x80>;
256 interrupts = <91 0x8>; 256 interrupts = <91 0x8>;
257 clocks = <&clks MPC512 257 clocks = <&clks MPC512x_CLK_BDLC>,
258 <&clks MPC512 258 <&clks MPC512x_CLK_IPS>,
259 <&clks MPC512 259 <&clks MPC512x_CLK_SYS>,
260 <&clks MPC512 260 <&clks MPC512x_CLK_REF>,
261 <&clks MPC512 261 <&clks MPC512x_CLK_MSCAN3_MCLK>;
262 clock-names = "ipg", " 262 clock-names = "ipg", "ips", "sys", "ref", "mclk";
263 }; 263 };
264 264
265 viu@2400 { 265 viu@2400 {
266 compatible = "fsl,mpc5 266 compatible = "fsl,mpc5121-viu";
267 reg = <0x2400 0x400>; 267 reg = <0x2400 0x400>;
268 interrupts = <67 0x8>; 268 interrupts = <67 0x8>;
269 clocks = <&clks MPC512 269 clocks = <&clks MPC512x_CLK_VIU>;
270 clock-names = "ipg"; 270 clock-names = "ipg";
271 }; 271 };
272 272
273 mdio@2800 { 273 mdio@2800 {
274 compatible = "fsl,mpc5 274 compatible = "fsl,mpc5121-fec-mdio";
275 reg = <0x2800 0x800>; 275 reg = <0x2800 0x800>;
276 #address-cells = <1>; 276 #address-cells = <1>;
277 #size-cells = <0>; 277 #size-cells = <0>;
278 clocks = <&clks MPC512 278 clocks = <&clks MPC512x_CLK_FEC>;
279 clock-names = "per"; 279 clock-names = "per";
280 }; 280 };
281 281
282 eth0: ethernet@2800 { 282 eth0: ethernet@2800 {
283 device_type = "network 283 device_type = "network";
284 compatible = "fsl,mpc5 284 compatible = "fsl,mpc5121-fec";
285 reg = <0x2800 0x800>; 285 reg = <0x2800 0x800>;
286 local-mac-address = [ 286 local-mac-address = [ 00 00 00 00 00 00 ];
287 interrupts = <4 0x8>; 287 interrupts = <4 0x8>;
288 clocks = <&clks MPC512 288 clocks = <&clks MPC512x_CLK_FEC>;
289 clock-names = "per"; 289 clock-names = "per";
290 }; 290 };
291 291
292 /* USB1 using external ULPI PH 292 /* USB1 using external ULPI PHY */
293 usb@3000 { 293 usb@3000 {
294 compatible = "fsl,mpc5 294 compatible = "fsl,mpc5121-usb2-dr";
295 reg = <0x3000 0x600>; 295 reg = <0x3000 0x600>;
296 #address-cells = <1>; 296 #address-cells = <1>;
297 #size-cells = <0>; 297 #size-cells = <0>;
298 interrupts = <43 0x8>; 298 interrupts = <43 0x8>;
299 dr_mode = "otg"; 299 dr_mode = "otg";
300 phy_type = "ulpi"; 300 phy_type = "ulpi";
301 clocks = <&clks MPC512 301 clocks = <&clks MPC512x_CLK_USB1>;
302 clock-names = "ipg"; 302 clock-names = "ipg";
303 }; 303 };
304 304
305 /* USB0 using internal UTMI PH 305 /* USB0 using internal UTMI PHY */
306 usb@4000 { 306 usb@4000 {
307 compatible = "fsl,mpc5 307 compatible = "fsl,mpc5121-usb2-dr";
308 reg = <0x4000 0x600>; 308 reg = <0x4000 0x600>;
309 #address-cells = <1>; 309 #address-cells = <1>;
310 #size-cells = <0>; 310 #size-cells = <0>;
311 interrupts = <44 0x8>; 311 interrupts = <44 0x8>;
312 dr_mode = "otg"; 312 dr_mode = "otg";
313 phy_type = "utmi_wide" 313 phy_type = "utmi_wide";
314 clocks = <&clks MPC512 314 clocks = <&clks MPC512x_CLK_USB2>;
315 clock-names = "ipg"; 315 clock-names = "ipg";
316 }; 316 };
317 317
318 /* IO control */ 318 /* IO control */
319 ioctl@a000 { 319 ioctl@a000 {
320 compatible = "fsl,mpc5 320 compatible = "fsl,mpc5121-ioctl";
321 reg = <0xA000 0x1000>; 321 reg = <0xA000 0x1000>;
322 }; 322 };
323 323
324 /* LocalPlus controller */ 324 /* LocalPlus controller */
325 lpc@10000 { 325 lpc@10000 {
326 compatible = "fsl,mpc5 326 compatible = "fsl,mpc5121-lpc";
327 reg = <0x10000 0x100>; 327 reg = <0x10000 0x100>;
328 }; 328 };
329 329
330 sclpc@10100 { 330 sclpc@10100 {
331 compatible = "fsl,mpc5 331 compatible = "fsl,mpc512x-lpbfifo";
332 reg = <0x10100 0x50>; 332 reg = <0x10100 0x50>;
333 interrupts = <7 0x8>; 333 interrupts = <7 0x8>;
334 dmas = <&dma0 26>; 334 dmas = <&dma0 26>;
335 dma-names = "rx-tx"; 335 dma-names = "rx-tx";
336 }; 336 };
337 337
338 pata@10200 { 338 pata@10200 {
339 compatible = "fsl,mpc5 339 compatible = "fsl,mpc5121-pata";
340 reg = <0x10200 0x100>; 340 reg = <0x10200 0x100>;
341 interrupts = <5 0x8>; 341 interrupts = <5 0x8>;
342 clocks = <&clks MPC512 342 clocks = <&clks MPC512x_CLK_PATA>;
343 clock-names = "ipg"; 343 clock-names = "ipg";
344 }; 344 };
345 345
346 /* 512x PSCs are not 52xx PSC 346 /* 512x PSCs are not 52xx PSC compatible */
347 347
348 /* PSC0 */ 348 /* PSC0 */
349 psc@11000 { 349 psc@11000 {
350 compatible = "fsl,mpc5 350 compatible = "fsl,mpc5121-psc";
351 reg = <0x11000 0x100>; 351 reg = <0x11000 0x100>;
352 interrupts = <40 0x8>; 352 interrupts = <40 0x8>;
353 fsl,rx-fifo-size = <16 353 fsl,rx-fifo-size = <16>;
354 fsl,tx-fifo-size = <16 354 fsl,tx-fifo-size = <16>;
355 clocks = <&clks MPC512 355 clocks = <&clks MPC512x_CLK_PSC0>,
356 <&clks MPC512 356 <&clks MPC512x_CLK_PSC0_MCLK>;
357 clock-names = "ipg", " 357 clock-names = "ipg", "mclk";
358 }; 358 };
359 359
360 /* PSC1 */ 360 /* PSC1 */
361 psc@11100 { 361 psc@11100 {
362 compatible = "fsl,mpc5 362 compatible = "fsl,mpc5121-psc";
363 reg = <0x11100 0x100>; 363 reg = <0x11100 0x100>;
364 interrupts = <40 0x8>; 364 interrupts = <40 0x8>;
365 fsl,rx-fifo-size = <16 365 fsl,rx-fifo-size = <16>;
366 fsl,tx-fifo-size = <16 366 fsl,tx-fifo-size = <16>;
367 clocks = <&clks MPC512 367 clocks = <&clks MPC512x_CLK_PSC1>,
368 <&clks MPC512 368 <&clks MPC512x_CLK_PSC1_MCLK>;
369 clock-names = "ipg", " 369 clock-names = "ipg", "mclk";
370 }; 370 };
371 371
372 /* PSC2 */ 372 /* PSC2 */
373 psc@11200 { 373 psc@11200 {
374 compatible = "fsl,mpc5 374 compatible = "fsl,mpc5121-psc";
375 reg = <0x11200 0x100>; 375 reg = <0x11200 0x100>;
376 interrupts = <40 0x8>; 376 interrupts = <40 0x8>;
377 fsl,rx-fifo-size = <16 377 fsl,rx-fifo-size = <16>;
378 fsl,tx-fifo-size = <16 378 fsl,tx-fifo-size = <16>;
379 clocks = <&clks MPC512 379 clocks = <&clks MPC512x_CLK_PSC2>,
380 <&clks MPC512 380 <&clks MPC512x_CLK_PSC2_MCLK>;
381 clock-names = "ipg", " 381 clock-names = "ipg", "mclk";
382 }; 382 };
383 383
384 /* PSC3 */ 384 /* PSC3 */
385 psc@11300 { 385 psc@11300 {
386 compatible = "fsl,mpc5 386 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
387 reg = <0x11300 0x100>; 387 reg = <0x11300 0x100>;
388 interrupts = <40 0x8>; 388 interrupts = <40 0x8>;
389 fsl,rx-fifo-size = <16 389 fsl,rx-fifo-size = <16>;
390 fsl,tx-fifo-size = <16 390 fsl,tx-fifo-size = <16>;
391 clocks = <&clks MPC512 391 clocks = <&clks MPC512x_CLK_PSC3>,
392 <&clks MPC512 392 <&clks MPC512x_CLK_PSC3_MCLK>;
393 clock-names = "ipg", " 393 clock-names = "ipg", "mclk";
394 }; 394 };
395 395
396 /* PSC4 */ 396 /* PSC4 */
397 psc@11400 { 397 psc@11400 {
398 compatible = "fsl,mpc5 398 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
399 reg = <0x11400 0x100>; 399 reg = <0x11400 0x100>;
400 interrupts = <40 0x8>; 400 interrupts = <40 0x8>;
401 fsl,rx-fifo-size = <16 401 fsl,rx-fifo-size = <16>;
402 fsl,tx-fifo-size = <16 402 fsl,tx-fifo-size = <16>;
403 clocks = <&clks MPC512 403 clocks = <&clks MPC512x_CLK_PSC4>,
404 <&clks MPC512 404 <&clks MPC512x_CLK_PSC4_MCLK>;
405 clock-names = "ipg", " 405 clock-names = "ipg", "mclk";
406 }; 406 };
407 407
408 /* PSC5 */ 408 /* PSC5 */
409 psc@11500 { 409 psc@11500 {
410 compatible = "fsl,mpc5 410 compatible = "fsl,mpc5121-psc";
411 reg = <0x11500 0x100>; 411 reg = <0x11500 0x100>;
412 interrupts = <40 0x8>; 412 interrupts = <40 0x8>;
413 fsl,rx-fifo-size = <16 413 fsl,rx-fifo-size = <16>;
414 fsl,tx-fifo-size = <16 414 fsl,tx-fifo-size = <16>;
415 clocks = <&clks MPC512 415 clocks = <&clks MPC512x_CLK_PSC5>,
416 <&clks MPC512 416 <&clks MPC512x_CLK_PSC5_MCLK>;
417 clock-names = "ipg", " 417 clock-names = "ipg", "mclk";
418 }; 418 };
419 419
420 /* PSC6 */ 420 /* PSC6 */
421 psc@11600 { 421 psc@11600 {
422 compatible = "fsl,mpc5 422 compatible = "fsl,mpc5121-psc";
423 reg = <0x11600 0x100>; 423 reg = <0x11600 0x100>;
424 interrupts = <40 0x8>; 424 interrupts = <40 0x8>;
425 fsl,rx-fifo-size = <16 425 fsl,rx-fifo-size = <16>;
426 fsl,tx-fifo-size = <16 426 fsl,tx-fifo-size = <16>;
427 clocks = <&clks MPC512 427 clocks = <&clks MPC512x_CLK_PSC6>,
428 <&clks MPC512 428 <&clks MPC512x_CLK_PSC6_MCLK>;
429 clock-names = "ipg", " 429 clock-names = "ipg", "mclk";
430 }; 430 };
431 431
432 /* PSC7 */ 432 /* PSC7 */
433 psc@11700 { 433 psc@11700 {
434 compatible = "fsl,mpc5 434 compatible = "fsl,mpc5121-psc";
435 reg = <0x11700 0x100>; 435 reg = <0x11700 0x100>;
436 interrupts = <40 0x8>; 436 interrupts = <40 0x8>;
437 fsl,rx-fifo-size = <16 437 fsl,rx-fifo-size = <16>;
438 fsl,tx-fifo-size = <16 438 fsl,tx-fifo-size = <16>;
439 clocks = <&clks MPC512 439 clocks = <&clks MPC512x_CLK_PSC7>,
440 <&clks MPC512 440 <&clks MPC512x_CLK_PSC7_MCLK>;
441 clock-names = "ipg", " 441 clock-names = "ipg", "mclk";
442 }; 442 };
443 443
444 /* PSC8 */ 444 /* PSC8 */
445 psc@11800 { 445 psc@11800 {
446 compatible = "fsl,mpc5 446 compatible = "fsl,mpc5121-psc";
447 reg = <0x11800 0x100>; 447 reg = <0x11800 0x100>;
448 interrupts = <40 0x8>; 448 interrupts = <40 0x8>;
449 fsl,rx-fifo-size = <16 449 fsl,rx-fifo-size = <16>;
450 fsl,tx-fifo-size = <16 450 fsl,tx-fifo-size = <16>;
451 clocks = <&clks MPC512 451 clocks = <&clks MPC512x_CLK_PSC8>,
452 <&clks MPC512 452 <&clks MPC512x_CLK_PSC8_MCLK>;
453 clock-names = "ipg", " 453 clock-names = "ipg", "mclk";
454 }; 454 };
455 455
456 /* PSC9 */ 456 /* PSC9 */
457 psc@11900 { 457 psc@11900 {
458 compatible = "fsl,mpc5 458 compatible = "fsl,mpc5121-psc";
459 reg = <0x11900 0x100>; 459 reg = <0x11900 0x100>;
460 interrupts = <40 0x8>; 460 interrupts = <40 0x8>;
461 fsl,rx-fifo-size = <16 461 fsl,rx-fifo-size = <16>;
462 fsl,tx-fifo-size = <16 462 fsl,tx-fifo-size = <16>;
463 clocks = <&clks MPC512 463 clocks = <&clks MPC512x_CLK_PSC9>,
464 <&clks MPC512 464 <&clks MPC512x_CLK_PSC9_MCLK>;
465 clock-names = "ipg", " 465 clock-names = "ipg", "mclk";
466 }; 466 };
467 467
468 /* PSC10 */ 468 /* PSC10 */
469 psc@11a00 { 469 psc@11a00 {
470 compatible = "fsl,mpc5 470 compatible = "fsl,mpc5121-psc";
471 reg = <0x11a00 0x100>; 471 reg = <0x11a00 0x100>;
472 interrupts = <40 0x8>; 472 interrupts = <40 0x8>;
473 fsl,rx-fifo-size = <16 473 fsl,rx-fifo-size = <16>;
474 fsl,tx-fifo-size = <16 474 fsl,tx-fifo-size = <16>;
475 clocks = <&clks MPC512 475 clocks = <&clks MPC512x_CLK_PSC10>,
476 <&clks MPC512 476 <&clks MPC512x_CLK_PSC10_MCLK>;
477 clock-names = "ipg", " 477 clock-names = "ipg", "mclk";
478 }; 478 };
479 479
480 /* PSC11 */ 480 /* PSC11 */
481 psc@11b00 { 481 psc@11b00 {
482 compatible = "fsl,mpc5 482 compatible = "fsl,mpc5121-psc";
483 reg = <0x11b00 0x100>; 483 reg = <0x11b00 0x100>;
484 interrupts = <40 0x8>; 484 interrupts = <40 0x8>;
485 fsl,rx-fifo-size = <16 485 fsl,rx-fifo-size = <16>;
486 fsl,tx-fifo-size = <16 486 fsl,tx-fifo-size = <16>;
487 clocks = <&clks MPC512 487 clocks = <&clks MPC512x_CLK_PSC11>,
488 <&clks MPC512 488 <&clks MPC512x_CLK_PSC11_MCLK>;
489 clock-names = "ipg", " 489 clock-names = "ipg", "mclk";
490 }; 490 };
491 491
492 pscfifo@11f00 { 492 pscfifo@11f00 {
493 compatible = "fsl,mpc5 493 compatible = "fsl,mpc5121-psc-fifo";
494 reg = <0x11f00 0x100>; 494 reg = <0x11f00 0x100>;
495 interrupts = <40 0x8>; 495 interrupts = <40 0x8>;
496 clocks = <&clks MPC512 496 clocks = <&clks MPC512x_CLK_PSC_FIFO>;
497 clock-names = "ipg"; 497 clock-names = "ipg";
498 }; 498 };
499 499
500 dma0: dma@14000 { 500 dma0: dma@14000 {
501 compatible = "fsl,mpc5 501 compatible = "fsl,mpc5121-dma";
502 reg = <0x14000 0x1800> 502 reg = <0x14000 0x1800>;
503 interrupts = <65 0x8>; 503 interrupts = <65 0x8>;
504 #dma-cells = <1>; 504 #dma-cells = <1>;
505 }; 505 };
506 }; 506 };
507 507
508 pci: pci@80008500 { 508 pci: pci@80008500 {
509 compatible = "fsl,mpc5121-pci" 509 compatible = "fsl,mpc5121-pci";
510 device_type = "pci"; 510 device_type = "pci";
511 interrupts = <1 0x8>; 511 interrupts = <1 0x8>;
512 clock-frequency = <0>; 512 clock-frequency = <0>;
513 #address-cells = <3>; 513 #address-cells = <3>;
514 #size-cells = <2>; 514 #size-cells = <2>;
515 #interrupt-cells = <1>; 515 #interrupt-cells = <1>;
516 clocks = <&clks MPC512x_CLK_PC 516 clocks = <&clks MPC512x_CLK_PCI>;
517 clock-names = "ipg"; 517 clock-names = "ipg";
518 518
519 reg = <0x80008500 0x100 /* int 519 reg = <0x80008500 0x100 /* internal registers */
520 0x80008300 0x8>; /* con 520 0x80008300 0x8>; /* config space access registers */
521 bus-range = <0x0 0x0>; 521 bus-range = <0x0 0x0>;
522 ranges = <0x42000000 0x0 0xa00 522 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
523 0x02000000 0x0 0xb00 523 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
524 0x01000000 0x0 0x000 524 0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
525 }; 525 };
526 }; 526 };
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