1 // SPDX-License-Identifier: GPL-2.0-or-later <<
2 /* 1 /*
3 * base MPC5121 Device Tree Source 2 * base MPC5121 Device Tree Source
4 * 3 *
5 * Copyright 2007-2008 Freescale Semiconductor 4 * Copyright 2007-2008 Freescale Semiconductor Inc.
>> 5 *
>> 6 * This program is free software; you can redistribute it and/or modify it
>> 7 * under the terms of the GNU General Public License as published by the
>> 8 * Free Software Foundation; either version 2 of the License, or (at your
>> 9 * option) any later version.
6 */ 10 */
7 11
8 #include <dt-bindings/clock/mpc512x-clock.h> 12 #include <dt-bindings/clock/mpc512x-clock.h>
9 13
10 /dts-v1/; 14 /dts-v1/;
11 15
12 / { 16 / {
13 model = "mpc5121"; 17 model = "mpc5121";
14 compatible = "fsl,mpc5121"; 18 compatible = "fsl,mpc5121";
15 #address-cells = <1>; 19 #address-cells = <1>;
16 #size-cells = <1>; 20 #size-cells = <1>;
17 interrupt-parent = <&ipic>; 21 interrupt-parent = <&ipic>;
18 22
19 aliases { 23 aliases {
20 ethernet0 = ð0; 24 ethernet0 = ð0;
21 pci = &pci; 25 pci = &pci;
22 }; 26 };
23 27
24 cpus { 28 cpus {
25 #address-cells = <1>; 29 #address-cells = <1>;
26 #size-cells = <0>; 30 #size-cells = <0>;
27 31
28 PowerPC,5121@0 { 32 PowerPC,5121@0 {
29 device_type = "cpu"; 33 device_type = "cpu";
30 reg = <0>; 34 reg = <0>;
31 d-cache-line-size = <0 35 d-cache-line-size = <0x20>; /* 32 bytes */
32 i-cache-line-size = <0 36 i-cache-line-size = <0x20>; /* 32 bytes */
33 d-cache-size = <0x8000 37 d-cache-size = <0x8000>; /* L1, 32K */
34 i-cache-size = <0x8000 38 i-cache-size = <0x8000>; /* L1, 32K */
35 timebase-frequency = < 39 timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */
36 bus-frequency = <19800 40 bus-frequency = <198000000>; /* 198 MHz csb bus */
37 clock-frequency = <396 41 clock-frequency = <396000000>; /* 396 MHz ppc core */
38 }; 42 };
39 }; 43 };
40 44
41 memory { 45 memory {
42 device_type = "memory"; 46 device_type = "memory";
43 reg = <0x00000000 0x10000000>; 47 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
44 }; 48 };
45 49
46 mbx@20000000 { 50 mbx@20000000 {
47 compatible = "fsl,mpc5121-mbx" 51 compatible = "fsl,mpc5121-mbx";
48 reg = <0x20000000 0x4000>; 52 reg = <0x20000000 0x4000>;
49 interrupts = <66 0x8>; 53 interrupts = <66 0x8>;
50 clocks = <&clks MPC512x_CLK_MB 54 clocks = <&clks MPC512x_CLK_MBX_BUS>,
51 <&clks MPC512x_CLK_MB 55 <&clks MPC512x_CLK_MBX_3D>,
52 <&clks MPC512x_CLK_MB 56 <&clks MPC512x_CLK_MBX>;
53 clock-names = "mbx-bus", "mbx- 57 clock-names = "mbx-bus", "mbx-3d", "mbx";
54 }; 58 };
55 59
56 sram@30000000 { 60 sram@30000000 {
57 compatible = "fsl,mpc5121-sram 61 compatible = "fsl,mpc5121-sram";
58 reg = <0x30000000 0x20000>; 62 reg = <0x30000000 0x20000>; /* 128K at 0x30000000 */
59 }; 63 };
60 64
61 nfc@40000000 { 65 nfc@40000000 {
62 compatible = "fsl,mpc5121-nfc" 66 compatible = "fsl,mpc5121-nfc";
63 reg = <0x40000000 0x100000>; 67 reg = <0x40000000 0x100000>; /* 1M at 0x40000000 */
64 interrupts = <6 8>; 68 interrupts = <6 8>;
65 #address-cells = <1>; 69 #address-cells = <1>;
66 #size-cells = <1>; 70 #size-cells = <1>;
67 clocks = <&clks MPC512x_CLK_NF 71 clocks = <&clks MPC512x_CLK_NFC>;
68 clock-names = "ipg"; 72 clock-names = "ipg";
69 }; 73 };
70 74
71 localbus@80000020 { 75 localbus@80000020 {
72 compatible = "fsl,mpc5121-loca 76 compatible = "fsl,mpc5121-localbus";
73 #address-cells = <2>; 77 #address-cells = <2>;
74 #size-cells = <1>; 78 #size-cells = <1>;
75 reg = <0x80000020 0x40>; 79 reg = <0x80000020 0x40>;
76 ranges = <0x0 0x0 0xfc000000 0 80 ranges = <0x0 0x0 0xfc000000 0x04000000>;
77 }; 81 };
78 82
79 clocks { 83 clocks {
80 #address-cells = <1>; 84 #address-cells = <1>;
81 #size-cells = <0>; 85 #size-cells = <0>;
82 86
83 osc: osc { 87 osc: osc {
84 compatible = "fixed-cl 88 compatible = "fixed-clock";
85 #clock-cells = <0>; 89 #clock-cells = <0>;
86 clock-frequency = <330 90 clock-frequency = <33000000>;
87 }; 91 };
88 }; 92 };
89 93
90 soc@80000000 { 94 soc@80000000 {
91 compatible = "fsl,mpc5121-immr 95 compatible = "fsl,mpc5121-immr";
92 #address-cells = <1>; 96 #address-cells = <1>;
93 #size-cells = <1>; 97 #size-cells = <1>;
94 ranges = <0x0 0x80000000 0x400 98 ranges = <0x0 0x80000000 0x400000>;
95 reg = <0x80000000 0x400000>; 99 reg = <0x80000000 0x400000>;
96 bus-frequency = <66000000>; 100 bus-frequency = <66000000>; /* 66 MHz ips bus */
97 101
98 102
99 /* 103 /*
100 * IPIC 104 * IPIC
101 * interrupts cell = <intr #, 105 * interrupts cell = <intr #, sense>
102 * sense values match linux IO 106 * sense values match linux IORESOURCE_IRQ_* defines:
103 * sense == 8: Level, low asse 107 * sense == 8: Level, low assertion
104 * sense == 2: Edge, high-to-l 108 * sense == 2: Edge, high-to-low change
105 */ 109 */
106 ipic: interrupt-controller@c00 110 ipic: interrupt-controller@c00 {
107 compatible = "fsl,mpc5 111 compatible = "fsl,mpc5121-ipic", "fsl,ipic";
108 interrupt-controller; 112 interrupt-controller;
109 #address-cells = <0>; 113 #address-cells = <0>;
110 #interrupt-cells = <2> 114 #interrupt-cells = <2>;
111 reg = <0xc00 0x100>; 115 reg = <0xc00 0x100>;
112 }; 116 };
113 117
114 /* Watchdog timer */ 118 /* Watchdog timer */
115 wdt@900 { 119 wdt@900 {
116 compatible = "fsl,mpc5 120 compatible = "fsl,mpc5121-wdt";
117 reg = <0x900 0x100>; 121 reg = <0x900 0x100>;
118 }; 122 };
119 123
120 /* Real time clock */ 124 /* Real time clock */
121 rtc@a00 { 125 rtc@a00 {
122 compatible = "fsl,mpc5 126 compatible = "fsl,mpc5121-rtc";
123 reg = <0xa00 0x100>; 127 reg = <0xa00 0x100>;
124 interrupts = <79 0x8 8 128 interrupts = <79 0x8 80 0x8>;
125 }; 129 };
126 130
127 /* Reset module */ 131 /* Reset module */
128 reset@e00 { 132 reset@e00 {
129 compatible = "fsl,mpc5 133 compatible = "fsl,mpc5121-reset";
130 reg = <0xe00 0x100>; 134 reg = <0xe00 0x100>;
131 }; 135 };
132 136
133 /* Clock control */ 137 /* Clock control */
134 clks: clock@f00 { 138 clks: clock@f00 {
135 compatible = "fsl,mpc5 139 compatible = "fsl,mpc5121-clock";
136 reg = <0xf00 0x100>; 140 reg = <0xf00 0x100>;
137 #clock-cells = <1>; 141 #clock-cells = <1>;
138 clocks = <&osc>; 142 clocks = <&osc>;
139 clock-names = "osc"; 143 clock-names = "osc";
140 }; 144 };
141 145
142 /* Power Management Controller 146 /* Power Management Controller */
143 pmc@1000 { !! 147 pmc@1000{
144 compatible = "fsl,mpc5 148 compatible = "fsl,mpc5121-pmc";
145 reg = <0x1000 0x100>; 149 reg = <0x1000 0x100>;
146 interrupts = <83 0x8>; 150 interrupts = <83 0x8>;
147 }; 151 };
148 152
149 gpio@1100 { 153 gpio@1100 {
150 compatible = "fsl,mpc5 154 compatible = "fsl,mpc5121-gpio";
151 reg = <0x1100 0x100>; 155 reg = <0x1100 0x100>;
152 interrupts = <78 0x8>; 156 interrupts = <78 0x8>;
153 }; 157 };
154 158
155 can@1300 { 159 can@1300 {
156 compatible = "fsl,mpc5 160 compatible = "fsl,mpc5121-mscan";
157 reg = <0x1300 0x80>; 161 reg = <0x1300 0x80>;
158 interrupts = <12 0x8>; 162 interrupts = <12 0x8>;
159 clocks = <&clks MPC512 163 clocks = <&clks MPC512x_CLK_BDLC>,
160 <&clks MPC512 164 <&clks MPC512x_CLK_IPS>,
161 <&clks MPC512 165 <&clks MPC512x_CLK_SYS>,
162 <&clks MPC512 166 <&clks MPC512x_CLK_REF>,
163 <&clks MPC512 167 <&clks MPC512x_CLK_MSCAN0_MCLK>;
164 clock-names = "ipg", " 168 clock-names = "ipg", "ips", "sys", "ref", "mclk";
165 }; 169 };
166 170
167 can@1380 { 171 can@1380 {
168 compatible = "fsl,mpc5 172 compatible = "fsl,mpc5121-mscan";
169 reg = <0x1380 0x80>; 173 reg = <0x1380 0x80>;
170 interrupts = <13 0x8>; 174 interrupts = <13 0x8>;
171 clocks = <&clks MPC512 175 clocks = <&clks MPC512x_CLK_BDLC>,
172 <&clks MPC512 176 <&clks MPC512x_CLK_IPS>,
173 <&clks MPC512 177 <&clks MPC512x_CLK_SYS>,
174 <&clks MPC512 178 <&clks MPC512x_CLK_REF>,
175 <&clks MPC512 179 <&clks MPC512x_CLK_MSCAN1_MCLK>;
176 clock-names = "ipg", " 180 clock-names = "ipg", "ips", "sys", "ref", "mclk";
177 }; 181 };
178 182
179 sdhc@1500 { 183 sdhc@1500 {
180 compatible = "fsl,mpc5 184 compatible = "fsl,mpc5121-sdhc";
181 reg = <0x1500 0x100>; 185 reg = <0x1500 0x100>;
182 interrupts = <8 0x8>; 186 interrupts = <8 0x8>;
183 dmas = <&dma0 30>; 187 dmas = <&dma0 30>;
184 dma-names = "rx-tx"; 188 dma-names = "rx-tx";
185 clocks = <&clks MPC512 189 clocks = <&clks MPC512x_CLK_IPS>,
186 <&clks MPC512 190 <&clks MPC512x_CLK_SDHC>;
187 clock-names = "ipg", " 191 clock-names = "ipg", "per";
188 }; 192 };
189 193
190 i2c@1700 { 194 i2c@1700 {
191 #address-cells = <1>; 195 #address-cells = <1>;
192 #size-cells = <0>; 196 #size-cells = <0>;
193 compatible = "fsl,mpc5 197 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
194 reg = <0x1700 0x20>; 198 reg = <0x1700 0x20>;
195 interrupts = <9 0x8>; 199 interrupts = <9 0x8>;
196 clocks = <&clks MPC512 200 clocks = <&clks MPC512x_CLK_I2C>;
197 clock-names = "ipg"; 201 clock-names = "ipg";
198 }; 202 };
199 203
200 i2c@1720 { 204 i2c@1720 {
201 #address-cells = <1>; 205 #address-cells = <1>;
202 #size-cells = <0>; 206 #size-cells = <0>;
203 compatible = "fsl,mpc5 207 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
204 reg = <0x1720 0x20>; 208 reg = <0x1720 0x20>;
205 interrupts = <10 0x8>; 209 interrupts = <10 0x8>;
206 clocks = <&clks MPC512 210 clocks = <&clks MPC512x_CLK_I2C>;
207 clock-names = "ipg"; 211 clock-names = "ipg";
208 }; 212 };
209 213
210 i2c@1740 { 214 i2c@1740 {
211 #address-cells = <1>; 215 #address-cells = <1>;
212 #size-cells = <0>; 216 #size-cells = <0>;
213 compatible = "fsl,mpc5 217 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
214 reg = <0x1740 0x20>; 218 reg = <0x1740 0x20>;
215 interrupts = <11 0x8>; 219 interrupts = <11 0x8>;
216 clocks = <&clks MPC512 220 clocks = <&clks MPC512x_CLK_I2C>;
217 clock-names = "ipg"; 221 clock-names = "ipg";
218 }; 222 };
219 223
220 i2ccontrol@1760 { 224 i2ccontrol@1760 {
221 compatible = "fsl,mpc5 225 compatible = "fsl,mpc5121-i2c-ctrl";
222 reg = <0x1760 0x8>; 226 reg = <0x1760 0x8>;
223 }; 227 };
224 228
225 axe@2000 { 229 axe@2000 {
226 compatible = "fsl,mpc5 230 compatible = "fsl,mpc5121-axe";
227 reg = <0x2000 0x100>; 231 reg = <0x2000 0x100>;
228 interrupts = <42 0x8>; 232 interrupts = <42 0x8>;
229 clocks = <&clks MPC512 233 clocks = <&clks MPC512x_CLK_AXE>;
230 clock-names = "ipg"; 234 clock-names = "ipg";
231 }; 235 };
232 236
233 display@2100 { 237 display@2100 {
234 compatible = "fsl,mpc5 238 compatible = "fsl,mpc5121-diu";
235 reg = <0x2100 0x100>; 239 reg = <0x2100 0x100>;
236 interrupts = <64 0x8>; 240 interrupts = <64 0x8>;
237 clocks = <&clks MPC512 241 clocks = <&clks MPC512x_CLK_DIU>;
238 clock-names = "ipg"; 242 clock-names = "ipg";
239 }; 243 };
240 244
241 can@2300 { 245 can@2300 {
242 compatible = "fsl,mpc5 246 compatible = "fsl,mpc5121-mscan";
243 reg = <0x2300 0x80>; 247 reg = <0x2300 0x80>;
244 interrupts = <90 0x8>; 248 interrupts = <90 0x8>;
245 clocks = <&clks MPC512 249 clocks = <&clks MPC512x_CLK_BDLC>,
246 <&clks MPC512 250 <&clks MPC512x_CLK_IPS>,
247 <&clks MPC512 251 <&clks MPC512x_CLK_SYS>,
248 <&clks MPC512 252 <&clks MPC512x_CLK_REF>,
249 <&clks MPC512 253 <&clks MPC512x_CLK_MSCAN2_MCLK>;
250 clock-names = "ipg", " 254 clock-names = "ipg", "ips", "sys", "ref", "mclk";
251 }; 255 };
252 256
253 can@2380 { 257 can@2380 {
254 compatible = "fsl,mpc5 258 compatible = "fsl,mpc5121-mscan";
255 reg = <0x2380 0x80>; 259 reg = <0x2380 0x80>;
256 interrupts = <91 0x8>; 260 interrupts = <91 0x8>;
257 clocks = <&clks MPC512 261 clocks = <&clks MPC512x_CLK_BDLC>,
258 <&clks MPC512 262 <&clks MPC512x_CLK_IPS>,
259 <&clks MPC512 263 <&clks MPC512x_CLK_SYS>,
260 <&clks MPC512 264 <&clks MPC512x_CLK_REF>,
261 <&clks MPC512 265 <&clks MPC512x_CLK_MSCAN3_MCLK>;
262 clock-names = "ipg", " 266 clock-names = "ipg", "ips", "sys", "ref", "mclk";
263 }; 267 };
264 268
265 viu@2400 { 269 viu@2400 {
266 compatible = "fsl,mpc5 270 compatible = "fsl,mpc5121-viu";
267 reg = <0x2400 0x400>; 271 reg = <0x2400 0x400>;
268 interrupts = <67 0x8>; 272 interrupts = <67 0x8>;
269 clocks = <&clks MPC512 273 clocks = <&clks MPC512x_CLK_VIU>;
270 clock-names = "ipg"; 274 clock-names = "ipg";
271 }; 275 };
272 276
273 mdio@2800 { 277 mdio@2800 {
274 compatible = "fsl,mpc5 278 compatible = "fsl,mpc5121-fec-mdio";
275 reg = <0x2800 0x800>; 279 reg = <0x2800 0x800>;
276 #address-cells = <1>; 280 #address-cells = <1>;
277 #size-cells = <0>; 281 #size-cells = <0>;
278 clocks = <&clks MPC512 282 clocks = <&clks MPC512x_CLK_FEC>;
279 clock-names = "per"; 283 clock-names = "per";
280 }; 284 };
281 285
282 eth0: ethernet@2800 { 286 eth0: ethernet@2800 {
283 device_type = "network 287 device_type = "network";
284 compatible = "fsl,mpc5 288 compatible = "fsl,mpc5121-fec";
285 reg = <0x2800 0x800>; 289 reg = <0x2800 0x800>;
286 local-mac-address = [ 290 local-mac-address = [ 00 00 00 00 00 00 ];
287 interrupts = <4 0x8>; 291 interrupts = <4 0x8>;
288 clocks = <&clks MPC512 292 clocks = <&clks MPC512x_CLK_FEC>;
289 clock-names = "per"; 293 clock-names = "per";
290 }; 294 };
291 295
292 /* USB1 using external ULPI PH 296 /* USB1 using external ULPI PHY */
293 usb@3000 { 297 usb@3000 {
294 compatible = "fsl,mpc5 298 compatible = "fsl,mpc5121-usb2-dr";
295 reg = <0x3000 0x600>; 299 reg = <0x3000 0x600>;
296 #address-cells = <1>; 300 #address-cells = <1>;
297 #size-cells = <0>; 301 #size-cells = <0>;
298 interrupts = <43 0x8>; 302 interrupts = <43 0x8>;
299 dr_mode = "otg"; 303 dr_mode = "otg";
300 phy_type = "ulpi"; 304 phy_type = "ulpi";
301 clocks = <&clks MPC512 305 clocks = <&clks MPC512x_CLK_USB1>;
302 clock-names = "ipg"; 306 clock-names = "ipg";
303 }; 307 };
304 308
305 /* USB0 using internal UTMI PH 309 /* USB0 using internal UTMI PHY */
306 usb@4000 { 310 usb@4000 {
307 compatible = "fsl,mpc5 311 compatible = "fsl,mpc5121-usb2-dr";
308 reg = <0x4000 0x600>; 312 reg = <0x4000 0x600>;
309 #address-cells = <1>; 313 #address-cells = <1>;
310 #size-cells = <0>; 314 #size-cells = <0>;
311 interrupts = <44 0x8>; 315 interrupts = <44 0x8>;
312 dr_mode = "otg"; 316 dr_mode = "otg";
313 phy_type = "utmi_wide" 317 phy_type = "utmi_wide";
314 clocks = <&clks MPC512 318 clocks = <&clks MPC512x_CLK_USB2>;
315 clock-names = "ipg"; 319 clock-names = "ipg";
316 }; 320 };
317 321
318 /* IO control */ 322 /* IO control */
319 ioctl@a000 { 323 ioctl@a000 {
320 compatible = "fsl,mpc5 324 compatible = "fsl,mpc5121-ioctl";
321 reg = <0xA000 0x1000>; 325 reg = <0xA000 0x1000>;
322 }; 326 };
323 327
324 /* LocalPlus controller */ 328 /* LocalPlus controller */
325 lpc@10000 { 329 lpc@10000 {
326 compatible = "fsl,mpc5 330 compatible = "fsl,mpc5121-lpc";
327 reg = <0x10000 0x100>; 331 reg = <0x10000 0x100>;
328 }; 332 };
329 333
330 sclpc@10100 { 334 sclpc@10100 {
331 compatible = "fsl,mpc5 335 compatible = "fsl,mpc512x-lpbfifo";
332 reg = <0x10100 0x50>; 336 reg = <0x10100 0x50>;
333 interrupts = <7 0x8>; 337 interrupts = <7 0x8>;
334 dmas = <&dma0 26>; 338 dmas = <&dma0 26>;
335 dma-names = "rx-tx"; 339 dma-names = "rx-tx";
336 }; 340 };
337 341
338 pata@10200 { 342 pata@10200 {
339 compatible = "fsl,mpc5 343 compatible = "fsl,mpc5121-pata";
340 reg = <0x10200 0x100>; 344 reg = <0x10200 0x100>;
341 interrupts = <5 0x8>; 345 interrupts = <5 0x8>;
342 clocks = <&clks MPC512 346 clocks = <&clks MPC512x_CLK_PATA>;
343 clock-names = "ipg"; 347 clock-names = "ipg";
344 }; 348 };
345 349
346 /* 512x PSCs are not 52xx PSC 350 /* 512x PSCs are not 52xx PSC compatible */
347 351
348 /* PSC0 */ 352 /* PSC0 */
349 psc@11000 { 353 psc@11000 {
350 compatible = "fsl,mpc5 354 compatible = "fsl,mpc5121-psc";
351 reg = <0x11000 0x100>; 355 reg = <0x11000 0x100>;
352 interrupts = <40 0x8>; 356 interrupts = <40 0x8>;
353 fsl,rx-fifo-size = <16 357 fsl,rx-fifo-size = <16>;
354 fsl,tx-fifo-size = <16 358 fsl,tx-fifo-size = <16>;
355 clocks = <&clks MPC512 359 clocks = <&clks MPC512x_CLK_PSC0>,
356 <&clks MPC512 360 <&clks MPC512x_CLK_PSC0_MCLK>;
357 clock-names = "ipg", " 361 clock-names = "ipg", "mclk";
358 }; 362 };
359 363
360 /* PSC1 */ 364 /* PSC1 */
361 psc@11100 { 365 psc@11100 {
362 compatible = "fsl,mpc5 366 compatible = "fsl,mpc5121-psc";
363 reg = <0x11100 0x100>; 367 reg = <0x11100 0x100>;
364 interrupts = <40 0x8>; 368 interrupts = <40 0x8>;
365 fsl,rx-fifo-size = <16 369 fsl,rx-fifo-size = <16>;
366 fsl,tx-fifo-size = <16 370 fsl,tx-fifo-size = <16>;
367 clocks = <&clks MPC512 371 clocks = <&clks MPC512x_CLK_PSC1>,
368 <&clks MPC512 372 <&clks MPC512x_CLK_PSC1_MCLK>;
369 clock-names = "ipg", " 373 clock-names = "ipg", "mclk";
370 }; 374 };
371 375
372 /* PSC2 */ 376 /* PSC2 */
373 psc@11200 { 377 psc@11200 {
374 compatible = "fsl,mpc5 378 compatible = "fsl,mpc5121-psc";
375 reg = <0x11200 0x100>; 379 reg = <0x11200 0x100>;
376 interrupts = <40 0x8>; 380 interrupts = <40 0x8>;
377 fsl,rx-fifo-size = <16 381 fsl,rx-fifo-size = <16>;
378 fsl,tx-fifo-size = <16 382 fsl,tx-fifo-size = <16>;
379 clocks = <&clks MPC512 383 clocks = <&clks MPC512x_CLK_PSC2>,
380 <&clks MPC512 384 <&clks MPC512x_CLK_PSC2_MCLK>;
381 clock-names = "ipg", " 385 clock-names = "ipg", "mclk";
382 }; 386 };
383 387
384 /* PSC3 */ 388 /* PSC3 */
385 psc@11300 { 389 psc@11300 {
386 compatible = "fsl,mpc5 390 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
387 reg = <0x11300 0x100>; 391 reg = <0x11300 0x100>;
388 interrupts = <40 0x8>; 392 interrupts = <40 0x8>;
389 fsl,rx-fifo-size = <16 393 fsl,rx-fifo-size = <16>;
390 fsl,tx-fifo-size = <16 394 fsl,tx-fifo-size = <16>;
391 clocks = <&clks MPC512 395 clocks = <&clks MPC512x_CLK_PSC3>,
392 <&clks MPC512 396 <&clks MPC512x_CLK_PSC3_MCLK>;
393 clock-names = "ipg", " 397 clock-names = "ipg", "mclk";
394 }; 398 };
395 399
396 /* PSC4 */ 400 /* PSC4 */
397 psc@11400 { 401 psc@11400 {
398 compatible = "fsl,mpc5 402 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
399 reg = <0x11400 0x100>; 403 reg = <0x11400 0x100>;
400 interrupts = <40 0x8>; 404 interrupts = <40 0x8>;
401 fsl,rx-fifo-size = <16 405 fsl,rx-fifo-size = <16>;
402 fsl,tx-fifo-size = <16 406 fsl,tx-fifo-size = <16>;
403 clocks = <&clks MPC512 407 clocks = <&clks MPC512x_CLK_PSC4>,
404 <&clks MPC512 408 <&clks MPC512x_CLK_PSC4_MCLK>;
405 clock-names = "ipg", " 409 clock-names = "ipg", "mclk";
406 }; 410 };
407 411
408 /* PSC5 */ 412 /* PSC5 */
409 psc@11500 { 413 psc@11500 {
410 compatible = "fsl,mpc5 414 compatible = "fsl,mpc5121-psc";
411 reg = <0x11500 0x100>; 415 reg = <0x11500 0x100>;
412 interrupts = <40 0x8>; 416 interrupts = <40 0x8>;
413 fsl,rx-fifo-size = <16 417 fsl,rx-fifo-size = <16>;
414 fsl,tx-fifo-size = <16 418 fsl,tx-fifo-size = <16>;
415 clocks = <&clks MPC512 419 clocks = <&clks MPC512x_CLK_PSC5>,
416 <&clks MPC512 420 <&clks MPC512x_CLK_PSC5_MCLK>;
417 clock-names = "ipg", " 421 clock-names = "ipg", "mclk";
418 }; 422 };
419 423
420 /* PSC6 */ 424 /* PSC6 */
421 psc@11600 { 425 psc@11600 {
422 compatible = "fsl,mpc5 426 compatible = "fsl,mpc5121-psc";
423 reg = <0x11600 0x100>; 427 reg = <0x11600 0x100>;
424 interrupts = <40 0x8>; 428 interrupts = <40 0x8>;
425 fsl,rx-fifo-size = <16 429 fsl,rx-fifo-size = <16>;
426 fsl,tx-fifo-size = <16 430 fsl,tx-fifo-size = <16>;
427 clocks = <&clks MPC512 431 clocks = <&clks MPC512x_CLK_PSC6>,
428 <&clks MPC512 432 <&clks MPC512x_CLK_PSC6_MCLK>;
429 clock-names = "ipg", " 433 clock-names = "ipg", "mclk";
430 }; 434 };
431 435
432 /* PSC7 */ 436 /* PSC7 */
433 psc@11700 { 437 psc@11700 {
434 compatible = "fsl,mpc5 438 compatible = "fsl,mpc5121-psc";
435 reg = <0x11700 0x100>; 439 reg = <0x11700 0x100>;
436 interrupts = <40 0x8>; 440 interrupts = <40 0x8>;
437 fsl,rx-fifo-size = <16 441 fsl,rx-fifo-size = <16>;
438 fsl,tx-fifo-size = <16 442 fsl,tx-fifo-size = <16>;
439 clocks = <&clks MPC512 443 clocks = <&clks MPC512x_CLK_PSC7>,
440 <&clks MPC512 444 <&clks MPC512x_CLK_PSC7_MCLK>;
441 clock-names = "ipg", " 445 clock-names = "ipg", "mclk";
442 }; 446 };
443 447
444 /* PSC8 */ 448 /* PSC8 */
445 psc@11800 { 449 psc@11800 {
446 compatible = "fsl,mpc5 450 compatible = "fsl,mpc5121-psc";
447 reg = <0x11800 0x100>; 451 reg = <0x11800 0x100>;
448 interrupts = <40 0x8>; 452 interrupts = <40 0x8>;
449 fsl,rx-fifo-size = <16 453 fsl,rx-fifo-size = <16>;
450 fsl,tx-fifo-size = <16 454 fsl,tx-fifo-size = <16>;
451 clocks = <&clks MPC512 455 clocks = <&clks MPC512x_CLK_PSC8>,
452 <&clks MPC512 456 <&clks MPC512x_CLK_PSC8_MCLK>;
453 clock-names = "ipg", " 457 clock-names = "ipg", "mclk";
454 }; 458 };
455 459
456 /* PSC9 */ 460 /* PSC9 */
457 psc@11900 { 461 psc@11900 {
458 compatible = "fsl,mpc5 462 compatible = "fsl,mpc5121-psc";
459 reg = <0x11900 0x100>; 463 reg = <0x11900 0x100>;
460 interrupts = <40 0x8>; 464 interrupts = <40 0x8>;
461 fsl,rx-fifo-size = <16 465 fsl,rx-fifo-size = <16>;
462 fsl,tx-fifo-size = <16 466 fsl,tx-fifo-size = <16>;
463 clocks = <&clks MPC512 467 clocks = <&clks MPC512x_CLK_PSC9>,
464 <&clks MPC512 468 <&clks MPC512x_CLK_PSC9_MCLK>;
465 clock-names = "ipg", " 469 clock-names = "ipg", "mclk";
466 }; 470 };
467 471
468 /* PSC10 */ 472 /* PSC10 */
469 psc@11a00 { 473 psc@11a00 {
470 compatible = "fsl,mpc5 474 compatible = "fsl,mpc5121-psc";
471 reg = <0x11a00 0x100>; 475 reg = <0x11a00 0x100>;
472 interrupts = <40 0x8>; 476 interrupts = <40 0x8>;
473 fsl,rx-fifo-size = <16 477 fsl,rx-fifo-size = <16>;
474 fsl,tx-fifo-size = <16 478 fsl,tx-fifo-size = <16>;
475 clocks = <&clks MPC512 479 clocks = <&clks MPC512x_CLK_PSC10>,
476 <&clks MPC512 480 <&clks MPC512x_CLK_PSC10_MCLK>;
477 clock-names = "ipg", " 481 clock-names = "ipg", "mclk";
478 }; 482 };
479 483
480 /* PSC11 */ 484 /* PSC11 */
481 psc@11b00 { 485 psc@11b00 {
482 compatible = "fsl,mpc5 486 compatible = "fsl,mpc5121-psc";
483 reg = <0x11b00 0x100>; 487 reg = <0x11b00 0x100>;
484 interrupts = <40 0x8>; 488 interrupts = <40 0x8>;
485 fsl,rx-fifo-size = <16 489 fsl,rx-fifo-size = <16>;
486 fsl,tx-fifo-size = <16 490 fsl,tx-fifo-size = <16>;
487 clocks = <&clks MPC512 491 clocks = <&clks MPC512x_CLK_PSC11>,
488 <&clks MPC512 492 <&clks MPC512x_CLK_PSC11_MCLK>;
489 clock-names = "ipg", " 493 clock-names = "ipg", "mclk";
490 }; 494 };
491 495
492 pscfifo@11f00 { 496 pscfifo@11f00 {
493 compatible = "fsl,mpc5 497 compatible = "fsl,mpc5121-psc-fifo";
494 reg = <0x11f00 0x100>; 498 reg = <0x11f00 0x100>;
495 interrupts = <40 0x8>; 499 interrupts = <40 0x8>;
496 clocks = <&clks MPC512 500 clocks = <&clks MPC512x_CLK_PSC_FIFO>;
497 clock-names = "ipg"; 501 clock-names = "ipg";
498 }; 502 };
499 503
500 dma0: dma@14000 { 504 dma0: dma@14000 {
501 compatible = "fsl,mpc5 505 compatible = "fsl,mpc5121-dma";
502 reg = <0x14000 0x1800> 506 reg = <0x14000 0x1800>;
503 interrupts = <65 0x8>; 507 interrupts = <65 0x8>;
504 #dma-cells = <1>; 508 #dma-cells = <1>;
505 }; 509 };
506 }; 510 };
507 511
508 pci: pci@80008500 { 512 pci: pci@80008500 {
509 compatible = "fsl,mpc5121-pci" 513 compatible = "fsl,mpc5121-pci";
510 device_type = "pci"; 514 device_type = "pci";
511 interrupts = <1 0x8>; 515 interrupts = <1 0x8>;
512 clock-frequency = <0>; 516 clock-frequency = <0>;
513 #address-cells = <3>; 517 #address-cells = <3>;
514 #size-cells = <2>; 518 #size-cells = <2>;
515 #interrupt-cells = <1>; 519 #interrupt-cells = <1>;
516 clocks = <&clks MPC512x_CLK_PC 520 clocks = <&clks MPC512x_CLK_PCI>;
517 clock-names = "ipg"; 521 clock-names = "ipg";
518 522
519 reg = <0x80008500 0x100 /* int 523 reg = <0x80008500 0x100 /* internal registers */
520 0x80008300 0x8>; /* con 524 0x80008300 0x8>; /* config space access registers */
521 bus-range = <0x0 0x0>; 525 bus-range = <0x0 0x0>;
522 ranges = <0x42000000 0x0 0xa00 526 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
523 0x02000000 0x0 0xb00 527 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
524 0x01000000 0x0 0x000 528 0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
525 }; 529 };
526 }; 530 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.