1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * base MPC5121 Device Tree Source
4 *
5 * Copyright 2007-2008 Freescale Semiconductor
6 */
7
8 #include <dt-bindings/clock/mpc512x-clock.h>
9
10 /dts-v1/;
11
12 / {
13 model = "mpc5121";
14 compatible = "fsl,mpc5121";
15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&ipic>;
18
19 aliases {
20 ethernet0 = ð0;
21 pci = &pci;
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 PowerPC,5121@0 {
29 device_type = "cpu";
30 reg = <0>;
31 d-cache-line-size = <0
32 i-cache-line-size = <0
33 d-cache-size = <0x8000
34 i-cache-size = <0x8000
35 timebase-frequency = <
36 bus-frequency = <19800
37 clock-frequency = <396
38 };
39 };
40
41 memory {
42 device_type = "memory";
43 reg = <0x00000000 0x10000000>;
44 };
45
46 mbx@20000000 {
47 compatible = "fsl,mpc5121-mbx"
48 reg = <0x20000000 0x4000>;
49 interrupts = <66 0x8>;
50 clocks = <&clks MPC512x_CLK_MB
51 <&clks MPC512x_CLK_MB
52 <&clks MPC512x_CLK_MB
53 clock-names = "mbx-bus", "mbx-
54 };
55
56 sram@30000000 {
57 compatible = "fsl,mpc5121-sram
58 reg = <0x30000000 0x20000>;
59 };
60
61 nfc@40000000 {
62 compatible = "fsl,mpc5121-nfc"
63 reg = <0x40000000 0x100000>;
64 interrupts = <6 8>;
65 #address-cells = <1>;
66 #size-cells = <1>;
67 clocks = <&clks MPC512x_CLK_NF
68 clock-names = "ipg";
69 };
70
71 localbus@80000020 {
72 compatible = "fsl,mpc5121-loca
73 #address-cells = <2>;
74 #size-cells = <1>;
75 reg = <0x80000020 0x40>;
76 ranges = <0x0 0x0 0xfc000000 0
77 };
78
79 clocks {
80 #address-cells = <1>;
81 #size-cells = <0>;
82
83 osc: osc {
84 compatible = "fixed-cl
85 #clock-cells = <0>;
86 clock-frequency = <330
87 };
88 };
89
90 soc@80000000 {
91 compatible = "fsl,mpc5121-immr
92 #address-cells = <1>;
93 #size-cells = <1>;
94 ranges = <0x0 0x80000000 0x400
95 reg = <0x80000000 0x400000>;
96 bus-frequency = <66000000>;
97
98
99 /*
100 * IPIC
101 * interrupts cell = <intr #,
102 * sense values match linux IO
103 * sense == 8: Level, low asse
104 * sense == 2: Edge, high-to-l
105 */
106 ipic: interrupt-controller@c00
107 compatible = "fsl,mpc5
108 interrupt-controller;
109 #address-cells = <0>;
110 #interrupt-cells = <2>
111 reg = <0xc00 0x100>;
112 };
113
114 /* Watchdog timer */
115 wdt@900 {
116 compatible = "fsl,mpc5
117 reg = <0x900 0x100>;
118 };
119
120 /* Real time clock */
121 rtc@a00 {
122 compatible = "fsl,mpc5
123 reg = <0xa00 0x100>;
124 interrupts = <79 0x8 8
125 };
126
127 /* Reset module */
128 reset@e00 {
129 compatible = "fsl,mpc5
130 reg = <0xe00 0x100>;
131 };
132
133 /* Clock control */
134 clks: clock@f00 {
135 compatible = "fsl,mpc5
136 reg = <0xf00 0x100>;
137 #clock-cells = <1>;
138 clocks = <&osc>;
139 clock-names = "osc";
140 };
141
142 /* Power Management Controller
143 pmc@1000 {
144 compatible = "fsl,mpc5
145 reg = <0x1000 0x100>;
146 interrupts = <83 0x8>;
147 };
148
149 gpio@1100 {
150 compatible = "fsl,mpc5
151 reg = <0x1100 0x100>;
152 interrupts = <78 0x8>;
153 };
154
155 can@1300 {
156 compatible = "fsl,mpc5
157 reg = <0x1300 0x80>;
158 interrupts = <12 0x8>;
159 clocks = <&clks MPC512
160 <&clks MPC512
161 <&clks MPC512
162 <&clks MPC512
163 <&clks MPC512
164 clock-names = "ipg", "
165 };
166
167 can@1380 {
168 compatible = "fsl,mpc5
169 reg = <0x1380 0x80>;
170 interrupts = <13 0x8>;
171 clocks = <&clks MPC512
172 <&clks MPC512
173 <&clks MPC512
174 <&clks MPC512
175 <&clks MPC512
176 clock-names = "ipg", "
177 };
178
179 sdhc@1500 {
180 compatible = "fsl,mpc5
181 reg = <0x1500 0x100>;
182 interrupts = <8 0x8>;
183 dmas = <&dma0 30>;
184 dma-names = "rx-tx";
185 clocks = <&clks MPC512
186 <&clks MPC512
187 clock-names = "ipg", "
188 };
189
190 i2c@1700 {
191 #address-cells = <1>;
192 #size-cells = <0>;
193 compatible = "fsl,mpc5
194 reg = <0x1700 0x20>;
195 interrupts = <9 0x8>;
196 clocks = <&clks MPC512
197 clock-names = "ipg";
198 };
199
200 i2c@1720 {
201 #address-cells = <1>;
202 #size-cells = <0>;
203 compatible = "fsl,mpc5
204 reg = <0x1720 0x20>;
205 interrupts = <10 0x8>;
206 clocks = <&clks MPC512
207 clock-names = "ipg";
208 };
209
210 i2c@1740 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213 compatible = "fsl,mpc5
214 reg = <0x1740 0x20>;
215 interrupts = <11 0x8>;
216 clocks = <&clks MPC512
217 clock-names = "ipg";
218 };
219
220 i2ccontrol@1760 {
221 compatible = "fsl,mpc5
222 reg = <0x1760 0x8>;
223 };
224
225 axe@2000 {
226 compatible = "fsl,mpc5
227 reg = <0x2000 0x100>;
228 interrupts = <42 0x8>;
229 clocks = <&clks MPC512
230 clock-names = "ipg";
231 };
232
233 display@2100 {
234 compatible = "fsl,mpc5
235 reg = <0x2100 0x100>;
236 interrupts = <64 0x8>;
237 clocks = <&clks MPC512
238 clock-names = "ipg";
239 };
240
241 can@2300 {
242 compatible = "fsl,mpc5
243 reg = <0x2300 0x80>;
244 interrupts = <90 0x8>;
245 clocks = <&clks MPC512
246 <&clks MPC512
247 <&clks MPC512
248 <&clks MPC512
249 <&clks MPC512
250 clock-names = "ipg", "
251 };
252
253 can@2380 {
254 compatible = "fsl,mpc5
255 reg = <0x2380 0x80>;
256 interrupts = <91 0x8>;
257 clocks = <&clks MPC512
258 <&clks MPC512
259 <&clks MPC512
260 <&clks MPC512
261 <&clks MPC512
262 clock-names = "ipg", "
263 };
264
265 viu@2400 {
266 compatible = "fsl,mpc5
267 reg = <0x2400 0x400>;
268 interrupts = <67 0x8>;
269 clocks = <&clks MPC512
270 clock-names = "ipg";
271 };
272
273 mdio@2800 {
274 compatible = "fsl,mpc5
275 reg = <0x2800 0x800>;
276 #address-cells = <1>;
277 #size-cells = <0>;
278 clocks = <&clks MPC512
279 clock-names = "per";
280 };
281
282 eth0: ethernet@2800 {
283 device_type = "network
284 compatible = "fsl,mpc5
285 reg = <0x2800 0x800>;
286 local-mac-address = [
287 interrupts = <4 0x8>;
288 clocks = <&clks MPC512
289 clock-names = "per";
290 };
291
292 /* USB1 using external ULPI PH
293 usb@3000 {
294 compatible = "fsl,mpc5
295 reg = <0x3000 0x600>;
296 #address-cells = <1>;
297 #size-cells = <0>;
298 interrupts = <43 0x8>;
299 dr_mode = "otg";
300 phy_type = "ulpi";
301 clocks = <&clks MPC512
302 clock-names = "ipg";
303 };
304
305 /* USB0 using internal UTMI PH
306 usb@4000 {
307 compatible = "fsl,mpc5
308 reg = <0x4000 0x600>;
309 #address-cells = <1>;
310 #size-cells = <0>;
311 interrupts = <44 0x8>;
312 dr_mode = "otg";
313 phy_type = "utmi_wide"
314 clocks = <&clks MPC512
315 clock-names = "ipg";
316 };
317
318 /* IO control */
319 ioctl@a000 {
320 compatible = "fsl,mpc5
321 reg = <0xA000 0x1000>;
322 };
323
324 /* LocalPlus controller */
325 lpc@10000 {
326 compatible = "fsl,mpc5
327 reg = <0x10000 0x100>;
328 };
329
330 sclpc@10100 {
331 compatible = "fsl,mpc5
332 reg = <0x10100 0x50>;
333 interrupts = <7 0x8>;
334 dmas = <&dma0 26>;
335 dma-names = "rx-tx";
336 };
337
338 pata@10200 {
339 compatible = "fsl,mpc5
340 reg = <0x10200 0x100>;
341 interrupts = <5 0x8>;
342 clocks = <&clks MPC512
343 clock-names = "ipg";
344 };
345
346 /* 512x PSCs are not 52xx PSC
347
348 /* PSC0 */
349 psc@11000 {
350 compatible = "fsl,mpc5
351 reg = <0x11000 0x100>;
352 interrupts = <40 0x8>;
353 fsl,rx-fifo-size = <16
354 fsl,tx-fifo-size = <16
355 clocks = <&clks MPC512
356 <&clks MPC512
357 clock-names = "ipg", "
358 };
359
360 /* PSC1 */
361 psc@11100 {
362 compatible = "fsl,mpc5
363 reg = <0x11100 0x100>;
364 interrupts = <40 0x8>;
365 fsl,rx-fifo-size = <16
366 fsl,tx-fifo-size = <16
367 clocks = <&clks MPC512
368 <&clks MPC512
369 clock-names = "ipg", "
370 };
371
372 /* PSC2 */
373 psc@11200 {
374 compatible = "fsl,mpc5
375 reg = <0x11200 0x100>;
376 interrupts = <40 0x8>;
377 fsl,rx-fifo-size = <16
378 fsl,tx-fifo-size = <16
379 clocks = <&clks MPC512
380 <&clks MPC512
381 clock-names = "ipg", "
382 };
383
384 /* PSC3 */
385 psc@11300 {
386 compatible = "fsl,mpc5
387 reg = <0x11300 0x100>;
388 interrupts = <40 0x8>;
389 fsl,rx-fifo-size = <16
390 fsl,tx-fifo-size = <16
391 clocks = <&clks MPC512
392 <&clks MPC512
393 clock-names = "ipg", "
394 };
395
396 /* PSC4 */
397 psc@11400 {
398 compatible = "fsl,mpc5
399 reg = <0x11400 0x100>;
400 interrupts = <40 0x8>;
401 fsl,rx-fifo-size = <16
402 fsl,tx-fifo-size = <16
403 clocks = <&clks MPC512
404 <&clks MPC512
405 clock-names = "ipg", "
406 };
407
408 /* PSC5 */
409 psc@11500 {
410 compatible = "fsl,mpc5
411 reg = <0x11500 0x100>;
412 interrupts = <40 0x8>;
413 fsl,rx-fifo-size = <16
414 fsl,tx-fifo-size = <16
415 clocks = <&clks MPC512
416 <&clks MPC512
417 clock-names = "ipg", "
418 };
419
420 /* PSC6 */
421 psc@11600 {
422 compatible = "fsl,mpc5
423 reg = <0x11600 0x100>;
424 interrupts = <40 0x8>;
425 fsl,rx-fifo-size = <16
426 fsl,tx-fifo-size = <16
427 clocks = <&clks MPC512
428 <&clks MPC512
429 clock-names = "ipg", "
430 };
431
432 /* PSC7 */
433 psc@11700 {
434 compatible = "fsl,mpc5
435 reg = <0x11700 0x100>;
436 interrupts = <40 0x8>;
437 fsl,rx-fifo-size = <16
438 fsl,tx-fifo-size = <16
439 clocks = <&clks MPC512
440 <&clks MPC512
441 clock-names = "ipg", "
442 };
443
444 /* PSC8 */
445 psc@11800 {
446 compatible = "fsl,mpc5
447 reg = <0x11800 0x100>;
448 interrupts = <40 0x8>;
449 fsl,rx-fifo-size = <16
450 fsl,tx-fifo-size = <16
451 clocks = <&clks MPC512
452 <&clks MPC512
453 clock-names = "ipg", "
454 };
455
456 /* PSC9 */
457 psc@11900 {
458 compatible = "fsl,mpc5
459 reg = <0x11900 0x100>;
460 interrupts = <40 0x8>;
461 fsl,rx-fifo-size = <16
462 fsl,tx-fifo-size = <16
463 clocks = <&clks MPC512
464 <&clks MPC512
465 clock-names = "ipg", "
466 };
467
468 /* PSC10 */
469 psc@11a00 {
470 compatible = "fsl,mpc5
471 reg = <0x11a00 0x100>;
472 interrupts = <40 0x8>;
473 fsl,rx-fifo-size = <16
474 fsl,tx-fifo-size = <16
475 clocks = <&clks MPC512
476 <&clks MPC512
477 clock-names = "ipg", "
478 };
479
480 /* PSC11 */
481 psc@11b00 {
482 compatible = "fsl,mpc5
483 reg = <0x11b00 0x100>;
484 interrupts = <40 0x8>;
485 fsl,rx-fifo-size = <16
486 fsl,tx-fifo-size = <16
487 clocks = <&clks MPC512
488 <&clks MPC512
489 clock-names = "ipg", "
490 };
491
492 pscfifo@11f00 {
493 compatible = "fsl,mpc5
494 reg = <0x11f00 0x100>;
495 interrupts = <40 0x8>;
496 clocks = <&clks MPC512
497 clock-names = "ipg";
498 };
499
500 dma0: dma@14000 {
501 compatible = "fsl,mpc5
502 reg = <0x14000 0x1800>
503 interrupts = <65 0x8>;
504 #dma-cells = <1>;
505 };
506 };
507
508 pci: pci@80008500 {
509 compatible = "fsl,mpc5121-pci"
510 device_type = "pci";
511 interrupts = <1 0x8>;
512 clock-frequency = <0>;
513 #address-cells = <3>;
514 #size-cells = <2>;
515 #interrupt-cells = <1>;
516 clocks = <&clks MPC512x_CLK_PC
517 clock-names = "ipg";
518
519 reg = <0x80008500 0x100 /* int
520 0x80008300 0x8>; /* con
521 bus-range = <0x0 0x0>;
522 ranges = <0x42000000 0x0 0xa00
523 0x02000000 0x0 0xb00
524 0x01000000 0x0 0x000
525 };
526 };
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