1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * MPC5121E ADS Device Tree Source 3 * MPC5121E ADS Device Tree Source
4 * 4 *
5 * Copyright 2007-2008 Freescale Semiconductor 5 * Copyright 2007-2008 Freescale Semiconductor Inc.
6 */ 6 */
7 7
8 #include "mpc5121.dtsi" 8 #include "mpc5121.dtsi"
9 9
10 / { 10 / {
11 model = "mpc5121ads"; 11 model = "mpc5121ads";
12 compatible = "fsl,mpc5121ads", "fsl,mp 12 compatible = "fsl,mpc5121ads", "fsl,mpc5121";
13 13
14 nfc@40000000 { 14 nfc@40000000 {
15 /* 15 /*
16 * ADS has two Hynix 512MB Nan 16 * ADS has two Hynix 512MB Nand flash chips in a single
17 * stacked package. 17 * stacked package.
18 */ 18 */
19 chips = <2>; 19 chips = <2>;
20 20
21 nand@0 { 21 nand@0 {
22 label = "nand"; 22 label = "nand";
23 reg = <0x00000000 0x40 23 reg = <0x00000000 0x40000000>; /* 512MB + 512MB */
24 }; 24 };
25 }; 25 };
26 26
27 localbus@80000020 { 27 localbus@80000020 {
28 ranges = <0x0 0x0 0xfc000000 0 28 ranges = <0x0 0x0 0xfc000000 0x04000000
29 0x2 0x0 0x82000000 0 29 0x2 0x0 0x82000000 0x00008000>;
30 30
31 flash@0,0 { 31 flash@0,0 {
32 compatible = "cfi-flas 32 compatible = "cfi-flash";
33 reg = <0 0x0 0x4000000 33 reg = <0 0x0 0x4000000>;
34 #address-cells = <1>; 34 #address-cells = <1>;
35 #size-cells = <1>; 35 #size-cells = <1>;
36 bank-width = <4>; 36 bank-width = <4>;
37 device-width = <2>; 37 device-width = <2>;
38 38
39 protected@0 { 39 protected@0 {
40 label = "prote 40 label = "protected";
41 reg = <0x00000 41 reg = <0x00000000 0x00040000>; // first sector is protected
42 read-only; 42 read-only;
43 }; 43 };
44 filesystem@40000 { 44 filesystem@40000 {
45 label = "files 45 label = "filesystem";
46 reg = <0x00040 46 reg = <0x00040000 0x03c00000>; // 60M for filesystem
47 }; 47 };
48 kernel@3c40000 { 48 kernel@3c40000 {
49 label = "kerne 49 label = "kernel";
50 reg = <0x03c40 50 reg = <0x03c40000 0x00280000>; // 2.5M for kernel
51 }; 51 };
52 device-tree@3ec0000 { 52 device-tree@3ec0000 {
53 label = "devic 53 label = "device-tree";
54 reg = <0x03ec0 54 reg = <0x03ec0000 0x00040000>; // one sector for device tree
55 }; 55 };
56 u-boot@3f00000 { 56 u-boot@3f00000 {
57 label = "u-boo 57 label = "u-boot";
58 reg = <0x03f00 58 reg = <0x03f00000 0x00100000>; // 1M for u-boot
59 read-only; 59 read-only;
60 }; 60 };
61 }; 61 };
62 62
63 board-control@2,0 { 63 board-control@2,0 {
64 compatible = "fsl,mpc5 64 compatible = "fsl,mpc5121ads-cpld";
65 reg = <0x2 0x0 0x8000> 65 reg = <0x2 0x0 0x8000>;
66 }; 66 };
67 67
68 cpld_pic: pic@2,a { 68 cpld_pic: pic@2,a {
69 compatible = "fsl,mpc5 69 compatible = "fsl,mpc5121ads-cpld-pic";
70 interrupt-controller; 70 interrupt-controller;
71 #interrupt-cells = <2> 71 #interrupt-cells = <2>;
72 reg = <0x2 0xa 0x5>; 72 reg = <0x2 0xa 0x5>;
73 /* irq routing: 73 /* irq routing:
74 * all irqs but touch 74 * all irqs but touch screen are routed to irq0 (ipic 48)
75 * touch screen is sta 75 * touch screen is statically routed to irq1 (ipic 17)
76 * so don't use it her 76 * so don't use it here
77 */ 77 */
78 interrupts = <48 0x8>; 78 interrupts = <48 0x8>;
79 }; 79 };
80 }; 80 };
81 81
82 soc@80000000 { 82 soc@80000000 {
83 83
84 i2c@1700 { 84 i2c@1700 {
85 fsl,preserve-clocking; 85 fsl,preserve-clocking;
86 86
87 hwmon@4a { 87 hwmon@4a {
88 compatible = " 88 compatible = "adi,ad7414";
89 reg = <0x4a>; 89 reg = <0x4a>;
90 }; 90 };
91 91
92 eeprom@50 { 92 eeprom@50 {
93 compatible = " 93 compatible = "atmel,24c32";
94 reg = <0x50>; 94 reg = <0x50>;
95 }; 95 };
96 96
97 rtc@68 { 97 rtc@68 {
98 compatible = " 98 compatible = "st,m41t62";
99 reg = <0x68>; 99 reg = <0x68>;
100 }; 100 };
101 }; 101 };
102 102
103 eth0: ethernet@2800 { 103 eth0: ethernet@2800 {
104 phy-handle = <&phy0>; 104 phy-handle = <&phy0>;
105 }; 105 };
106 106
107 can@2300 { 107 can@2300 {
108 status = "disabled"; 108 status = "disabled";
109 }; 109 };
110 110
111 can@2380 { 111 can@2380 {
112 status = "disabled"; 112 status = "disabled";
113 }; 113 };
114 114
115 viu@2400 { 115 viu@2400 {
116 status = "disabled"; 116 status = "disabled";
117 }; 117 };
118 118
119 mdio@2800 { 119 mdio@2800 {
120 phy0: ethernet-phy@0 { 120 phy0: ethernet-phy@0 {
121 reg = <1>; 121 reg = <1>;
122 }; 122 };
123 }; 123 };
124 124
125 /* mpc5121ads only uses USB0 * 125 /* mpc5121ads only uses USB0 */
126 usb@3000 { 126 usb@3000 {
127 status = "disabled"; 127 status = "disabled";
128 }; 128 };
129 129
130 /* USB0 using internal UTMI PH 130 /* USB0 using internal UTMI PHY */
131 usb@4000 { 131 usb@4000 {
132 dr_mode = "host"; 132 dr_mode = "host";
133 fsl,invert-drvvbus; 133 fsl,invert-drvvbus;
134 fsl,invert-pwr-fault; 134 fsl,invert-pwr-fault;
135 }; 135 };
136 136
137 /* PSC3 serial port A aka ttyP 137 /* PSC3 serial port A aka ttyPSC0 */
138 psc@11300 { 138 psc@11300 {
139 compatible = "fsl,mpc5 139 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
140 }; 140 };
141 141
142 /* PSC4 serial port B aka ttyP 142 /* PSC4 serial port B aka ttyPSC1 */
143 psc@11400 { 143 psc@11400 {
144 compatible = "fsl,mpc5 144 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
145 }; 145 };
146 146
147 /* PSC5 in ac97 mode */ 147 /* PSC5 in ac97 mode */
148 ac97: psc@11500 { 148 ac97: psc@11500 {
149 compatible = "fsl,mpc5 149 compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc";
150 fsl,mode = "ac97-slave 150 fsl,mode = "ac97-slave";
151 fsl,rx-fifo-size = <38 151 fsl,rx-fifo-size = <384>;
152 fsl,tx-fifo-size = <38 152 fsl,tx-fifo-size = <384>;
153 }; 153 };
154 }; 154 };
155 155
156 pci: pci@80008500 { 156 pci: pci@80008500 {
157 interrupt-map-mask = <0xf800 0 157 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
158 interrupt-map = < 158 interrupt-map = <
159 /* IDSEL 0x15 159 /* IDSEL 0x15 - Slot 1 PCI */
160 0xa800 0x0 0x 160 0xa800 0x0 0x0 0x1 &cpld_pic 0x0 0x8
161 0xa800 0x0 0x 161 0xa800 0x0 0x0 0x2 &cpld_pic 0x1 0x8
162 0xa800 0x0 0x 162 0xa800 0x0 0x0 0x3 &cpld_pic 0x2 0x8
163 0xa800 0x0 0x 163 0xa800 0x0 0x0 0x4 &cpld_pic 0x3 0x8
164 164
165 /* IDSEL 0x16 165 /* IDSEL 0x16 - Slot 2 MiniPCI */
166 0xb000 0x0 0x 166 0xb000 0x0 0x0 0x1 &cpld_pic 0x4 0x8
167 0xb000 0x0 0x 167 0xb000 0x0 0x0 0x2 &cpld_pic 0x5 0x8
168 168
169 /* IDSEL 0x17 169 /* IDSEL 0x17 - Slot 3 MiniPCI */
170 0xb800 0x0 0x 170 0xb800 0x0 0x0 0x1 &cpld_pic 0x6 0x8
171 0xb800 0x0 0x 171 0xb800 0x0 0x0 0x2 &cpld_pic 0x7 0x8
172 >; 172 >;
173 }; 173 };
174 }; 174 };
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