1 // SPDX-License-Identifier: GPL-2.0-or-later <<
2 /* 1 /*
3 * base MPC5200b Device Tree Source 2 * base MPC5200b Device Tree Source
4 * 3 *
5 * Copyright (C) 2010 SecretLab 4 * Copyright (C) 2010 SecretLab
6 * Grant Likely <grant@secretlab.ca> 5 * Grant Likely <grant@secretlab.ca>
7 * John Bonesio <bones@secretlab.ca> 6 * John Bonesio <bones@secretlab.ca>
>> 7 *
>> 8 * This program is free software; you can redistribute it and/or modify it
>> 9 * under the terms of the GNU General Public License as published by the
>> 10 * Free Software Foundation; either version 2 of the License, or (at your
>> 11 * option) any later version.
8 */ 12 */
9 13
10 /dts-v1/; 14 /dts-v1/;
11 15
12 / { 16 / {
13 model = "fsl,mpc5200b"; 17 model = "fsl,mpc5200b";
14 compatible = "fsl,mpc5200b"; 18 compatible = "fsl,mpc5200b";
15 #address-cells = <1>; 19 #address-cells = <1>;
16 #size-cells = <1>; 20 #size-cells = <1>;
17 interrupt-parent = <&mpc5200_pic>; 21 interrupt-parent = <&mpc5200_pic>;
18 22
19 cpus { 23 cpus {
20 #address-cells = <1>; 24 #address-cells = <1>;
21 #size-cells = <0>; 25 #size-cells = <0>;
22 26
23 powerpc: PowerPC,5200@0 { 27 powerpc: PowerPC,5200@0 {
24 device_type = "cpu"; 28 device_type = "cpu";
25 reg = <0>; 29 reg = <0>;
26 d-cache-line-size = <3 30 d-cache-line-size = <32>;
27 i-cache-line-size = <3 31 i-cache-line-size = <32>;
28 d-cache-size = <0x4000 32 d-cache-size = <0x4000>; // L1, 16K
29 i-cache-size = <0x4000 33 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = < 34 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; 35 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; 36 clock-frequency = <0>; // from bootloader
33 }; 37 };
34 }; 38 };
35 39
36 memory: memory@0 { !! 40 memory: memory {
37 device_type = "memory"; 41 device_type = "memory";
38 reg = <0x00000000 0x04000000>; 42 reg = <0x00000000 0x04000000>; // 64MB
39 }; 43 };
40 44
41 soc: soc5200@f0000000 { 45 soc: soc5200@f0000000 {
42 #address-cells = <1>; 46 #address-cells = <1>;
43 #size-cells = <1>; 47 #size-cells = <1>;
44 compatible = "fsl,mpc5200b-imm 48 compatible = "fsl,mpc5200b-immr";
45 ranges = <0 0xf0000000 0x0000c 49 ranges = <0 0xf0000000 0x0000c000>;
46 reg = <0xf0000000 0x00000100>; 50 reg = <0xf0000000 0x00000100>;
47 bus-frequency = <0>; 51 bus-frequency = <0>; // from bootloader
48 system-frequency = <0>; 52 system-frequency = <0>; // from bootloader
49 53
50 cdm@200 { 54 cdm@200 {
51 compatible = "fsl,mpc5 55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
52 reg = <0x200 0x38>; 56 reg = <0x200 0x38>;
53 }; 57 };
54 58
55 mpc5200_pic: interrupt-control 59 mpc5200_pic: interrupt-controller@500 {
56 // 5200 interrupts are 60 // 5200 interrupts are encoded into two levels;
57 interrupt-controller; 61 interrupt-controller;
58 #interrupt-cells = <3> 62 #interrupt-cells = <3>;
59 compatible = "fsl,mpc5 63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
60 reg = <0x500 0x80>; 64 reg = <0x500 0x80>;
61 }; 65 };
62 66
63 gpt0: timer@600 { // Gen 67 gpt0: timer@600 { // General Purpose Timer
64 compatible = "fsl,mpc5 68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
65 #gpio-cells = <2>; // 69 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
66 reg = <0x600 0x10>; 70 reg = <0x600 0x10>;
67 interrupts = <1 9 0>; 71 interrupts = <1 9 0>;
68 // add 'fsl,has-wdt' t 72 // add 'fsl,has-wdt' to enable watchdog
69 }; 73 };
70 74
71 gpt1: timer@610 { // Gen 75 gpt1: timer@610 { // General Purpose Timer
72 compatible = "fsl,mpc5 76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
73 #gpio-cells = <2>; // 77 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
74 reg = <0x610 0x10>; 78 reg = <0x610 0x10>;
75 interrupts = <1 10 0>; 79 interrupts = <1 10 0>;
76 }; 80 };
77 81
78 gpt2: timer@620 { // Gen 82 gpt2: timer@620 { // General Purpose Timer
79 compatible = "fsl,mpc5 83 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
80 #gpio-cells = <2>; // 84 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
81 reg = <0x620 0x10>; 85 reg = <0x620 0x10>;
82 interrupts = <1 11 0>; 86 interrupts = <1 11 0>;
83 }; 87 };
84 88
85 gpt3: timer@630 { // Gen 89 gpt3: timer@630 { // General Purpose Timer
86 compatible = "fsl,mpc5 90 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
87 #gpio-cells = <2>; // 91 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
88 reg = <0x630 0x10>; 92 reg = <0x630 0x10>;
89 interrupts = <1 12 0>; 93 interrupts = <1 12 0>;
90 }; 94 };
91 95
92 gpt4: timer@640 { // Gen 96 gpt4: timer@640 { // General Purpose Timer
93 compatible = "fsl,mpc5 97 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
94 #gpio-cells = <2>; // 98 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
95 reg = <0x640 0x10>; 99 reg = <0x640 0x10>;
96 interrupts = <1 13 0>; 100 interrupts = <1 13 0>;
97 }; 101 };
98 102
99 gpt5: timer@650 { // Gen 103 gpt5: timer@650 { // General Purpose Timer
100 compatible = "fsl,mpc5 104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
101 #gpio-cells = <2>; // 105 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
102 reg = <0x650 0x10>; 106 reg = <0x650 0x10>;
103 interrupts = <1 14 0>; 107 interrupts = <1 14 0>;
104 }; 108 };
105 109
106 gpt6: timer@660 { // Gen 110 gpt6: timer@660 { // General Purpose Timer
107 compatible = "fsl,mpc5 111 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
108 #gpio-cells = <2>; // 112 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
109 reg = <0x660 0x10>; 113 reg = <0x660 0x10>;
110 interrupts = <1 15 0>; 114 interrupts = <1 15 0>;
111 }; 115 };
112 116
113 gpt7: timer@670 { // Gen 117 gpt7: timer@670 { // General Purpose Timer
114 compatible = "fsl,mpc5 118 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
115 #gpio-cells = <2>; // 119 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
116 reg = <0x670 0x10>; 120 reg = <0x670 0x10>;
117 interrupts = <1 16 0>; 121 interrupts = <1 16 0>;
118 }; 122 };
119 123
120 rtc@800 { // Real time c 124 rtc@800 { // Real time clock
121 compatible = "fsl,mpc5 125 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
122 reg = <0x800 0x100>; 126 reg = <0x800 0x100>;
123 interrupts = <1 5 0 1 127 interrupts = <1 5 0 1 6 0>;
124 }; 128 };
125 129
126 can@900 { 130 can@900 {
127 compatible = "fsl,mpc5 131 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
128 interrupts = <2 17 0>; 132 interrupts = <2 17 0>;
129 reg = <0x900 0x80>; 133 reg = <0x900 0x80>;
130 }; 134 };
131 135
132 can@980 { 136 can@980 {
133 compatible = "fsl,mpc5 137 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
134 interrupts = <2 18 0>; 138 interrupts = <2 18 0>;
135 reg = <0x980 0x80>; 139 reg = <0x980 0x80>;
136 }; 140 };
137 141
138 gpio_simple: gpio@b00 { 142 gpio_simple: gpio@b00 {
139 compatible = "fsl,mpc5 143 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
140 reg = <0xb00 0x40>; 144 reg = <0xb00 0x40>;
141 interrupts = <1 7 0>; 145 interrupts = <1 7 0>;
142 gpio-controller; 146 gpio-controller;
143 #gpio-cells = <2>; 147 #gpio-cells = <2>;
144 }; 148 };
145 149
146 gpio_wkup: gpio@c00 { 150 gpio_wkup: gpio@c00 {
147 compatible = "fsl,mpc5 151 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
148 reg = <0xc00 0x40>; 152 reg = <0xc00 0x40>;
149 interrupts = <1 8 0 0 153 interrupts = <1 8 0 0 3 0>;
150 gpio-controller; 154 gpio-controller;
151 #gpio-cells = <2>; 155 #gpio-cells = <2>;
152 }; 156 };
153 157
154 spi@f00 { 158 spi@f00 {
155 #address-cells = <1>; 159 #address-cells = <1>;
156 #size-cells = <0>; 160 #size-cells = <0>;
157 compatible = "fsl,mpc5 161 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
158 reg = <0xf00 0x20>; 162 reg = <0xf00 0x20>;
159 interrupts = <2 13 0 2 163 interrupts = <2 13 0 2 14 0>;
160 }; 164 };
161 165
162 usb: usb@1000 { 166 usb: usb@1000 {
163 compatible = "fsl,mpc5 167 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
164 reg = <0x1000 0xff>; 168 reg = <0x1000 0xff>;
165 interrupts = <2 6 0>; 169 interrupts = <2 6 0>;
166 }; 170 };
167 171
168 dma-controller@1200 { 172 dma-controller@1200 {
169 compatible = "fsl,mpc5 173 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
170 reg = <0x1200 0x80>; 174 reg = <0x1200 0x80>;
171 interrupts = <3 0 0 3 175 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
172 3 4 0 3 176 3 4 0 3 5 0 3 6 0 3 7 0
173 3 8 0 3 177 3 8 0 3 9 0 3 10 0 3 11 0
174 3 12 0 178 3 12 0 3 13 0 3 14 0 3 15 0>;
175 }; 179 };
176 180
177 xlb@1f00 { 181 xlb@1f00 {
178 compatible = "fsl,mpc5 182 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
179 reg = <0x1f00 0x100>; 183 reg = <0x1f00 0x100>;
180 }; 184 };
181 185
182 psc1: psc@2000 { 186 psc1: psc@2000 { // PSC1
183 compatible = "fsl,mpc5 187 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
184 reg = <0x2000 0x100>; 188 reg = <0x2000 0x100>;
185 interrupts = <2 1 0>; 189 interrupts = <2 1 0>;
186 }; 190 };
187 191
188 psc2: psc@2200 { 192 psc2: psc@2200 { // PSC2
189 compatible = "fsl,mpc5 193 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
190 reg = <0x2200 0x100>; 194 reg = <0x2200 0x100>;
191 interrupts = <2 2 0>; 195 interrupts = <2 2 0>;
192 }; 196 };
193 197
194 psc3: psc@2400 { 198 psc3: psc@2400 { // PSC3
195 compatible = "fsl,mpc5 199 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
196 reg = <0x2400 0x100>; 200 reg = <0x2400 0x100>;
197 interrupts = <2 3 0>; 201 interrupts = <2 3 0>;
198 }; 202 };
199 203
200 psc4: psc@2600 { 204 psc4: psc@2600 { // PSC4
201 compatible = "fsl,mpc5 205 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
202 reg = <0x2600 0x100>; 206 reg = <0x2600 0x100>;
203 interrupts = <2 11 0>; 207 interrupts = <2 11 0>;
204 }; 208 };
205 209
206 psc5: psc@2800 { 210 psc5: psc@2800 { // PSC5
207 compatible = "fsl,mpc5 211 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
208 reg = <0x2800 0x100>; 212 reg = <0x2800 0x100>;
209 interrupts = <2 12 0>; 213 interrupts = <2 12 0>;
210 }; 214 };
211 215
212 psc6: psc@2c00 { 216 psc6: psc@2c00 { // PSC6
213 compatible = "fsl,mpc5 217 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
214 reg = <0x2c00 0x100>; 218 reg = <0x2c00 0x100>;
215 interrupts = <2 4 0>; 219 interrupts = <2 4 0>;
216 }; 220 };
217 221
218 eth0: ethernet@3000 { 222 eth0: ethernet@3000 {
219 compatible = "fsl,mpc5 223 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
220 reg = <0x3000 0x400>; 224 reg = <0x3000 0x400>;
221 local-mac-address = [ 225 local-mac-address = [ 00 00 00 00 00 00 ];
222 interrupts = <2 5 0>; 226 interrupts = <2 5 0>;
223 }; 227 };
224 228
225 mdio@3000 { 229 mdio@3000 {
226 #address-cells = <1>; 230 #address-cells = <1>;
227 #size-cells = <0>; 231 #size-cells = <0>;
228 compatible = "fsl,mpc5 232 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
229 reg = <0x3000 0x400>; 233 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
230 interrupts = <2 5 0>; 234 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
231 }; 235 };
232 236
233 ata@3a00 { 237 ata@3a00 {
234 compatible = "fsl,mpc5 238 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
235 reg = <0x3a00 0x100>; 239 reg = <0x3a00 0x100>;
236 interrupts = <2 7 0>; 240 interrupts = <2 7 0>;
237 }; 241 };
238 242
239 sclpc@3c00 { 243 sclpc@3c00 {
240 compatible = "fsl,mpc5 244 compatible = "fsl,mpc5200-lpbfifo";
241 reg = <0x3c00 0x60>; 245 reg = <0x3c00 0x60>;
242 interrupts = <2 23 0>; 246 interrupts = <2 23 0>;
243 }; 247 };
244 248
245 i2c@3d00 { 249 i2c@3d00 {
246 #address-cells = <1>; 250 #address-cells = <1>;
247 #size-cells = <0>; 251 #size-cells = <0>;
248 compatible = "fsl,mpc5 252 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
249 reg = <0x3d00 0x40>; 253 reg = <0x3d00 0x40>;
250 interrupts = <2 15 0>; 254 interrupts = <2 15 0>;
251 }; 255 };
252 256
253 i2c@3d40 { 257 i2c@3d40 {
254 #address-cells = <1>; 258 #address-cells = <1>;
255 #size-cells = <0>; 259 #size-cells = <0>;
256 compatible = "fsl,mpc5 260 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
257 reg = <0x3d40 0x40>; 261 reg = <0x3d40 0x40>;
258 interrupts = <2 16 0>; 262 interrupts = <2 16 0>;
259 }; 263 };
260 264
261 sram@8000 { 265 sram@8000 {
262 compatible = "fsl,mpc5 266 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
263 reg = <0x8000 0x4000>; 267 reg = <0x8000 0x4000>;
264 }; 268 };
265 }; 269 };
266 270
267 pci: pci@f0000d00 { 271 pci: pci@f0000d00 {
268 #interrupt-cells = <1>; 272 #interrupt-cells = <1>;
269 #size-cells = <2>; 273 #size-cells = <2>;
270 #address-cells = <3>; 274 #address-cells = <3>;
271 device_type = "pci"; 275 device_type = "pci";
272 compatible = "fsl,mpc5200b-pci 276 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
273 reg = <0xf0000d00 0x100>; 277 reg = <0xf0000d00 0x100>;
274 // interrupt-map-mask = need t 278 // interrupt-map-mask = need to add
275 // interrupt-map = need to add 279 // interrupt-map = need to add
276 clock-frequency = <0>; // From 280 clock-frequency = <0>; // From boot loader
277 interrupts = <2 8 0 2 9 0 2 10 281 interrupts = <2 8 0 2 9 0 2 10 0>;
278 bus-range = <0 0>; 282 bus-range = <0 0>;
279 ranges = <0x42000000 0 0x80000 !! 283 // ranges = need to add
280 <0x02000000 0 0x90000 <<
281 <0x01000000 0 0x00000 <<
282 }; 284 };
283 285
284 localbus: localbus { 286 localbus: localbus {
285 compatible = "fsl,mpc5200b-lpb 287 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
286 #address-cells = <2>; 288 #address-cells = <2>;
287 #size-cells = <1>; 289 #size-cells = <1>;
288 ranges = <0 0 0xfc000000 0x200 290 ranges = <0 0 0xfc000000 0x2000000>;
289 }; 291 };
290 }; 292 };
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