1 // SPDX-License-Identifier: GPL-2.0-or-later <<
2 /* 1 /*
3 * MPC8308RDB Device Tree Source 2 * MPC8308RDB Device Tree Source
4 * 3 *
5 * Copyright 2009 Freescale Semiconductor Inc. 4 * Copyright 2009 Freescale Semiconductor Inc.
6 * Copyright 2010 Ilya Yanok, Emcraft Systems, 5 * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
>> 6 *
>> 7 * This program is free software; you can redistribute it and/or modify it
>> 8 * under the terms of the GNU General Public License as published by the
>> 9 * Free Software Foundation; either version 2 of the License, or (at your
>> 10 * option) any later version.
7 */ 11 */
8 12
9 /dts-v1/; 13 /dts-v1/;
10 14
11 / { 15 / {
12 compatible = "fsl,mpc8308rdb"; 16 compatible = "fsl,mpc8308rdb";
13 #address-cells = <1>; 17 #address-cells = <1>;
14 #size-cells = <1>; 18 #size-cells = <1>;
15 19
16 aliases { 20 aliases {
17 ethernet0 = &enet0; 21 ethernet0 = &enet0;
18 ethernet1 = &enet1; 22 ethernet1 = &enet1;
19 serial0 = &serial0; 23 serial0 = &serial0;
20 serial1 = &serial1; 24 serial1 = &serial1;
21 pci0 = &pci0; 25 pci0 = &pci0;
22 }; 26 };
23 27
24 cpus { 28 cpus {
25 #address-cells = <1>; 29 #address-cells = <1>;
26 #size-cells = <0>; 30 #size-cells = <0>;
27 31
28 PowerPC,8308@0 { 32 PowerPC,8308@0 {
29 device_type = "cpu"; 33 device_type = "cpu";
30 reg = <0x0>; 34 reg = <0x0>;
31 d-cache-line-size = <3 35 d-cache-line-size = <32>;
32 i-cache-line-size = <3 36 i-cache-line-size = <32>;
33 d-cache-size = <16384> 37 d-cache-size = <16384>;
34 i-cache-size = <16384> 38 i-cache-size = <16384>;
35 timebase-frequency = < 39 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; 40 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; 41 clock-frequency = <0>; // from bootloader
38 }; 42 };
39 }; 43 };
40 44
41 memory { 45 memory {
42 device_type = "memory"; 46 device_type = "memory";
43 reg = <0x00000000 0x08000000>; 47 reg = <0x00000000 0x08000000>; // 128MB at 0
44 }; 48 };
45 49
46 localbus@e0005000 { 50 localbus@e0005000 {
47 #address-cells = <2>; 51 #address-cells = <2>;
48 #size-cells = <1>; 52 #size-cells = <1>;
49 compatible = "fsl,mpc8315-elbc 53 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
50 reg = <0xe0005000 0x1000>; 54 reg = <0xe0005000 0x1000>;
51 interrupts = <77 0x8>; 55 interrupts = <77 0x8>;
52 interrupt-parent = <&ipic>; 56 interrupt-parent = <&ipic>;
53 57
54 // CS0 and CS1 are swapped whe 58 // CS0 and CS1 are swapped when
55 // booting from nand, but the 59 // booting from nand, but the
56 // addresses are the same. 60 // addresses are the same.
57 ranges = <0x0 0x0 0xfe000000 0 61 ranges = <0x0 0x0 0xfe000000 0x00800000
58 0x1 0x0 0xe0600000 0 62 0x1 0x0 0xe0600000 0x00002000
59 0x2 0x0 0xf0000000 0 63 0x2 0x0 0xf0000000 0x00020000
60 0x3 0x0 0xfa000000 0 64 0x3 0x0 0xfa000000 0x00008000>;
61 65
62 flash@0,0 { 66 flash@0,0 {
63 #address-cells = <1>; 67 #address-cells = <1>;
64 #size-cells = <1>; 68 #size-cells = <1>;
65 compatible = "cfi-flas 69 compatible = "cfi-flash";
66 reg = <0x0 0x0 0x80000 70 reg = <0x0 0x0 0x800000>;
67 bank-width = <2>; 71 bank-width = <2>;
68 device-width = <1>; 72 device-width = <1>;
69 73
70 u-boot@0 { 74 u-boot@0 {
71 reg = <0x0 0x6 75 reg = <0x0 0x60000>;
72 read-only; 76 read-only;
73 }; 77 };
74 env@60000 { 78 env@60000 {
75 reg = <0x60000 79 reg = <0x60000 0x10000>;
76 }; 80 };
77 env1@70000 { 81 env1@70000 {
78 reg = <0x70000 82 reg = <0x70000 0x10000>;
79 }; 83 };
80 kernel@80000 { 84 kernel@80000 {
81 reg = <0x80000 85 reg = <0x80000 0x200000>;
82 }; 86 };
83 dtb@280000 { 87 dtb@280000 {
84 reg = <0x28000 88 reg = <0x280000 0x10000>;
85 }; 89 };
86 ramdisk@290000 { 90 ramdisk@290000 {
87 reg = <0x29000 91 reg = <0x290000 0x570000>;
88 }; 92 };
89 }; 93 };
90 94
91 nand@1,0 { 95 nand@1,0 {
92 #address-cells = <1>; 96 #address-cells = <1>;
93 #size-cells = <1>; 97 #size-cells = <1>;
94 compatible = "fsl,mpc8 98 compatible = "fsl,mpc8315-fcm-nand",
95 "fsl,elbc 99 "fsl,elbc-fcm-nand";
96 reg = <0x1 0x0 0x2000> 100 reg = <0x1 0x0 0x2000>;
97 101
98 jffs2@0 { 102 jffs2@0 {
99 reg = <0x0 0x2 103 reg = <0x0 0x2000000>;
100 }; 104 };
101 }; 105 };
102 }; 106 };
103 107
104 immr@e0000000 { 108 immr@e0000000 {
105 #address-cells = <1>; 109 #address-cells = <1>;
106 #size-cells = <1>; 110 #size-cells = <1>;
107 device_type = "soc"; 111 device_type = "soc";
108 compatible = "fsl,mpc8308-immr 112 compatible = "fsl,mpc8308-immr", "simple-bus";
109 ranges = <0 0xe0000000 0x00100 113 ranges = <0 0xe0000000 0x00100000>;
110 reg = <0xe0000000 0x00000200>; 114 reg = <0xe0000000 0x00000200>;
111 bus-frequency = <0>; 115 bus-frequency = <0>;
112 116
113 i2c@3000 { 117 i2c@3000 {
114 #address-cells = <1>; 118 #address-cells = <1>;
115 #size-cells = <0>; 119 #size-cells = <0>;
116 cell-index = <0>; 120 cell-index = <0>;
117 compatible = "fsl-i2c" 121 compatible = "fsl-i2c";
118 reg = <0x3000 0x100>; 122 reg = <0x3000 0x100>;
119 interrupts = <14 0x8>; 123 interrupts = <14 0x8>;
120 interrupt-parent = <&i 124 interrupt-parent = <&ipic>;
121 dfsrr; 125 dfsrr;
122 rtc@68 { 126 rtc@68 {
123 compatible = " 127 compatible = "dallas,ds1339";
124 reg = <0x68>; 128 reg = <0x68>;
125 }; 129 };
126 }; 130 };
127 131
128 usb@23000 { 132 usb@23000 {
129 compatible = "fsl-usb2 133 compatible = "fsl-usb2-dr";
130 reg = <0x23000 0x1000> 134 reg = <0x23000 0x1000>;
131 #address-cells = <1>; 135 #address-cells = <1>;
132 #size-cells = <0>; 136 #size-cells = <0>;
133 interrupt-parent = <&i 137 interrupt-parent = <&ipic>;
134 interrupts = <38 0x8>; 138 interrupts = <38 0x8>;
135 dr_mode = "peripheral" 139 dr_mode = "peripheral";
136 phy_type = "ulpi"; 140 phy_type = "ulpi";
137 }; 141 };
138 142
139 enet0: ethernet@24000 { 143 enet0: ethernet@24000 {
140 #address-cells = <1>; 144 #address-cells = <1>;
141 #size-cells = <1>; 145 #size-cells = <1>;
142 ranges = <0x0 0x24000 146 ranges = <0x0 0x24000 0x1000>;
143 147
144 cell-index = <0>; 148 cell-index = <0>;
145 device_type = "network 149 device_type = "network";
146 model = "eTSEC"; 150 model = "eTSEC";
147 compatible = "gianfar" 151 compatible = "gianfar";
148 reg = <0x24000 0x1000> 152 reg = <0x24000 0x1000>;
149 local-mac-address = [ 153 local-mac-address = [ 00 00 00 00 00 00 ];
150 interrupts = <32 0x8 3 154 interrupts = <32 0x8 33 0x8 34 0x8>;
151 interrupt-parent = <&i 155 interrupt-parent = <&ipic>;
152 tbi-handle = < &tbi0 > 156 tbi-handle = < &tbi0 >;
153 phy-handle = < &phy2 > 157 phy-handle = < &phy2 >;
154 fsl,magic-packet; 158 fsl,magic-packet;
155 159
156 mdio@520 { 160 mdio@520 {
157 #address-cells 161 #address-cells = <1>;
158 #size-cells = 162 #size-cells = <0>;
159 compatible = " 163 compatible = "fsl,gianfar-mdio";
160 reg = <0x520 0 164 reg = <0x520 0x20>;
161 phy2: ethernet 165 phy2: ethernet-phy@2 {
162 interr 166 interrupt-parent = <&ipic>;
163 interr 167 interrupts = <17 0x8>;
164 reg = 168 reg = <0x2>;
165 }; 169 };
166 tbi0: tbi-phy@ 170 tbi0: tbi-phy@11 {
167 reg = 171 reg = <0x11>;
168 device 172 device_type = "tbi-phy";
169 }; 173 };
170 }; 174 };
171 }; 175 };
172 176
173 enet1: ethernet@25000 { 177 enet1: ethernet@25000 {
174 #address-cells = <1>; 178 #address-cells = <1>;
175 #size-cells = <1>; 179 #size-cells = <1>;
176 cell-index = <1>; 180 cell-index = <1>;
177 device_type = "network 181 device_type = "network";
178 model = "eTSEC"; 182 model = "eTSEC";
179 compatible = "gianfar" 183 compatible = "gianfar";
180 reg = <0x25000 0x1000> 184 reg = <0x25000 0x1000>;
181 ranges = <0x0 0x25000 185 ranges = <0x0 0x25000 0x1000>;
182 local-mac-address = [ 186 local-mac-address = [ 00 00 00 00 00 00 ];
183 interrupts = <35 0x8 3 187 interrupts = <35 0x8 36 0x8 37 0x8>;
184 interrupt-parent = <&i 188 interrupt-parent = <&ipic>;
185 tbi-handle = < &tbi1 > 189 tbi-handle = < &tbi1 >;
186 /* Vitesse 7385 isn't 190 /* Vitesse 7385 isn't on the MDIO bus */
187 fixed-link = <1 1 1000 191 fixed-link = <1 1 1000 0 0>;
188 fsl,magic-packet; 192 fsl,magic-packet;
189 193
190 mdio@520 { 194 mdio@520 {
191 #address-cells 195 #address-cells = <1>;
192 #size-cells = 196 #size-cells = <0>;
193 compatible = " 197 compatible = "fsl,gianfar-tbi";
194 reg = <0x520 0 198 reg = <0x520 0x20>;
195 199
196 tbi1: tbi-phy@ 200 tbi1: tbi-phy@11 {
197 reg = 201 reg = <0x11>;
198 device 202 device_type = "tbi-phy";
199 }; 203 };
200 }; 204 };
201 }; 205 };
202 206
203 serial0: serial@4500 { 207 serial0: serial@4500 {
204 cell-index = <0>; 208 cell-index = <0>;
205 device_type = "serial" 209 device_type = "serial";
206 compatible = "fsl,ns16 210 compatible = "fsl,ns16550", "ns16550";
207 reg = <0x4500 0x100>; 211 reg = <0x4500 0x100>;
208 clock-frequency = <133 212 clock-frequency = <133333333>;
209 interrupts = <9 0x8>; 213 interrupts = <9 0x8>;
210 interrupt-parent = <&i 214 interrupt-parent = <&ipic>;
211 }; 215 };
212 216
213 serial1: serial@4600 { 217 serial1: serial@4600 {
214 cell-index = <1>; 218 cell-index = <1>;
215 device_type = "serial" 219 device_type = "serial";
216 compatible = "fsl,ns16 220 compatible = "fsl,ns16550", "ns16550";
217 reg = <0x4600 0x100>; 221 reg = <0x4600 0x100>;
218 clock-frequency = <133 222 clock-frequency = <133333333>;
219 interrupts = <10 0x8>; 223 interrupts = <10 0x8>;
220 interrupt-parent = <&i 224 interrupt-parent = <&ipic>;
221 }; 225 };
222 226
223 gpio@c00 { 227 gpio@c00 {
224 #gpio-cells = <2>; 228 #gpio-cells = <2>;
225 device_type = "gpio"; 229 device_type = "gpio";
226 compatible = "fsl,mpc8 230 compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
227 reg = <0xc00 0x18>; 231 reg = <0xc00 0x18>;
228 interrupts = <74 0x8>; 232 interrupts = <74 0x8>;
229 interrupt-parent = <&i 233 interrupt-parent = <&ipic>;
230 gpio-controller; 234 gpio-controller;
231 }; 235 };
232 236
233 /* IPIC 237 /* IPIC
234 * interrupts cell = <intr #, 238 * interrupts cell = <intr #, sense>
235 * sense values match linux IO 239 * sense values match linux IORESOURCE_IRQ_* defines:
236 * sense == 8: Level, low asse 240 * sense == 8: Level, low assertion
237 * sense == 2: Edge, high-to-l 241 * sense == 2: Edge, high-to-low change
238 */ 242 */
239 ipic: interrupt-controller@700 243 ipic: interrupt-controller@700 {
240 compatible = "fsl,ipic 244 compatible = "fsl,ipic";
241 interrupt-controller; 245 interrupt-controller;
242 #address-cells = <0>; 246 #address-cells = <0>;
243 #interrupt-cells = <2> 247 #interrupt-cells = <2>;
244 reg = <0x700 0x100>; 248 reg = <0x700 0x100>;
245 device_type = "ipic"; 249 device_type = "ipic";
246 }; 250 };
247 251
248 ipic-msi@7c0 { 252 ipic-msi@7c0 {
249 compatible = "fsl,ipic 253 compatible = "fsl,ipic-msi";
250 reg = <0x7c0 0x40>; 254 reg = <0x7c0 0x40>;
251 msi-available-ranges = 255 msi-available-ranges = <0x0 0x100>;
252 interrupts = < 0x43 0x 256 interrupts = < 0x43 0x8
253 0x4 0 257 0x4 0x8
254 0x51 0 258 0x51 0x8
255 0x52 0 259 0x52 0x8
256 0x56 0 260 0x56 0x8
257 0x57 0 261 0x57 0x8
258 0x58 0 262 0x58 0x8
259 0x59 0 263 0x59 0x8 >;
260 interrupt-parent = < & 264 interrupt-parent = < &ipic >;
261 }; 265 };
262 266
263 dma@2c000 { 267 dma@2c000 {
264 compatible = "fsl,mpc8 268 compatible = "fsl,mpc8308-dma";
265 reg = <0x2c000 0x1800> 269 reg = <0x2c000 0x1800>;
266 interrupts = <3 0x8 270 interrupts = <3 0x8
267 94 0x8 271 94 0x8>;
268 interrupt-parent = < & 272 interrupt-parent = < &ipic >;
269 }; 273 };
270 274
271 }; 275 };
272 276
273 pci0: pcie@e0009000 { 277 pci0: pcie@e0009000 {
274 #address-cells = <3>; 278 #address-cells = <3>;
275 #size-cells = <2>; 279 #size-cells = <2>;
276 #interrupt-cells = <1>; 280 #interrupt-cells = <1>;
277 device_type = "pci"; 281 device_type = "pci";
278 compatible = "fsl,mpc8308-pcie 282 compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
279 reg = <0xe0009000 0x00001000 283 reg = <0xe0009000 0x00001000
280 0xb0000000 0x01000000> 284 0xb0000000 0x01000000>;
281 ranges = <0x02000000 0 0xa0000 285 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
282 0x01000000 0 0x00000 286 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
283 bus-range = <0 0>; 287 bus-range = <0 0>;
284 interrupt-map-mask = <0xf800 0 288 interrupt-map-mask = <0xf800 0 0 7>;
285 interrupt-map = <0 0 0 1 &ipic 289 interrupt-map = <0 0 0 1 &ipic 1 8
286 0 0 0 2 &ipic 290 0 0 0 2 &ipic 1 8
287 0 0 0 3 &ipic 291 0 0 0 3 &ipic 1 8
288 0 0 0 4 &ipic 292 0 0 0 4 &ipic 1 8>;
289 interrupts = <0x1 0x8>; 293 interrupts = <0x1 0x8>;
290 interrupt-parent = <&ipic>; 294 interrupt-parent = <&ipic>;
291 clock-frequency = <0>; 295 clock-frequency = <0>;
292 296
293 pcie@0 { 297 pcie@0 {
294 #address-cells = <3>; 298 #address-cells = <3>;
295 #size-cells = <2>; 299 #size-cells = <2>;
296 device_type = "pci"; 300 device_type = "pci";
297 reg = <0 0 0 0 0>; 301 reg = <0 0 0 0 0>;
298 ranges = <0x02000000 0 302 ranges = <0x02000000 0 0xa0000000
299 0x02000000 0 303 0x02000000 0 0xa0000000
300 0 0x10000000 304 0 0x10000000
301 0x01000000 0 305 0x01000000 0 0x00000000
302 0x01000000 0 306 0x01000000 0 0x00000000
303 0 0x00800000 307 0 0x00800000>;
304 }; 308 };
305 }; 309 };
306 }; 310 };
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