1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * MPC8313E RDB Device Tree Source 3 * MPC8313E RDB Device Tree Source
4 * 4 *
5 * Copyright 2005, 2006, 2007 Freescale Semico 5 * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc.
6 */ 6 */
7 7
8 /dts-v1/; 8 /dts-v1/;
9 9
10 / { 10 / {
11 model = "MPC8313ERDB"; 11 model = "MPC8313ERDB";
12 compatible = "MPC8313ERDB", "MPC831xRD 12 compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB";
13 #address-cells = <1>; 13 #address-cells = <1>;
14 #size-cells = <1>; 14 #size-cells = <1>;
15 15
16 aliases { 16 aliases {
17 ethernet0 = &enet0; 17 ethernet0 = &enet0;
18 ethernet1 = &enet1; 18 ethernet1 = &enet1;
19 serial0 = &serial0; 19 serial0 = &serial0;
20 serial1 = &serial1; 20 serial1 = &serial1;
21 pci0 = &pci0; 21 pci0 = &pci0;
22 }; 22 };
23 23
24 cpus { 24 cpus {
25 #address-cells = <1>; 25 #address-cells = <1>;
26 #size-cells = <0>; 26 #size-cells = <0>;
27 27
28 PowerPC,8313@0 { 28 PowerPC,8313@0 {
29 device_type = "cpu"; 29 device_type = "cpu";
30 reg = <0x0>; 30 reg = <0x0>;
31 d-cache-line-size = <3 31 d-cache-line-size = <32>;
32 i-cache-line-size = <3 32 i-cache-line-size = <32>;
33 d-cache-size = <16384> 33 d-cache-size = <16384>;
34 i-cache-size = <16384> 34 i-cache-size = <16384>;
35 timebase-frequency = < 35 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; 36 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; 37 clock-frequency = <0>; // from bootloader
38 }; 38 };
39 }; 39 };
40 40
41 memory { 41 memory {
42 device_type = "memory"; 42 device_type = "memory";
43 reg = <0x00000000 0x08000000>; 43 reg = <0x00000000 0x08000000>; // 128MB at 0
44 }; 44 };
45 45
46 localbus@e0005000 { 46 localbus@e0005000 {
47 #address-cells = <2>; 47 #address-cells = <2>;
48 #size-cells = <1>; 48 #size-cells = <1>;
49 compatible = "fsl,mpc8313-elbc 49 compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";
50 reg = <0xe0005000 0x1000>; 50 reg = <0xe0005000 0x1000>;
51 interrupts = <77 0x8>; 51 interrupts = <77 0x8>;
52 interrupt-parent = <&ipic>; 52 interrupt-parent = <&ipic>;
53 53
54 // CS0 and CS1 are swapped whe 54 // CS0 and CS1 are swapped when
55 // booting from nand, but the 55 // booting from nand, but the
56 // addresses are the same. 56 // addresses are the same.
57 ranges = <0x0 0x0 0xfe000000 0 57 ranges = <0x0 0x0 0xfe000000 0x00800000
58 0x1 0x0 0xe2800000 0 58 0x1 0x0 0xe2800000 0x00008000
59 0x2 0x0 0xf0000000 0 59 0x2 0x0 0xf0000000 0x00020000
60 0x3 0x0 0xfa000000 0 60 0x3 0x0 0xfa000000 0x00008000>;
61 61
62 flash@0,0 { 62 flash@0,0 {
63 #address-cells = <1>; 63 #address-cells = <1>;
64 #size-cells = <1>; 64 #size-cells = <1>;
65 compatible = "cfi-flas 65 compatible = "cfi-flash";
66 reg = <0x0 0x0 0x80000 66 reg = <0x0 0x0 0x800000>;
67 bank-width = <2>; 67 bank-width = <2>;
68 device-width = <1>; 68 device-width = <1>;
69 }; 69 };
70 70
71 nand@1,0 { 71 nand@1,0 {
72 #address-cells = <1>; 72 #address-cells = <1>;
73 #size-cells = <1>; 73 #size-cells = <1>;
74 compatible = "fsl,mpc8 74 compatible = "fsl,mpc8313-fcm-nand",
75 "fsl,elbc 75 "fsl,elbc-fcm-nand";
76 reg = <0x1 0x0 0x2000> 76 reg = <0x1 0x0 0x2000>;
77 77
78 u-boot@0 { 78 u-boot@0 {
79 reg = <0x0 0x1 79 reg = <0x0 0x100000>;
80 read-only; 80 read-only;
81 }; 81 };
82 82
83 kernel@100000 { 83 kernel@100000 {
84 reg = <0x10000 84 reg = <0x100000 0x300000>;
85 }; 85 };
86 86
87 fs@400000 { 87 fs@400000 {
88 reg = <0x40000 88 reg = <0x400000 0x1c00000>;
89 }; 89 };
90 }; 90 };
91 }; 91 };
92 92
93 soc8313@e0000000 { 93 soc8313@e0000000 {
94 #address-cells = <1>; 94 #address-cells = <1>;
95 #size-cells = <1>; 95 #size-cells = <1>;
96 device_type = "soc"; 96 device_type = "soc";
97 compatible = "simple-bus"; 97 compatible = "simple-bus";
98 ranges = <0x0 0xe0000000 0x001 98 ranges = <0x0 0xe0000000 0x00100000>;
99 reg = <0xe0000000 0x00000200>; 99 reg = <0xe0000000 0x00000200>;
100 bus-frequency = <0>; 100 bus-frequency = <0>;
101 101
102 wdt@200 { 102 wdt@200 {
103 device_type = "watchdo 103 device_type = "watchdog";
104 compatible = "mpc83xx_ 104 compatible = "mpc83xx_wdt";
105 reg = <0x200 0x100>; 105 reg = <0x200 0x100>;
106 }; 106 };
107 107
108 sleep-nexus { 108 sleep-nexus {
109 #address-cells = <1>; 109 #address-cells = <1>;
110 #size-cells = <1>; 110 #size-cells = <1>;
111 compatible = "simple-b 111 compatible = "simple-bus";
112 sleep = <&pmc 0x030000 112 sleep = <&pmc 0x03000000>;
113 ranges; 113 ranges;
114 114
115 i2c@3000 { 115 i2c@3000 {
116 #address-cells 116 #address-cells = <1>;
117 #size-cells = 117 #size-cells = <0>;
118 cell-index = < 118 cell-index = <0>;
119 compatible = " 119 compatible = "fsl-i2c";
120 reg = <0x3000 120 reg = <0x3000 0x100>;
121 interrupts = < 121 interrupts = <14 0x8>;
122 interrupt-pare 122 interrupt-parent = <&ipic>;
123 dfsrr; 123 dfsrr;
124 rtc@68 { 124 rtc@68 {
125 compat 125 compatible = "dallas,ds1339";
126 reg = 126 reg = <0x68>;
127 }; 127 };
128 }; 128 };
129 129
130 crypto@30000 { 130 crypto@30000 {
131 compatible = " 131 compatible = "fsl,sec2.2", "fsl,sec2.1",
132 " 132 "fsl,sec2.0";
133 reg = <0x30000 133 reg = <0x30000 0x10000>;
134 interrupts = < 134 interrupts = <11 0x8>;
135 interrupt-pare 135 interrupt-parent = <&ipic>;
136 fsl,num-channe 136 fsl,num-channels = <1>;
137 fsl,channel-fi 137 fsl,channel-fifo-len = <24>;
138 fsl,exec-units 138 fsl,exec-units-mask = <0x4c>;
139 fsl,descriptor 139 fsl,descriptor-types-mask = <0x0122003f>;
140 }; 140 };
141 }; 141 };
142 142
143 i2c@3100 { 143 i2c@3100 {
144 #address-cells = <1>; 144 #address-cells = <1>;
145 #size-cells = <0>; 145 #size-cells = <0>;
146 cell-index = <1>; 146 cell-index = <1>;
147 compatible = "fsl-i2c" 147 compatible = "fsl-i2c";
148 reg = <0x3100 0x100>; 148 reg = <0x3100 0x100>;
149 interrupts = <15 0x8>; 149 interrupts = <15 0x8>;
150 interrupt-parent = <&i 150 interrupt-parent = <&ipic>;
151 dfsrr; 151 dfsrr;
152 }; 152 };
153 153
154 spi@7000 { 154 spi@7000 {
155 cell-index = <0>; 155 cell-index = <0>;
156 compatible = "fsl,spi" 156 compatible = "fsl,spi";
157 reg = <0x7000 0x1000>; 157 reg = <0x7000 0x1000>;
158 interrupts = <16 0x8>; 158 interrupts = <16 0x8>;
159 interrupt-parent = <&i 159 interrupt-parent = <&ipic>;
160 mode = "cpu"; 160 mode = "cpu";
161 }; 161 };
162 162
163 /* phy type (ULPI, UTMI, UTMI_ 163 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
164 usb@23000 { 164 usb@23000 {
165 compatible = "fsl-usb2 165 compatible = "fsl-usb2-dr";
166 reg = <0x23000 0x1000> 166 reg = <0x23000 0x1000>;
167 #address-cells = <1>; 167 #address-cells = <1>;
168 #size-cells = <0>; 168 #size-cells = <0>;
169 interrupt-parent = <&i 169 interrupt-parent = <&ipic>;
170 interrupts = <38 0x8>; 170 interrupts = <38 0x8>;
171 phy_type = "utmi_wide" 171 phy_type = "utmi_wide";
172 sleep = <&pmc 0x003000 172 sleep = <&pmc 0x00300000>;
173 }; 173 };
174 174
175 ptp_clock@24E00 { 175 ptp_clock@24E00 {
176 compatible = "fsl,etse 176 compatible = "fsl,etsec-ptp";
177 reg = <0x24E00 0xB0>; 177 reg = <0x24E00 0xB0>;
178 interrupts = <12 0x8 1 178 interrupts = <12 0x8 13 0x8>;
179 interrupt-parent = < & 179 interrupt-parent = < &ipic >;
180 fsl,tclk-period = <10> 180 fsl,tclk-period = <10>;
181 fsl,tmr-prsc = <100 181 fsl,tmr-prsc = <100>;
182 fsl,tmr-add = <0x9 182 fsl,tmr-add = <0x999999A4>;
183 fsl,tmr-fiper1 = <0x3 183 fsl,tmr-fiper1 = <0x3B9AC9F6>;
184 fsl,tmr-fiper2 = <0x0 184 fsl,tmr-fiper2 = <0x00018696>;
185 fsl,max-adj = <659 185 fsl,max-adj = <659999998>;
186 }; 186 };
187 187
188 enet0: ethernet@24000 { 188 enet0: ethernet@24000 {
189 #address-cells = <1>; 189 #address-cells = <1>;
190 #size-cells = <1>; 190 #size-cells = <1>;
191 sleep = <&pmc 0x200000 191 sleep = <&pmc 0x20000000>;
192 ranges = <0x0 0x24000 192 ranges = <0x0 0x24000 0x1000>;
193 193
194 cell-index = <0>; 194 cell-index = <0>;
195 device_type = "network 195 device_type = "network";
196 model = "eTSEC"; 196 model = "eTSEC";
197 compatible = "gianfar" 197 compatible = "gianfar";
198 reg = <0x24000 0x1000> 198 reg = <0x24000 0x1000>;
199 local-mac-address = [ 199 local-mac-address = [ 00 00 00 00 00 00 ];
200 interrupts = <37 0x8 3 200 interrupts = <37 0x8 36 0x8 35 0x8>;
201 interrupt-parent = <&i 201 interrupt-parent = <&ipic>;
202 tbi-handle = < &tbi0 > 202 tbi-handle = < &tbi0 >;
203 /* Vitesse 7385 isn't 203 /* Vitesse 7385 isn't on the MDIO bus */
204 fixed-link = <1 1 1000 204 fixed-link = <1 1 1000 0 0>;
205 fsl,magic-packet; 205 fsl,magic-packet;
206 206
207 mdio@520 { 207 mdio@520 {
208 #address-cells 208 #address-cells = <1>;
209 #size-cells = 209 #size-cells = <0>;
210 compatible = " 210 compatible = "fsl,gianfar-mdio";
211 reg = <0x520 0 211 reg = <0x520 0x20>;
212 phy4: ethernet 212 phy4: ethernet-phy@4 {
213 interr 213 interrupt-parent = <&ipic>;
214 interr 214 interrupts = <20 0x8>;
215 reg = 215 reg = <0x4>;
216 }; 216 };
217 tbi0: tbi-phy@ 217 tbi0: tbi-phy@11 {
218 reg = 218 reg = <0x11>;
219 device 219 device_type = "tbi-phy";
220 }; 220 };
221 }; 221 };
222 }; 222 };
223 223
224 enet1: ethernet@25000 { 224 enet1: ethernet@25000 {
225 #address-cells = <1>; 225 #address-cells = <1>;
226 #size-cells = <1>; 226 #size-cells = <1>;
227 cell-index = <1>; 227 cell-index = <1>;
228 device_type = "network 228 device_type = "network";
229 model = "eTSEC"; 229 model = "eTSEC";
230 compatible = "gianfar" 230 compatible = "gianfar";
231 reg = <0x25000 0x1000> 231 reg = <0x25000 0x1000>;
232 ranges = <0x0 0x25000 232 ranges = <0x0 0x25000 0x1000>;
233 local-mac-address = [ 233 local-mac-address = [ 00 00 00 00 00 00 ];
234 interrupts = <34 0x8 3 234 interrupts = <34 0x8 33 0x8 32 0x8>;
235 interrupt-parent = <&i 235 interrupt-parent = <&ipic>;
236 tbi-handle = < &tbi1 > 236 tbi-handle = < &tbi1 >;
237 phy-handle = < &phy4 > 237 phy-handle = < &phy4 >;
238 sleep = <&pmc 0x100000 238 sleep = <&pmc 0x10000000>;
239 fsl,magic-packet; 239 fsl,magic-packet;
240 240
241 mdio@520 { 241 mdio@520 {
242 #address-cells 242 #address-cells = <1>;
243 #size-cells = 243 #size-cells = <0>;
244 compatible = " 244 compatible = "fsl,gianfar-tbi";
245 reg = <0x520 0 245 reg = <0x520 0x20>;
246 246
247 tbi1: tbi-phy@ 247 tbi1: tbi-phy@11 {
248 reg = 248 reg = <0x11>;
249 device 249 device_type = "tbi-phy";
250 }; 250 };
251 }; 251 };
252 252
253 253
254 }; 254 };
255 255
256 serial0: serial@4500 { 256 serial0: serial@4500 {
257 cell-index = <0>; 257 cell-index = <0>;
258 device_type = "serial" 258 device_type = "serial";
259 compatible = "fsl,ns16 259 compatible = "fsl,ns16550", "ns16550";
260 reg = <0x4500 0x100>; 260 reg = <0x4500 0x100>;
261 clock-frequency = <0>; 261 clock-frequency = <0>;
262 interrupts = <9 0x8>; 262 interrupts = <9 0x8>;
263 interrupt-parent = <&i 263 interrupt-parent = <&ipic>;
264 }; 264 };
265 265
266 serial1: serial@4600 { 266 serial1: serial@4600 {
267 cell-index = <1>; 267 cell-index = <1>;
268 device_type = "serial" 268 device_type = "serial";
269 compatible = "fsl,ns16 269 compatible = "fsl,ns16550", "ns16550";
270 reg = <0x4600 0x100>; 270 reg = <0x4600 0x100>;
271 clock-frequency = <0>; 271 clock-frequency = <0>;
272 interrupts = <10 0x8>; 272 interrupts = <10 0x8>;
273 interrupt-parent = <&i 273 interrupt-parent = <&ipic>;
274 }; 274 };
275 275
276 /* IPIC 276 /* IPIC
277 * interrupts cell = <intr #, 277 * interrupts cell = <intr #, sense>
278 * sense values match linux IO 278 * sense values match linux IORESOURCE_IRQ_* defines:
279 * sense == 8: Level, low asse 279 * sense == 8: Level, low assertion
280 * sense == 2: Edge, high-to-l 280 * sense == 2: Edge, high-to-low change
281 */ 281 */
282 ipic: pic@700 { 282 ipic: pic@700 {
283 interrupt-controller; 283 interrupt-controller;
284 #address-cells = <0>; 284 #address-cells = <0>;
285 #interrupt-cells = <2> 285 #interrupt-cells = <2>;
286 reg = <0x700 0x100>; 286 reg = <0x700 0x100>;
287 device_type = "ipic"; 287 device_type = "ipic";
288 }; 288 };
289 289
290 pmc: power@b00 { 290 pmc: power@b00 {
291 compatible = "fsl,mpc8 291 compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
292 reg = <0xb00 0x100 0xa 292 reg = <0xb00 0x100 0xa00 0x100>;
293 interrupts = <80 8>; 293 interrupts = <80 8>;
294 interrupt-parent = <&i 294 interrupt-parent = <&ipic>;
295 fsl,mpc8313-wakeup-tim 295 fsl,mpc8313-wakeup-timer = <>m1>;
296 296
297 /* Remove this (or cha 297 /* Remove this (or change to "okay") if you have
298 * a REVA3 or later bo 298 * a REVA3 or later board, if you apply one of the
299 * workarounds listed 299 * workarounds listed in section 8.5 of the board
300 * manual, or if you a 300 * manual, or if you are adapting this device tree
301 * to a different boar 301 * to a different board.
302 */ 302 */
303 status = "fail"; 303 status = "fail";
304 }; 304 };
305 305
306 gtm1: timer@500 { 306 gtm1: timer@500 {
307 compatible = "fsl,mpc8 307 compatible = "fsl,mpc8313-gtm", "fsl,gtm";
308 reg = <0x500 0x100>; 308 reg = <0x500 0x100>;
309 interrupts = <90 8 78 309 interrupts = <90 8 78 8 84 8 72 8>;
310 interrupt-parent = <&i 310 interrupt-parent = <&ipic>;
311 }; 311 };
312 312
313 timer@600 { 313 timer@600 {
314 compatible = "fsl,mpc8 314 compatible = "fsl,mpc8313-gtm", "fsl,gtm";
315 reg = <0x600 0x100>; 315 reg = <0x600 0x100>;
316 interrupts = <91 8 79 316 interrupts = <91 8 79 8 85 8 73 8>;
317 interrupt-parent = <&i 317 interrupt-parent = <&ipic>;
318 }; 318 };
319 }; 319 };
320 320
321 sleep-nexus { 321 sleep-nexus {
322 #address-cells = <1>; 322 #address-cells = <1>;
323 #size-cells = <1>; 323 #size-cells = <1>;
324 compatible = "simple-bus"; 324 compatible = "simple-bus";
325 sleep = <&pmc 0x00010000>; 325 sleep = <&pmc 0x00010000>;
326 ranges; 326 ranges;
327 327
328 pci0: pci@e0008500 { 328 pci0: pci@e0008500 {
329 cell-index = <1>; 329 cell-index = <1>;
330 interrupt-map-mask = < 330 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
331 interrupt-map = < 331 interrupt-map = <
332 /* IDS 332 /* IDSEL 0x0E -mini PCI */
333 0x700 333 0x7000 0x0 0x0 0x1 &ipic 18 0x8
334 0x700 334 0x7000 0x0 0x0 0x2 &ipic 18 0x8
335 0x700 335 0x7000 0x0 0x0 0x3 &ipic 18 0x8
336 0x700 336 0x7000 0x0 0x0 0x4 &ipic 18 0x8
337 337
338 /* IDS 338 /* IDSEL 0x0F - PCI slot */
339 0x780 339 0x7800 0x0 0x0 0x1 &ipic 17 0x8
340 0x780 340 0x7800 0x0 0x0 0x2 &ipic 18 0x8
341 0x780 341 0x7800 0x0 0x0 0x3 &ipic 17 0x8
342 0x780 342 0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
343 interrupt-parent = <&i 343 interrupt-parent = <&ipic>;
344 interrupts = <66 0x8>; 344 interrupts = <66 0x8>;
345 bus-range = <0x0 0x0>; 345 bus-range = <0x0 0x0>;
346 ranges = <0x02000000 0 346 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
347 0x42000000 0 347 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
348 0x01000000 0 348 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
349 clock-frequency = <666 349 clock-frequency = <66666666>;
350 #interrupt-cells = <1> 350 #interrupt-cells = <1>;
351 #size-cells = <2>; 351 #size-cells = <2>;
352 #address-cells = <3>; 352 #address-cells = <3>;
353 reg = <0xe0008500 0x10 353 reg = <0xe0008500 0x100 /* internal registers */
354 0xe0008300 0x8> 354 0xe0008300 0x8>; /* config space access registers */
355 compatible = "fsl,mpc8 355 compatible = "fsl,mpc8349-pci";
356 device_type = "pci"; 356 device_type = "pci";
357 }; 357 };
358 358
359 dma@82a8 { 359 dma@82a8 {
360 #address-cells = <1>; 360 #address-cells = <1>;
361 #size-cells = <1>; 361 #size-cells = <1>;
362 compatible = "fsl,mpc8 362 compatible = "fsl,mpc8313-dma", "fsl,elo-dma";
363 reg = <0xe00082a8 4>; 363 reg = <0xe00082a8 4>;
364 ranges = <0 0xe0008100 364 ranges = <0 0xe0008100 0x1a8>;
365 interrupt-parent = <&i 365 interrupt-parent = <&ipic>;
366 interrupts = <71 8>; 366 interrupts = <71 8>;
367 367
368 dma-channel@0 { 368 dma-channel@0 {
369 compatible = " 369 compatible = "fsl,mpc8313-dma-channel",
370 " 370 "fsl,elo-dma-channel";
371 reg = <0 0x28> 371 reg = <0 0x28>;
372 interrupt-pare 372 interrupt-parent = <&ipic>;
373 interrupts = < 373 interrupts = <71 8>;
374 cell-index = < 374 cell-index = <0>;
375 }; 375 };
376 376
377 dma-channel@80 { 377 dma-channel@80 {
378 compatible = " 378 compatible = "fsl,mpc8313-dma-channel",
379 " 379 "fsl,elo-dma-channel";
380 reg = <0x80 0x 380 reg = <0x80 0x28>;
381 interrupt-pare 381 interrupt-parent = <&ipic>;
382 interrupts = < 382 interrupts = <71 8>;
383 cell-index = < 383 cell-index = <1>;
384 }; 384 };
385 385
386 dma-channel@100 { 386 dma-channel@100 {
387 compatible = " 387 compatible = "fsl,mpc8313-dma-channel",
388 " 388 "fsl,elo-dma-channel";
389 reg = <0x100 0 389 reg = <0x100 0x28>;
390 interrupt-pare 390 interrupt-parent = <&ipic>;
391 interrupts = < 391 interrupts = <71 8>;
392 cell-index = < 392 cell-index = <2>;
393 }; 393 };
394 394
395 dma-channel@180 { 395 dma-channel@180 {
396 compatible = " 396 compatible = "fsl,mpc8313-dma-channel",
397 " 397 "fsl,elo-dma-channel";
398 reg = <0x180 0 398 reg = <0x180 0x28>;
399 interrupt-pare 399 interrupt-parent = <&ipic>;
400 interrupts = < 400 interrupts = <71 8>;
401 cell-index = < 401 cell-index = <3>;
402 }; 402 };
403 }; 403 };
404 }; 404 };
405 }; 405 };
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