1 // SPDX-License-Identifier: GPL-2.0-or-later <<
2 /* 1 /*
3 * MPC8315E RDB Device Tree Source 2 * MPC8315E RDB Device Tree Source
4 * 3 *
5 * Copyright 2007 Freescale Semiconductor Inc. 4 * Copyright 2007 Freescale Semiconductor Inc.
>> 5 *
>> 6 * This program is free software; you can redistribute it and/or modify it
>> 7 * under the terms of the GNU General Public License as published by the
>> 8 * Free Software Foundation; either version 2 of the License, or (at your
>> 9 * option) any later version.
6 */ 10 */
7 11
8 /dts-v1/; 12 /dts-v1/;
9 13
10 / { 14 / {
11 compatible = "fsl,mpc8315erdb"; 15 compatible = "fsl,mpc8315erdb";
12 #address-cells = <1>; 16 #address-cells = <1>;
13 #size-cells = <1>; 17 #size-cells = <1>;
14 18
15 aliases { 19 aliases {
16 ethernet0 = &enet0; 20 ethernet0 = &enet0;
17 ethernet1 = &enet1; 21 ethernet1 = &enet1;
18 serial0 = &serial0; 22 serial0 = &serial0;
19 serial1 = &serial1; 23 serial1 = &serial1;
20 pci0 = &pci0; 24 pci0 = &pci0;
21 pci1 = &pci1; 25 pci1 = &pci1;
22 pci2 = &pci2; 26 pci2 = &pci2;
23 }; 27 };
24 28
25 cpus { 29 cpus {
26 #address-cells = <1>; 30 #address-cells = <1>;
27 #size-cells = <0>; 31 #size-cells = <0>;
28 32
29 PowerPC,8315@0 { 33 PowerPC,8315@0 {
30 device_type = "cpu"; 34 device_type = "cpu";
31 reg = <0x0>; 35 reg = <0x0>;
32 d-cache-line-size = <3 36 d-cache-line-size = <32>;
33 i-cache-line-size = <3 37 i-cache-line-size = <32>;
34 d-cache-size = <16384> 38 d-cache-size = <16384>;
35 i-cache-size = <16384> 39 i-cache-size = <16384>;
36 timebase-frequency = < 40 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; 41 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; 42 clock-frequency = <0>; // from bootloader
39 }; 43 };
40 }; 44 };
41 45
42 memory { 46 memory {
43 device_type = "memory"; 47 device_type = "memory";
44 reg = <0x00000000 0x08000000>; 48 reg = <0x00000000 0x08000000>; // 128MB at 0
45 }; 49 };
46 50
47 localbus@e0005000 { 51 localbus@e0005000 {
48 #address-cells = <2>; 52 #address-cells = <2>;
49 #size-cells = <1>; 53 #size-cells = <1>;
50 compatible = "fsl,mpc8315-elbc 54 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
51 reg = <0xe0005000 0x1000>; 55 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>; 56 interrupts = <77 0x8>;
53 interrupt-parent = <&ipic>; 57 interrupt-parent = <&ipic>;
54 58
55 // CS0 and CS1 are swapped whe 59 // CS0 and CS1 are swapped when
56 // booting from nand, but the 60 // booting from nand, but the
57 // addresses are the same. 61 // addresses are the same.
58 ranges = <0x0 0x0 0xfe000000 0 62 ranges = <0x0 0x0 0xfe000000 0x00800000
59 0x1 0x0 0xe0600000 0 63 0x1 0x0 0xe0600000 0x00002000
60 0x2 0x0 0xf0000000 0 64 0x2 0x0 0xf0000000 0x00020000
61 0x3 0x0 0xfa000000 0 65 0x3 0x0 0xfa000000 0x00008000>;
62 66
63 flash@0,0 { 67 flash@0,0 {
64 #address-cells = <1>; 68 #address-cells = <1>;
65 #size-cells = <1>; 69 #size-cells = <1>;
66 compatible = "cfi-flas 70 compatible = "cfi-flash";
67 reg = <0x0 0x0 0x80000 71 reg = <0x0 0x0 0x800000>;
68 bank-width = <2>; 72 bank-width = <2>;
69 device-width = <1>; 73 device-width = <1>;
70 }; 74 };
71 75
72 nand@1,0 { 76 nand@1,0 {
73 #address-cells = <1>; 77 #address-cells = <1>;
74 #size-cells = <1>; 78 #size-cells = <1>;
75 compatible = "fsl,mpc8 79 compatible = "fsl,mpc8315-fcm-nand",
76 "fsl,elbc 80 "fsl,elbc-fcm-nand";
77 reg = <0x1 0x0 0x2000> 81 reg = <0x1 0x0 0x2000>;
78 82
79 u-boot@0 { 83 u-boot@0 {
80 reg = <0x0 0x1 84 reg = <0x0 0x100000>;
81 read-only; 85 read-only;
82 }; 86 };
83 87
84 kernel@100000 { 88 kernel@100000 {
85 reg = <0x10000 89 reg = <0x100000 0x300000>;
86 }; 90 };
87 fs@400000 { 91 fs@400000 {
88 reg = <0x40000 92 reg = <0x400000 0x1c00000>;
89 }; 93 };
90 }; 94 };
91 }; 95 };
92 96
93 immr@e0000000 { 97 immr@e0000000 {
94 #address-cells = <1>; 98 #address-cells = <1>;
95 #size-cells = <1>; 99 #size-cells = <1>;
96 device_type = "soc"; 100 device_type = "soc";
97 compatible = "fsl,mpc8315-immr 101 compatible = "fsl,mpc8315-immr", "simple-bus";
98 ranges = <0 0xe0000000 0x00100 102 ranges = <0 0xe0000000 0x00100000>;
99 reg = <0xe0000000 0x00000200>; 103 reg = <0xe0000000 0x00000200>;
100 bus-frequency = <0>; 104 bus-frequency = <0>;
101 105
102 wdt@200 { 106 wdt@200 {
103 device_type = "watchdo 107 device_type = "watchdog";
104 compatible = "mpc83xx_ 108 compatible = "mpc83xx_wdt";
105 reg = <0x200 0x100>; 109 reg = <0x200 0x100>;
106 }; 110 };
107 111
108 i2c@3000 { 112 i2c@3000 {
109 #address-cells = <1>; 113 #address-cells = <1>;
110 #size-cells = <0>; 114 #size-cells = <0>;
111 cell-index = <0>; 115 cell-index = <0>;
112 compatible = "fsl-i2c" 116 compatible = "fsl-i2c";
113 reg = <0x3000 0x100>; 117 reg = <0x3000 0x100>;
114 interrupts = <14 0x8>; 118 interrupts = <14 0x8>;
115 interrupt-parent = <&i 119 interrupt-parent = <&ipic>;
116 dfsrr; 120 dfsrr;
117 rtc@68 { 121 rtc@68 {
118 compatible = " 122 compatible = "dallas,ds1339";
119 reg = <0x68>; 123 reg = <0x68>;
120 }; 124 };
121 125
122 mcu_pio: mcu@a { 126 mcu_pio: mcu@a {
123 #gpio-cells = 127 #gpio-cells = <2>;
124 compatible = " 128 compatible = "fsl,mc9s08qg8-mpc8315erdb",
125 " 129 "fsl,mcu-mpc8349emitx";
126 reg = <0x0a>; 130 reg = <0x0a>;
127 gpio-controlle 131 gpio-controller;
128 }; 132 };
129 }; 133 };
130 134
131 spi@7000 { 135 spi@7000 {
132 cell-index = <0>; 136 cell-index = <0>;
133 compatible = "fsl,spi" 137 compatible = "fsl,spi";
134 reg = <0x7000 0x1000>; 138 reg = <0x7000 0x1000>;
135 interrupts = <16 0x8>; 139 interrupts = <16 0x8>;
136 interrupt-parent = <&i 140 interrupt-parent = <&ipic>;
137 mode = "cpu"; 141 mode = "cpu";
138 }; 142 };
139 143
140 dma@82a8 { 144 dma@82a8 {
141 #address-cells = <1>; 145 #address-cells = <1>;
142 #size-cells = <1>; 146 #size-cells = <1>;
143 compatible = "fsl,mpc8 147 compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
144 reg = <0x82a8 4>; 148 reg = <0x82a8 4>;
145 ranges = <0 0x8100 0x1 149 ranges = <0 0x8100 0x1a8>;
146 interrupt-parent = <&i 150 interrupt-parent = <&ipic>;
147 interrupts = <71 8>; 151 interrupts = <71 8>;
148 cell-index = <0>; 152 cell-index = <0>;
149 dma-channel@0 { 153 dma-channel@0 {
150 compatible = " 154 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
151 reg = <0 0x80> 155 reg = <0 0x80>;
152 cell-index = < 156 cell-index = <0>;
153 interrupt-pare 157 interrupt-parent = <&ipic>;
154 interrupts = < 158 interrupts = <71 8>;
155 }; 159 };
156 dma-channel@80 { 160 dma-channel@80 {
157 compatible = " 161 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
158 reg = <0x80 0x 162 reg = <0x80 0x80>;
159 cell-index = < 163 cell-index = <1>;
160 interrupt-pare 164 interrupt-parent = <&ipic>;
161 interrupts = < 165 interrupts = <71 8>;
162 }; 166 };
163 dma-channel@100 { 167 dma-channel@100 {
164 compatible = " 168 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
165 reg = <0x100 0 169 reg = <0x100 0x80>;
166 cell-index = < 170 cell-index = <2>;
167 interrupt-pare 171 interrupt-parent = <&ipic>;
168 interrupts = < 172 interrupts = <71 8>;
169 }; 173 };
170 dma-channel@180 { 174 dma-channel@180 {
171 compatible = " 175 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
172 reg = <0x180 0 176 reg = <0x180 0x28>;
173 cell-index = < 177 cell-index = <3>;
174 interrupt-pare 178 interrupt-parent = <&ipic>;
175 interrupts = < 179 interrupts = <71 8>;
176 }; 180 };
177 }; 181 };
178 182
179 usb@23000 { 183 usb@23000 {
180 compatible = "fsl-usb2 184 compatible = "fsl-usb2-dr";
181 reg = <0x23000 0x1000> 185 reg = <0x23000 0x1000>;
182 #address-cells = <1>; 186 #address-cells = <1>;
183 #size-cells = <0>; 187 #size-cells = <0>;
184 interrupt-parent = <&i 188 interrupt-parent = <&ipic>;
185 interrupts = <38 0x8>; 189 interrupts = <38 0x8>;
186 phy_type = "utmi"; 190 phy_type = "utmi";
187 }; 191 };
188 192
189 enet0: ethernet@24000 { 193 enet0: ethernet@24000 {
190 #address-cells = <1>; 194 #address-cells = <1>;
191 #size-cells = <1>; 195 #size-cells = <1>;
192 cell-index = <0>; 196 cell-index = <0>;
193 device_type = "network 197 device_type = "network";
194 model = "eTSEC"; 198 model = "eTSEC";
195 compatible = "gianfar" 199 compatible = "gianfar";
196 reg = <0x24000 0x1000> 200 reg = <0x24000 0x1000>;
197 ranges = <0x0 0x24000 201 ranges = <0x0 0x24000 0x1000>;
198 local-mac-address = [ 202 local-mac-address = [ 00 00 00 00 00 00 ];
199 interrupts = <32 0x8 3 203 interrupts = <32 0x8 33 0x8 34 0x8>;
200 interrupt-parent = <&i 204 interrupt-parent = <&ipic>;
201 tbi-handle = <&tbi0>; 205 tbi-handle = <&tbi0>;
202 phy-handle = < &phy0 > 206 phy-handle = < &phy0 >;
203 fsl,magic-packet; 207 fsl,magic-packet;
204 208
205 mdio@520 { 209 mdio@520 {
206 #address-cells 210 #address-cells = <1>;
207 #size-cells = 211 #size-cells = <0>;
208 compatible = " 212 compatible = "fsl,gianfar-mdio";
209 reg = <0x520 0 213 reg = <0x520 0x20>;
210 214
211 phy0: ethernet 215 phy0: ethernet-phy@0 {
212 interr 216 interrupt-parent = <&ipic>;
213 interr 217 interrupts = <20 0x8>;
214 reg = 218 reg = <0x0>;
215 }; 219 };
216 220
217 phy1: ethernet 221 phy1: ethernet-phy@1 {
218 interr 222 interrupt-parent = <&ipic>;
219 interr 223 interrupts = <19 0x8>;
220 reg = 224 reg = <0x1>;
221 }; 225 };
222 226
223 tbi0: tbi-phy@ 227 tbi0: tbi-phy@11 {
224 reg = 228 reg = <0x11>;
225 device 229 device_type = "tbi-phy";
226 }; 230 };
227 }; 231 };
228 }; 232 };
229 233
230 enet1: ethernet@25000 { 234 enet1: ethernet@25000 {
231 #address-cells = <1>; 235 #address-cells = <1>;
232 #size-cells = <1>; 236 #size-cells = <1>;
233 cell-index = <1>; 237 cell-index = <1>;
234 device_type = "network 238 device_type = "network";
235 model = "eTSEC"; 239 model = "eTSEC";
236 compatible = "gianfar" 240 compatible = "gianfar";
237 reg = <0x25000 0x1000> 241 reg = <0x25000 0x1000>;
238 ranges = <0x0 0x25000 242 ranges = <0x0 0x25000 0x1000>;
239 local-mac-address = [ 243 local-mac-address = [ 00 00 00 00 00 00 ];
240 interrupts = <35 0x8 3 244 interrupts = <35 0x8 36 0x8 37 0x8>;
241 interrupt-parent = <&i 245 interrupt-parent = <&ipic>;
242 tbi-handle = <&tbi1>; 246 tbi-handle = <&tbi1>;
243 phy-handle = < &phy1 > 247 phy-handle = < &phy1 >;
244 fsl,magic-packet; 248 fsl,magic-packet;
245 249
246 mdio@520 { 250 mdio@520 {
247 #address-cells 251 #address-cells = <1>;
248 #size-cells = 252 #size-cells = <0>;
249 compatible = " 253 compatible = "fsl,gianfar-tbi";
250 reg = <0x520 0 254 reg = <0x520 0x20>;
251 255
252 tbi1: tbi-phy@ 256 tbi1: tbi-phy@11 {
253 reg = 257 reg = <0x11>;
254 device 258 device_type = "tbi-phy";
255 }; 259 };
256 }; 260 };
257 }; 261 };
258 262
259 serial0: serial@4500 { 263 serial0: serial@4500 {
260 cell-index = <0>; 264 cell-index = <0>;
261 device_type = "serial" 265 device_type = "serial";
262 compatible = "fsl,ns16 266 compatible = "fsl,ns16550", "ns16550";
263 reg = <0x4500 0x100>; 267 reg = <0x4500 0x100>;
264 clock-frequency = <133 268 clock-frequency = <133333333>;
265 interrupts = <9 0x8>; 269 interrupts = <9 0x8>;
266 interrupt-parent = <&i 270 interrupt-parent = <&ipic>;
267 }; 271 };
268 272
269 serial1: serial@4600 { 273 serial1: serial@4600 {
270 cell-index = <1>; 274 cell-index = <1>;
271 device_type = "serial" 275 device_type = "serial";
272 compatible = "fsl,ns16 276 compatible = "fsl,ns16550", "ns16550";
273 reg = <0x4600 0x100>; 277 reg = <0x4600 0x100>;
274 clock-frequency = <133 278 clock-frequency = <133333333>;
275 interrupts = <10 0x8>; 279 interrupts = <10 0x8>;
276 interrupt-parent = <&i 280 interrupt-parent = <&ipic>;
277 }; 281 };
278 282
279 crypto@30000 { 283 crypto@30000 {
280 compatible = "fsl,sec3 284 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
281 "fsl,sec2 285 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
282 "fsl,sec2 286 "fsl,sec2.0";
283 reg = <0x30000 0x10000 287 reg = <0x30000 0x10000>;
284 interrupts = <11 0x8>; 288 interrupts = <11 0x8>;
285 interrupt-parent = <&i 289 interrupt-parent = <&ipic>;
286 fsl,num-channels = <4> 290 fsl,num-channels = <4>;
287 fsl,channel-fifo-len = 291 fsl,channel-fifo-len = <24>;
288 fsl,exec-units-mask = 292 fsl,exec-units-mask = <0x97c>;
289 fsl,descriptor-types-m 293 fsl,descriptor-types-mask = <0x3a30abf>;
290 }; 294 };
291 295
292 sata@18000 { 296 sata@18000 {
293 compatible = "fsl,mpc8 297 compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
294 reg = <0x18000 0x1000> 298 reg = <0x18000 0x1000>;
295 cell-index = <1>; 299 cell-index = <1>;
296 interrupts = <44 0x8>; 300 interrupts = <44 0x8>;
297 interrupt-parent = <&i 301 interrupt-parent = <&ipic>;
298 }; 302 };
299 303
300 sata@19000 { 304 sata@19000 {
301 compatible = "fsl,mpc8 305 compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
302 reg = <0x19000 0x1000> 306 reg = <0x19000 0x1000>;
303 cell-index = <2>; 307 cell-index = <2>;
304 interrupts = <45 0x8>; 308 interrupts = <45 0x8>;
305 interrupt-parent = <&i 309 interrupt-parent = <&ipic>;
306 }; 310 };
307 311
308 gtm1: timer@500 { 312 gtm1: timer@500 {
309 compatible = "fsl,mpc8 313 compatible = "fsl,mpc8315-gtm", "fsl,gtm";
310 reg = <0x500 0x100>; 314 reg = <0x500 0x100>;
311 interrupts = <90 8 78 315 interrupts = <90 8 78 8 84 8 72 8>;
312 interrupt-parent = <&i 316 interrupt-parent = <&ipic>;
313 clock-frequency = <133 317 clock-frequency = <133333333>;
314 }; 318 };
315 319
316 timer@600 { 320 timer@600 {
317 compatible = "fsl,mpc8 321 compatible = "fsl,mpc8315-gtm", "fsl,gtm";
318 reg = <0x600 0x100>; 322 reg = <0x600 0x100>;
319 interrupts = <91 8 79 323 interrupts = <91 8 79 8 85 8 73 8>;
320 interrupt-parent = <&i 324 interrupt-parent = <&ipic>;
321 clock-frequency = <133 325 clock-frequency = <133333333>;
322 }; 326 };
323 327
324 /* IPIC 328 /* IPIC
325 * interrupts cell = <intr #, 329 * interrupts cell = <intr #, sense>
326 * sense values match linux IO 330 * sense values match linux IORESOURCE_IRQ_* defines:
327 * sense == 8: Level, low asse 331 * sense == 8: Level, low assertion
328 * sense == 2: Edge, high-to-l 332 * sense == 2: Edge, high-to-low change
329 */ 333 */
330 ipic: interrupt-controller@700 334 ipic: interrupt-controller@700 {
331 interrupt-controller; 335 interrupt-controller;
332 #address-cells = <0>; 336 #address-cells = <0>;
333 #interrupt-cells = <2> 337 #interrupt-cells = <2>;
334 reg = <0x700 0x100>; 338 reg = <0x700 0x100>;
335 device_type = "ipic"; 339 device_type = "ipic";
336 }; 340 };
337 341
338 ipic-msi@7c0 { 342 ipic-msi@7c0 {
339 compatible = "fsl,ipic 343 compatible = "fsl,ipic-msi";
340 reg = <0x7c0 0x40>; 344 reg = <0x7c0 0x40>;
341 msi-available-ranges = 345 msi-available-ranges = <0 0x100>;
342 interrupts = <0x43 0x8 346 interrupts = <0x43 0x8
343 0x4 0x8 347 0x4 0x8
344 0x51 0x8 348 0x51 0x8
345 0x52 0x8 349 0x52 0x8
346 0x56 0x8 350 0x56 0x8
347 0x57 0x8 351 0x57 0x8
348 0x58 0x8 352 0x58 0x8
349 0x59 0x8 353 0x59 0x8>;
350 interrupt-parent = < & 354 interrupt-parent = < &ipic >;
351 }; 355 };
352 356
353 pmc: power@b00 { 357 pmc: power@b00 {
354 compatible = "fsl,mpc8 358 compatible = "fsl,mpc8315-pmc", "fsl,mpc8313-pmc",
355 "fsl,mpc8 359 "fsl,mpc8349-pmc";
356 reg = <0xb00 0x100 0xa 360 reg = <0xb00 0x100 0xa00 0x100>;
357 interrupts = <80 8>; 361 interrupts = <80 8>;
358 interrupt-parent = <&i 362 interrupt-parent = <&ipic>;
359 fsl,mpc8313-wakeup-tim 363 fsl,mpc8313-wakeup-timer = <>m1>;
360 }; 364 };
361 }; 365 };
362 366
363 pci0: pci@e0008500 { 367 pci0: pci@e0008500 {
364 interrupt-map-mask = <0xf800 0 368 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
365 interrupt-map = < 369 interrupt-map = <
366 /* IDSEL 0x0E 370 /* IDSEL 0x0E -mini PCI */
367 0x7000 0x0 0x 371 0x7000 0x0 0x0 0x1 &ipic 18 0x8
368 0x7000 0x0 0x 372 0x7000 0x0 0x0 0x2 &ipic 18 0x8
369 0x7000 0x0 0x 373 0x7000 0x0 0x0 0x3 &ipic 18 0x8
370 0x7000 0x0 0x 374 0x7000 0x0 0x0 0x4 &ipic 18 0x8
371 375
372 /* IDSEL 0x0F 376 /* IDSEL 0x0F -mini PCI */
373 0x7800 0x0 0x 377 0x7800 0x0 0x0 0x1 &ipic 17 0x8
374 0x7800 0x0 0x 378 0x7800 0x0 0x0 0x2 &ipic 17 0x8
375 0x7800 0x0 0x 379 0x7800 0x0 0x0 0x3 &ipic 17 0x8
376 0x7800 0x0 0x 380 0x7800 0x0 0x0 0x4 &ipic 17 0x8
377 381
378 /* IDSEL 0x10 382 /* IDSEL 0x10 - PCI slot */
379 0x8000 0x0 0x 383 0x8000 0x0 0x0 0x1 &ipic 48 0x8
380 0x8000 0x0 0x 384 0x8000 0x0 0x0 0x2 &ipic 17 0x8
381 0x8000 0x0 0x 385 0x8000 0x0 0x0 0x3 &ipic 48 0x8
382 0x8000 0x0 0x 386 0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
383 interrupt-parent = <&ipic>; 387 interrupt-parent = <&ipic>;
384 interrupts = <66 0x8>; 388 interrupts = <66 0x8>;
385 bus-range = <0x0 0x0>; 389 bus-range = <0x0 0x0>;
386 ranges = <0x02000000 0 0x90000 390 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
387 0x42000000 0 0x80000 391 0x42000000 0 0x80000000 0x80000000 0 0x10000000
388 0x01000000 0 0x00000 392 0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
389 clock-frequency = <66666666>; 393 clock-frequency = <66666666>;
390 #interrupt-cells = <1>; 394 #interrupt-cells = <1>;
391 #size-cells = <2>; 395 #size-cells = <2>;
392 #address-cells = <3>; 396 #address-cells = <3>;
393 reg = <0xe0008500 0x100 397 reg = <0xe0008500 0x100 /* internal registers */
394 0xe0008300 0x8>; 398 0xe0008300 0x8>; /* config space access registers */
395 compatible = "fsl,mpc8349-pci" 399 compatible = "fsl,mpc8349-pci";
396 device_type = "pci"; 400 device_type = "pci";
397 }; 401 };
398 402
399 pci1: pcie@e0009000 { 403 pci1: pcie@e0009000 {
400 #address-cells = <3>; 404 #address-cells = <3>;
401 #size-cells = <2>; 405 #size-cells = <2>;
402 #interrupt-cells = <1>; 406 #interrupt-cells = <1>;
403 device_type = "pci"; 407 device_type = "pci";
404 compatible = "fsl,mpc8315-pcie 408 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
405 reg = <0xe0009000 0x00001000>; 409 reg = <0xe0009000 0x00001000>;
406 ranges = <0x02000000 0 0xa0000 410 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
407 0x01000000 0 0x00000 411 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
408 bus-range = <0 255>; 412 bus-range = <0 255>;
409 interrupt-map-mask = <0xf800 0 413 interrupt-map-mask = <0xf800 0 0 7>;
410 interrupt-map = <0 0 0 1 &ipic 414 interrupt-map = <0 0 0 1 &ipic 1 8
411 0 0 0 2 &ipic 415 0 0 0 2 &ipic 1 8
412 0 0 0 3 &ipic 416 0 0 0 3 &ipic 1 8
413 0 0 0 4 &ipic 417 0 0 0 4 &ipic 1 8>;
414 clock-frequency = <0>; 418 clock-frequency = <0>;
415 419
416 pcie@0 { 420 pcie@0 {
417 #address-cells = <3>; 421 #address-cells = <3>;
418 #size-cells = <2>; 422 #size-cells = <2>;
419 device_type = "pci"; 423 device_type = "pci";
420 reg = <0 0 0 0 0>; 424 reg = <0 0 0 0 0>;
421 ranges = <0x02000000 0 425 ranges = <0x02000000 0 0xa0000000
422 0x02000000 0 426 0x02000000 0 0xa0000000
423 0 0x10000000 427 0 0x10000000
424 0x01000000 0 428 0x01000000 0 0x00000000
425 0x01000000 0 429 0x01000000 0 0x00000000
426 0 0x00800000 430 0 0x00800000>;
427 }; 431 };
428 }; 432 };
429 433
430 pci2: pcie@e000a000 { 434 pci2: pcie@e000a000 {
431 #address-cells = <3>; 435 #address-cells = <3>;
432 #size-cells = <2>; 436 #size-cells = <2>;
433 #interrupt-cells = <1>; 437 #interrupt-cells = <1>;
434 device_type = "pci"; 438 device_type = "pci";
435 compatible = "fsl,mpc8315-pcie 439 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
436 reg = <0xe000a000 0x00001000>; 440 reg = <0xe000a000 0x00001000>;
437 ranges = <0x02000000 0 0xc0000 441 ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000
438 0x01000000 0 0x00000 442 0x01000000 0 0x00000000 0xd1000000 0 0x00800000>;
439 bus-range = <0 255>; 443 bus-range = <0 255>;
440 interrupt-map-mask = <0xf800 0 444 interrupt-map-mask = <0xf800 0 0 7>;
441 interrupt-map = <0 0 0 1 &ipic 445 interrupt-map = <0 0 0 1 &ipic 2 8
442 0 0 0 2 &ipic 446 0 0 0 2 &ipic 2 8
443 0 0 0 3 &ipic 447 0 0 0 3 &ipic 2 8
444 0 0 0 4 &ipic 448 0 0 0 4 &ipic 2 8>;
445 clock-frequency = <0>; 449 clock-frequency = <0>;
446 450
447 pcie@0 { 451 pcie@0 {
448 #address-cells = <3>; 452 #address-cells = <3>;
449 #size-cells = <2>; 453 #size-cells = <2>;
450 device_type = "pci"; 454 device_type = "pci";
451 reg = <0 0 0 0 0>; 455 reg = <0 0 0 0 0>;
452 ranges = <0x02000000 0 456 ranges = <0x02000000 0 0xc0000000
453 0x02000000 0 457 0x02000000 0 0xc0000000
454 0 0x10000000 458 0 0x10000000
455 0x01000000 0 459 0x01000000 0 0x00000000
456 0x01000000 0 460 0x01000000 0 0x00000000
457 0 0x00800000 461 0 0x00800000>;
458 }; 462 };
459 }; 463 };
460 464
461 leds { 465 leds {
462 compatible = "gpio-leds"; 466 compatible = "gpio-leds";
463 467
464 pwr { 468 pwr {
465 gpios = <&mcu_pio 0 0> 469 gpios = <&mcu_pio 0 0>;
466 default-state = "on"; 470 default-state = "on";
467 }; 471 };
468 472
469 hdd { 473 hdd {
470 gpios = <&mcu_pio 1 0> 474 gpios = <&mcu_pio 1 0>;
471 linux,default-trigger 475 linux,default-trigger = "disk-activity";
472 }; 476 };
473 }; 477 };
474 }; 478 };
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